8t(0<:rockchip,rk3399-evbrockchip,rk3399google,rk3399evb-rev2 +!7Rockchip RK3399 Evaluation Boardaliases=/ethernet@fe300000G/i2c@ff3c0000L/i2c@ff110000Q/i2c@ff120000V/i2c@ff130000[/i2c@ff3d0000`/i2c@ff140000e/i2c@ff150000j/i2c@ff160000o/i2c@ff3e0000t/serial@ff180000|/serial@ff190000/serial@ff1a0000/serial@ff1b0000/serial@ff370000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cpu@0cpuarm,cortex-a53arm,armv8pscidcpu@1cpuarm,cortex-a53arm,armv8pscidcpu@2cpuarm,cortex-a53arm,armv8pscidcpu@3cpuarm,cortex-a53arm,armv8pscidcpu@100cpuarm,cortex-a72arm,armv8psci cpu@101cpuarm,cortex-a72arm,armv8psci display-subsystemrockchip,display-subsystem pmu_a53arm,cortex-a53-pmu pmu_a72arm,cortex-a72-pmu psci arm,psci-1.0smctimerarm,armv8-timer@   xin24m fixed-clockn6.xin24mAamba simple-bus+Ndma-controller@ff6d0000arm,pl330arm,primecellm@ U `apb_pclkgdma-controller@ff6e0000arm,pl330arm,primecelln@ U `apb_pclkpcie@f8000000rockchip,rk3399-pcie laxi-baseapb-base+v G`aclkaclk-perfhclkpm0123syslegacyclient`     ,pcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-38N8( coremgmtmgmt-stickypipepmpclkaclk disabled  (2default@interrupt-controllerJv ethernet@fe300000rockchip,rk3399-gmac0 macirq8ighfjfM`stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac_  stmmacethmokayzinputrgmii2default@  'P(dwmmc@fe3100000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc1@@р M`biuciuciu-driveciu-sample_y reset disableddwmmc@fe3200000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc2@Aр L`biuciuciu-driveciu-sample_z reset disabledsdhci@fe330000+rockchip,rk3399-sdhci-5.1arasan,sdhci-5.13 (zN> N`clk_xinclk_ahb.emmc_cardclockA phy_arasan_okayS]lfusb@fe380000 generic-ehci8`usbhostarbiterutmiusbokayusb@fe3a0000 generic-ohci:`usbhostarbiterutmiusbokayusb@fe3c0000 generic-ehci<`usbhostarbiterutmiusbokayusb@fe3e0000 generic-ohci> `usbhostarbiterutmiusbokayusb@fe800000rockchip,rk3399-dwc3+N0G`ref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk%  usb3-otg disableddwc3 snps,dwc3iotg usb2-phy utmi_wide_ disabledusb@fe900000rockchip,rk3399-dwc3+N0G`ref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk&  usb3-otg disableddwc3 snps,dwc3notg usb2-phy utmi_wide_ disabledinterrupt-controller@fee00000 arm,gic-v3v+NJP  interrupt-controller@fee20000arm,gic-v3-its:ppi-partitionsinterrupt-partition-0I interrupt-partition-1I saradc@ff100000rockchip,rk3399-saradc>RPe`saradcapb_pclk  saradc-apb disabledi2c@ff110000rockchip,rk3399-i2czA> AU `i2cpclk;2default@+ disabledi2c@ff120000rockchip,rk3399-i2czB> BV `i2cpclk#2default@+ disabledi2c@ff130000rockchip,rk3399-i2czC> CW `i2cpclk"2default@ + disabledi2c@ff140000rockchip,rk3399-i2czD> DX `i2cpclk&2default@!+ disabledi2c@ff150000rockchip,rk3399-i2czE> EY `i2cpclk%2default@"+ disabledi2c@ff160000rockchip,rk3399-i2czF> FZ `i2cpclk$2default@#+ disabledserial@ff180000&rockchip,rk3399-uartsnps,dw-apb-uartQ``baudclkapb_pclkcdn2default@$ disabledserial@ff190000&rockchip,rk3399-uartsnps,dw-apb-uartRa`baudclkapb_pclkbdn2default@% disabledserial@ff1a0000&rockchip,rk3399-uartsnps,dw-apb-uartSb`baudclkapb_pclkddn2default@&okayserial@ff1b0000&rockchip,rk3399-uartsnps,dw-apb-uartTc`baudclkapb_pclkedn2default@' disabledspi@ff1c0000(rockchip,rk3399-spirockchip,rk3066-spiG[`spiclkapb_pclkD2default@()*++ disabledspi@ff1d0000(rockchip,rk3399-spirockchip,rk3066-spiH\`spiclkapb_pclk52default@,-./+ disabledspi@ff1e0000(rockchip,rk3399-spirockchip,rk3066-spiI]`spiclkapb_pclk42default@0123+ disabledspi@ff1f0000(rockchip,rk3399-spirockchip,rk3066-spiJ^`spiclkapb_pclkC2default@4567+ disabledspi@ff200000(rockchip,rk3399-spirockchip,rk3066-spi K_`spiclkapb_pclk2default@89:;_+ disabledthermal-zonescpu{d<tripscpu_alert0ppassive=cpu_alert1$passive>cpu_crits criticalcooling-mapsmap0= map1>gpu{d<tripsgpu_alert0$passive?gpu_crits criticalcooling-mapsmap0? tsadc@ff260000rockchip,rk3399-tsadc&azO> qOd`tsadcapb_pclk  tsadc-apbms2initdefaultsleep@@A@ disabled<qos@ffa58000syscon Iqos@ffa5c000syscon Jqos@ffa60080syscon qos@ffa60100syscon qos@ffa60180syscon qos@ffa70000syscon Mqos@ffa70080syscon Nqos@ffa74000syscon@ Kqos@ffa76000syscon` Lqos@ffa90000syscon Oqos@ffa98000syscon Bqos@ffaa0000syscon Pqos@ffaa0080syscon Qqos@ffaa8000syscon Rqos@ffaa8080syscon Sqos@ffab0000syscon Cqos@ffab0080syscon Dqos@ffab8000syscon Eqos@ffac0000syscon Fqos@ffac0080syscon Gqos@ffac8000syscon Tqos@ffac8080syscon Uqos@ffad0000syscon Vqos@ffad8080syscon qos@ffae0000syscon Hpower-management@ff310000&rockchip,rk3399-pmusysconsimple-mfd1power-controller!rockchip,rk3399-power-controller+pd_iep@34"/Bpd_rga@33!/CDpd_vcodec@31/Epd_vdu@32 /FGpd_gpu@35#/Hpd_edp@25lpd_emmc@23/Ipd_gmac@22f/Jpd_sd@27L/Kpd_sdioaudio@28/Lpd_usb3@24/MNpd_vio@15+pd_hdcp@21r/Opd_isp0@19/PQpd_isp1@20/RSpd_tcpc0@RK3399_PD_TCPC0~}pd_tcpc1@RK3399_PD_TCPC1 pd_vo@16+pd_vopb@17/TUpd_vopl@18/Vsyscon@ff320000)rockchip,rk3399-pmugrfsysconsimple-mfd2+dio-domains&rockchip,rk3399-pmu-io-voltage-domain disabledspi@ff350000(rockchip,rk3399-spirockchip,rk3066-spi5WW`spiclkapb_pclk<2default@XYZ[+ disabledserial@ff370000&rockchip,rk3399-uartsnps,dw-apb-uart7WW"`baudclkapb_pclkfdn2default@\ disabledi2c@ff3c0000rockchip,rk3399-i2c<zW > W W `i2cpclk92default@]+ disabledi2c@ff3d0000rockchip,rk3399-i2c=zW > W W `i2cpclk82default@^+ disabledi2c@ff3e0000rockchip,rk3399-i2c>zW > W W `i2cpclk:2default@_+ disabledpwm@ff420000(rockchip,rk3399-pwmrockchip,rk3288-pwmB62default@`W`pwmokaypwm@ff420010(rockchip,rk3399-pwmrockchip,rk3288-pwmB62default@aW`pwm disabledpwm@ff420020(rockchip,rk3399-pwmrockchip,rk3288-pwmB 62default@bW`pwmokaypwm@ff420030(rockchip,rk3399-pwmrockchip,rk3288-pwmB062default@cW`pwmokayiommu@ff650800rockchip,iommue@svpu_mmuA disablediommu@ff660480rockchip,iommu f@f@u vdec_mmuA disablediommu@ff670800rockchip,iommug@*iep_mmuA disabledrga@ff680000rockchip,rk3399-rgah7m`aclkhclksclkjgi  coreaxiahb_!efuse@ff690000rockchip,rk3399-efusei+} `pclk_efusecpu-id@7cpu-leakage@17gpu-leakage@18center-leakage@19cpu-leakage@1alogic-leakage@1bwafer-info@1cpmu-clock-controller@ff750000rockchip,rk3399-pmucruumdANzW>(JWclock-controller@ff760000rockchip,rk3399-cruvmAN`z@BC0>#g/;рxh<4`#Fsyscon@ff770000&rockchip,rk3399-grfsysconsimple-mfdw+io-domains"rockchip,rk3399-io-voltage-domain disabledusb2-phy@e450rockchip,rk3399-usb2phyP{`phyclkA.clk_usbphy0_480mokayhost-port[ linestateokayeotg-port[0ghjotg-bvalidotg-idlinestate disabledusb2-phy@e460rockchip,rk3399-usb2phy`|`phyclkA.clk_usbphy1_480mokayhost-port[ linestateokayeotg-port[0lmootg-bvalidotg-idlinestate disabledphy@f780rockchip,rk3399-emmc-phy$f`emmcclk[okaypcie-phyrockchip,rk3399-pcie-phy`refclk[ phy disabledphy@ff7c0000rockchip,rk3399-typec-phy|~}`tcpdcoretcpdphy-refz~>_L uphyuphy-pipeuphy-tcphym f ~   disableddp-port[usb3-port[phy@ff800000rockchip,rk3399-typec-phy`tcpdcoretcpdphy-refz>_ M uphyuphy-pipeuphy-tcphym f ~   disableddp-port[usb3-port[watchdog@ff848000 snps,dw-wdt|xrktimer@ff850000rockchip,rk3399-timerQhZ `pclktimerspdif@ff870000rockchip,rk3399-spdifBgtx `mclkhclkU2default@h_ disabledi2s@ff880000(rockchip,rk3399-i2srockchip,rk3066-i2sm'ggtxrx`i2s_clki2s_hclkV2default@i_ disabledi2s@ff890000(rockchip,rk3399-i2srockchip,rk3066-i2s(ggtxrx`i2s_clki2s_hclkW2default@j_ disabledi2s@ff8a0000(rockchip,rk3399-i2srockchip,rk3066-i2s)ggtxrx`i2s_clki2s_hclkX_ disabledvop@ff8f0000rockchip,rk3399-vop-lit>wz>ׄ`aclk_vopdclk_vophclk_vopk_  axiahbdclk disabledport+ endpoint@0lxendpoint@1m}endpoint@2nvendpoint@3oziommu@ff8f3f00rockchip,iommu?w vopl_mmu `aclkhclk_A disabledkvop@ff900000rockchip,rk3399-vop-big>vz>ׄ`aclk_vopdclk_vophclk_vopp_  axiahbdclk disabledport+ endpoint@0q|endpoint@1rwendpoint@2suendpoint@3tyiommu@ff903f00rockchip,iommu?v vopb_mmu `aclkhclk_A disabledpiommu@ff914000rockchip,iommu @P+ isp0_mmuA disablediommu@ff924000rockchip,iommu @P, isp1_mmuA disabledhdmi@ff940000rockchip,rk3399-dw-hdmi(tqop`iahbisfrvpllgrfcec_nm disabledportsport+endpoint@0usendpoint@1vnmipi@ff960000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsi- po`refpclkphy_cfggrf_ apbm disabledports+port@0+endpoint@0wrendpoint@1xlmipi@ff968000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsi. qo`refpclkphy_cfggrf_ apbm disabledports+port@0+endpoint@0ytendpoint@1zoedp@ff970000rockchip,rk3399-edp jlo `dppclkgrf2default@{_ dpm disabledports+port@0+endpoint@0|qendpoint@1}mgpu@ff9a0000#rockchip,rk3399-maliarm,mali-t8600 gpujobmmu_# disabledpinctrlrockchip,rk3399-pinctrlmd+Ngpio0@ff720000rockchip,gpio-bankrWJvgpio1@ff730000rockchip,gpio-banksWJvgpio2@ff780000rockchip,gpio-bankxPJvgpio3@ff788000rockchip,gpio-bankxQJvgpio4@ff790000rockchip,gpio-bankyRJvpcfg-pull-up*pcfg-pull-down7pcfg-pull-noneF~pcfg-pull-none-12maFS pcfg-pull-up-8ma*Spcfg-pull-down-4ma7Spcfg-pull-up-2ma*Spcfg-pull-down-12ma7S pcfg-pull-none-13maFS clockclk-32kb~edpedp-hpdb~{gmacrgmii-pinsb~ ~  ~ ~~~~~~rmii-pinsb ~  ~ ~ ~~~~i2c0i2c0-xfer b~~]i2c1i2c1-xfer b~~i2c2i2c2-xfer bi2c3i2c3-xfer b~~ i2c4i2c4-xfer b ~ ~^i2c5i2c5-xfer b ~ ~!i2c6i2c6-xfer b ~ ~"i2c7i2c7-xfer b~~#i2c8i2c8-xfer b~~_i2s0i2s0-8ch-busb~~~~~~~~~ii2s1i2s1-2ch-busPb~~~~~jsdio0sdio0-bus1bsdio0-bus4@bsdio0-cmdbsdio0-clkb~sdio0-cdbsdio0-pwrbsdio0-bkpwrbsdio0-wpbsdio0-intbsdmmcsdmmc-bus1bsdmmc-bus4@b   sdmmc-clkb ~sdmmc-cmdb sdmmc-cdbsdmmc-wpbsleepap-pwroffb~ddrio-pwroffb~spdifspdif-busb~hspdif-bus-1b~spi0spi0-clkb(spi0-cs0b+spi0-cs1bspi0-txb)spi0-rxb*spi1spi1-clkb ,spi1-cs0b /spi1-rxb.spi1-txb-spi2spi2-clkb 0spi2-cs0b 3spi2-rxb 2spi2-txb 1spi3spi3-clkbXspi3-cs0b[spi3-rxbZspi3-txbYspi4spi4-clkb4spi4-cs0b7spi4-rxb6spi4-txb5spi5spi5-clkb8spi5-cs0b;spi5-rxb:spi5-txb9tsadcotp-gpiob~@otp-outb~Auart0uart0-xfer b~$uart0-ctsb~uart0-rtsb~uart1uart1-xfer b  ~%uart2auart2a-xfer b ~uart2buart2b-xfer b~uart2cuart2c-xfer b~&uart3uart3-xfer b~'uart3-ctsb~uart3-rtsb~uart4uart4-xfer b~\uarthdcpuarthdcp-xfer b~pwm0pwm0-pinb~`vop0-pwm-pinb~pwm1pwm1-pinb~avop1-pwm-pinb~pwm2pwm2-pinb~bpwm3apwm3a-pinb~cpwm3bpwm3b-pinb~hdmihdmi-i2c-xfer b~~hdmi-cecb~pciepci-clkreqn-cpmb~pci-clkreqnb-cpmb~pmicpmic-int-lbpmic-dvs2busb2vcc5v0-host-enb~backlightpwm-backlightp  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  aexternal-gmac-clock fixed-clocksY@ .clkin_gmacAvdd-centerpwm-regulatora vdd_center 5\okayvcc3v3-sysregulator-fixed vcc3v3_sys2Z2Zvcc5v0-sysregulator-fixed vcc5v0_sysLK@LK@vcc5v0-host-regulatorregulator-fixed 2default@ vcc5v0_host%evcc-phy-regulatorregulator-fixedvcc_phy compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4cpudevice_typeregenable-method#cooling-cellsclocksdynamic-power-coefficientphandleportsinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsranges#dma-cellsclock-namesreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapphysphy-namesresetsreset-namesstatusep-gpiosnum-lanespinctrl-namespinctrl-0interrupt-controllerpower-domainsrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaymax-frequencyfifo-deptharasan,soc-ctl-sysconassigned-clock-ratesbus-widthmmc-hs400-1_8vmmc-hs400-enhanced-strobenon-removabledr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirkmsi-controlleraffinity#io-channel-cellsreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#power-domain-cellspm_qos#pwm-cells#iommu-cells#reset-cells#phy-cellsrockchip,typec-conn-dirrockchip,usb3tousb2-enrockchip,external-psmrockchip,pipe-statusdmasdma-namesiommusremote-endpointrockchip,disable-mmu-resetrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsbrightness-levelsdefault-brightness-levelenable-gpiospwmsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onenable-active-highvin-supply