8( ',Qualcomm Technologies, Inc. SDM845 MTP2qcom,sdm845-mtpchosenmemory@80000000=memoryIreserved-memory Mmemory@85fc0000ITmemory@85fe0000 2qcom,cmd-dbITmemory@86000000I T[ memory@86200000I Tcpus cpu@0=cpu 2qcom,kryo385Icpsciql2-cache2cacheq[l3-cache2cache[cpu@100=cpu 2qcom,kryo385Icpsciql2-cache2cacheq[cpu@200=cpu 2qcom,kryo385Icpsciql2-cache2cacheq[cpu@300=cpu 2qcom,kryo385Icpsciql2-cache2cacheq[cpu@400=cpu 2qcom,kryo385Icpsciql2-cache2cacheq[cpu@500=cpu 2qcom,kryo385Icpsciql2-cache2cacheq[cpu@600=cpu 2qcom,kryo385Icpsciq l2-cache2cacheq[ cpu@700=cpu 2qcom,kryo385Icpsciq l2-cache2cacheq[ timer2arm,armv8-timer0clocksxo-board 2fixed-clockI xo_boardsleep-clk 2fixed-clockhwlock2qcom,tcsr-mutex [ smem 2qcom,smem  psci 2arm,psci-1.0jsmcsoc M 2simple-busclock-controller@1000002qcom,gcc-sdm845Isyscon@1f400002sysconI[ pinctrl@34000002qcom,sdm845-pinctrlI@  %:spmi@c4400002qcom,spmi-pmic-arb(I D ``p @`Kcorechnlsobsrvrintrcnfg Uperiph_irq em %:zmailbox@179900002qcom,sdm845-apss-sharedIinterrupt-controller@17a00000 2arm,gic-v3 M:%I  [gic-its@17a400002arm,gic-v3-itsI disabledtimer@17c90000 M2arm,armv7-timer-memIframe@17ca0000Iframe@17cc0000 I disabledframe@17cd0000 I disabledframe@17ce0000 I disabledframe@17cf0000 I disabledframe@17d00000 I disabledframe@17d10000 I disabled interrupt-parent#address-cells#size-cellsmodelcompatibledevice_typeregrangesno-mapphandleenable-methodnext-level-cacheinterrupts#clock-cellsclock-frequencyclock-output-namessyscon#hwlock-cellsmemory-regionhwlocks#reset-cells#power-domain-cellsgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellsreg-namesinterrupt-namesqcom,eeqcom,channelcell-index#mbox-cellsmsi-controller#msi-cellsstatusframe-number