//===- TableGen'erated file -------------------------------------*- C++ -*-===//
//
// Assembly Writer Source Fragment
//
// Automatically generated file, do not edit!
//
//===----------------------------------------------------------------------===//
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
static const unsigned OpInfo[] = {
0U, // PHI
0U, // INLINEASM
0U, // DBG_LABEL
0U, // EH_LABEL
0U, // GC_LABEL
0U, // KILL
0U, // EXTRACT_SUBREG
0U, // INSERT_SUBREG
0U, // IMPLICIT_DEF
0U, // SUBREG_TO_REG
0U, // COPY_TO_REGCLASS
1U, // DBG_VALUE
67108875U, // ADCSSri
67108875U, // ADCSSrr
67108875U, // ADCSSrs
134750225U, // ADCri
134758417U, // ADCrr
202375185U, // ADCrs
135815189U, // ADDSri
135815189U, // ADDSrr
202924053U, // ADDSrs
134750234U, // ADDri
134758426U, // ADDrr
202375194U, // ADDrs
69206046U, // ADJCALLSTACKDOWN
69206066U, // ADJCALLSTACKUP
134750276U, // ANDri
134758468U, // ANDrr
202375236U, // ANDrs
271056968U, // ATOMIC_CMP_SWAP_I16
271581256U, // ATOMIC_CMP_SWAP_I32
272105544U, // ATOMIC_CMP_SWAP_I8
272629832U, // ATOMIC_LOAD_ADD_I16
273154120U, // ATOMIC_LOAD_ADD_I32
273678408U, // ATOMIC_LOAD_ADD_I8
274202696U, // ATOMIC_LOAD_AND_I16
274726984U, // ATOMIC_LOAD_AND_I32
275251272U, // ATOMIC_LOAD_AND_I8
275775560U, // ATOMIC_LOAD_NAND_I16
276299848U, // ATOMIC_LOAD_NAND_I32
276824136U, // ATOMIC_LOAD_NAND_I8
277348424U, // ATOMIC_LOAD_OR_I16
277872712U, // ATOMIC_LOAD_OR_I32
278397000U, // ATOMIC_LOAD_OR_I8
278921288U, // ATOMIC_LOAD_SUB_I16
279445576U, // ATOMIC_LOAD_SUB_I32
279969864U, // ATOMIC_LOAD_SUB_I8
280494152U, // ATOMIC_LOAD_XOR_I16
281018440U, // ATOMIC_LOAD_XOR_I32
281542728U, // ATOMIC_LOAD_XOR_I8
282067016U, // ATOMIC_SWAP_I16
282591304U, // ATOMIC_SWAP_I32
283115592U, // ATOMIC_SWAP_I8
69206089U, // B
135815244U, // BFC
135815248U, // BFI
134750292U, // BICri
134758484U, // BICrr
202375252U, // BICrs
337141848U, // BKPT
402653277U, // BL
69206113U, // BLX
69206113U, // BLXr9
337150054U, // BL_pred
402653277U, // BLr9
337150054U, // BLr9_pred
69206121U, // BMOVPCRX
69206121U, // BMOVPCRXr9
69206142U, // BRIND
67108994U, // BR_JTadd
485007499U, // BR_JTm
82362516U, // BR_JTr
69206173U, // BX
337141933U, // BXJ
552599729U, // BX_RET
69206173U, // BXr9
337141940U, // Bcc
620290230U, // CDP
687866042U, // CDP2
193U, // CLREX
739795143U, // CLZ
739795147U, // CMNzri
739795147U, // CMNzrr
806904011U, // CMNzrs
739795151U, // CMPri
739795151U, // CMPrr
806904015U, // CMPrs
739795151U, // CMPzri
739795151U, // CMPzrr
806904015U, // CMPzrs
872415304U, // CONSTPOOL_ENTRY
939524307U, // CPS
337141975U, // DBG
219U, // DMBish
227U, // DMBishst
237U, // DMBnsh
245U, // DMBnshst
255U, // DMBosh
263U, // DMBoshst
273U, // DMBst
280U, // DSBish
288U, // DSBishst
298U, // DSBnsh
306U, // DSBnshst
316U, // DSBosh
324U, // DSBoshst
334U, // DSBst
134750549U, // EORri
134758741U, // EORrr
202375509U, // EORrs
755556697U, // FCONSTD
756080985U, // FCONSTS
555221342U, // FMSTAT
355U, // ISBsy
85983591U, // Int_MemBarrierV6
372U, // Int_MemBarrierV7
86507879U, // Int_SyncBarrierV6
376U, // Int_SyncBarrierV7
87032188U, // Int_eh_sjlj_setjmp
221831558U, // LDC2L_OFFSET
825819526U, // LDC2L_OPTION
221839750U, // LDC2L_POST
221831558U, // LDC2L_PRE
217653638U, // LDC2_OFFSET
821633414U, // LDC2_OPTION
217653638U, // LDC2_POST
217653638U, // LDC2_PRE
221831563U, // LDCL_OFFSET
825819531U, // LDCL_OPTION
221839755U, // LDCL_POST
221831563U, // LDCL_PRE
217653643U, // LDC_OFFSET
821633419U, // LDC_OPTION
217653643U, // LDC_POST
217653643U, // LDC_PRE
1027686799U, // LDM
1027686799U, // LDM_RET
806904211U, // LDR
806904215U, // LDRB
202924444U, // LDRBT
202924439U, // LDRB_POST
202924439U, // LDRB_PRE
202924450U, // LDRD
605577634U, // LDRD_POST
605577634U, // LDRD_PRE
739795367U, // LDREX
739795373U, // LDREXB
135815604U, // LDREXD
739795387U, // LDREXH
806904258U, // LDRH
202924487U, // LDRHT
202924482U, // LDRH_POST
202924482U, // LDRH_PRE
806904269U, // LDRSB
202924499U, // LDRSBT
202924493U, // LDRSB_POST
202924493U, // LDRSB_PRE
806904282U, // LDRSH
202924512U, // LDRSHT
202924506U, // LDRSH_POST
202924506U, // LDRSH_PRE
202924519U, // LDRT
202924435U, // LDR_POST
202924435U, // LDR_PRE
806904211U, // LDRcp
1095238124U, // LEApcrel
1095762412U, // LEApcrelJT
620290546U, // MCR
671105526U, // MCR2
217637373U, // MCRR
671105538U, // MCRR2
827851274U, // MLA
806904334U, // MLS
135815698U, // MOVCCi
135815698U, // MOVCCr
202924562U, // MOVCCs
559940114U, // MOVPCLR
69206164U, // MOVPCRX
135815702U, // MOVTi16
761881106U, // MOVi
739795483U, // MOVi16
739795474U, // MOVi2pieces
739795483U, // MOVi32imm
761790994U, // MOVr
761790994U, // MOVrx
827949586U, // MOVs
739795488U, // MOVsra_flag
739795488U, // MOVsrl_flag
620290597U, // MRC
671105577U, // MRC2
217637424U, // MRRC
671105589U, // MRRC2
337142333U, // MRS
337142333U, // MRSsys
359686721U, // MSR
359768641U, // MSRi
360211009U, // MSRsys
360292929U, // MSRsysi
134758981U, // MUL
761881161U, // MVNi
761791049U, // MVNr
827949641U, // MVNs
538968653U, // NOP
134750801U, // ORRri
134758993U, // ORRrr
202375761U, // ORRrs
1166017109U, // PICADD
1233650261U, // PICLDR
1234174549U, // PICLDRB
1234698837U, // PICLDRH
1235223125U, // PICLDRSB
1235747413U, // PICLDRSH
1236271701U, // PICSTR
1236795989U, // PICSTRB
1237320277U, // PICSTRH
806904407U, // PKHBT
806904413U, // PKHTB
67109475U, // PLDWi
471859818U, // PLDWr
67109488U, // PLDi
471859830U, // PLDr
67109499U, // PLIi
471859841U, // PLIr
135815814U, // QADD
135815819U, // QADD16
135815826U, // QADD8
135815832U, // QASX
135815837U, // QDADD
135815843U, // QDSUB
135815849U, // QSAX
135815854U, // QSUB
135815859U, // QSUB16
135815866U, // QSUB8
739795648U, // RBIT
739795653U, // REV
739795657U, // REV16
739795663U, // REVSH
1008222933U, // RFE
1008222933U, // RFEW
135815897U, // RSBSri
202924761U, // RSBSrs
134750942U, // RSBri
202375902U, // RSBrs
67109602U, // RSCSri
67109602U, // RSCSrs
134750952U, // RSCri
202375912U, // RSCrs
135815916U, // SADD16
135815923U, // SADD8
135815929U, // SASX
67109630U, // SBCSSri
67109630U, // SBCSSrr
67109630U, // SBCSSrs
134750980U, // SBCri
134759172U, // SBCrr
202375940U, // SBCrs
806904584U, // SBFX
135815949U, // SEL
785U, // SETENDBE
795U, // SETENDLE
538968869U, // SEV
135815977U, // SHADD16
135815985U, // SHADD8
135815992U, // SHASX
135815998U, // SHSAX
135816004U, // SHSUB16
135816012U, // SHSUB8
337142611U, // SMC
806904663U, // SMLABB
806904670U, // SMLABT
806904677U, // SMLAD
806904683U, // SMLADX
827851634U, // SMLAL
806904696U, // SMLALBB
806904704U, // SMLALBT
806904712U, // SMLALD
806904719U, // SMLALDX
806904727U, // SMLALTB
806904735U, // SMLALTT
806904743U, // SMLATB
806904750U, // SMLATT
806904757U, // SMLAWB
806904764U, // SMLAWT
806904771U, // SMLSD
806904777U, // SMLSDX
806904784U, // SMLSLD
806904791U, // SMLSLDX
806904799U, // SMMLA
806904805U, // SMMLAR
806904812U, // SMMLS
806904818U, // SMMLSR
135816185U, // SMMUL
135816191U, // SMMULR
135816198U, // SMUAD
135816204U, // SMUADX
135816211U, // SMULBB
135816218U, // SMULBT
827851809U, // SMULL
135816231U, // SMULTB
135816238U, // SMULTT
135816245U, // SMULWB
135816252U, // SMULWT
135816259U, // SMUSD
135816265U, // SMUSDX
1036534864U, // SRS
1037059152U, // SRSW
135816276U, // SSAT16
806904923U, // SSATasr
806904923U, // SSATlsl
135816288U, // SSAX
135816293U, // SSUB16
135816300U, // SSUB8
221832306U, // STC2L_OFFSET
825820274U, // STC2L_OPTION
221840498U, // STC2L_POST
221832306U, // STC2L_PRE
217654386U, // STC2_OFFSET
821634162U, // STC2_OPTION
217654386U, // STC2_POST
217654386U, // STC2_PRE
221832311U, // STCL_OFFSET
825820279U, // STCL_OPTION
221840503U, // STCL_POST
221832311U, // STCL_PRE
217654391U, // STC_OFFSET
821634167U, // STC_OPTION
217654391U, // STC_POST
217654391U, // STC_PRE
1027687547U, // STM
806904959U, // STR
806904963U, // STRB
202900616U, // STRBT
202900611U, // STRB_POST
202900611U, // STRB_PRE
202925198U, // STRD
605553806U, // STRD_POST
605553806U, // STRD_PRE
135816339U, // STREX
135816345U, // STREXB
806904992U, // STREXD
135816359U, // STREXH
806905006U, // STRH
202900659U, // STRHT
202900654U, // STRH_POST
202900654U, // STRH_PRE
202900665U, // STRT
202900607U, // STR_POST
202900607U, // STR_PRE
135816382U, // SUBSri
135816382U, // SUBSrr
202925246U, // SUBSrs
134751427U, // SUBri
134759619U, // SUBrr
202376387U, // SUBrs
337142983U, // SVC
135816395U, // SWP
135816399U, // SWPB
135816404U, // SXTAB16rr
806905044U, // SXTAB16rr_rot
135816412U, // SXTABrr
806905052U, // SXTABrr_rot
135816418U, // SXTAHrr
806905058U, // SXTAHrr_rot
739796200U, // SXTB16r
135816424U, // SXTB16r_rot
739796207U, // SXTBr
135816431U, // SXTBr_rot
739796212U, // SXTHr
135816436U, // SXTHr_rot
739796217U, // TEQri
739796217U, // TEQrr
806905081U, // TEQrs
1277U, // TPsoft
538969360U, // TRAP
739796245U, // TSTri
739796245U, // TSTrr
806905109U, // TSTrs
135816473U, // UADD16
135816480U, // UADD8
135816486U, // UASX
806905131U, // UBFX
135816496U, // UHADD16
135816504U, // UHADD8
135816511U, // UHASX
135816517U, // UHSAX
135816523U, // UHSUB16
135816531U, // UHSUB8
806905178U, // UMAAL
827852128U, // UMLAL
827852134U, // UMULL
135816556U, // UQADD16
135816564U, // UQADD8
135816571U, // UQASX
135816577U, // UQSAX
135816583U, // UQSUB16
135816591U, // UQSUB8
135816598U, // USAD8
806905244U, // USADA8
135816611U, // USAT16
806905258U, // USATasr
806905258U, // USATlsl
135816623U, // USAX
135816628U, // USUB16
135816635U, // USUB8
135816641U, // UXTAB16rr
806905281U, // UXTAB16rr_rot
135816649U, // UXTABrr
806905289U, // UXTABrr_rot
135816655U, // UXTAHrr
806905295U, // UXTAHrr_rot
739796437U, // UXTB16r
135816661U, // UXTB16r_rot
739796444U, // UXTBr
135816668U, // UXTBr_rot
739796449U, // UXTHr
135816673U, // UXTHr_rot
836257254U, // VABALsv2i64
836781542U, // VABALsv4i32
837305830U, // VABALsv8i16
837830118U, // VABALuv2i64
838354406U, // VABALuv4i32
838878694U, // VABALuv8i16
837305836U, // VABAsv16i8
836257260U, // VABAsv2i32
836781548U, // VABAsv4i16
836257260U, // VABAsv4i32
836781548U, // VABAsv8i16
837305836U, // VABAsv8i8
838878700U, // VABAuv16i8
837830124U, // VABAuv2i32
838354412U, // VABAuv4i16
837830124U, // VABAuv4i32
838354412U, // VABAuv8i16
838878700U, // VABAuv8i8
165152241U, // VABDLsv2i64
165676529U, // VABDLsv4i32
166200817U, // VABDLsv8i16
166725105U, // VABDLuv2i64
167249393U, // VABDLuv4i32
167773681U, // VABDLuv8i16
152102391U, // VABDfd
152102391U, // VABDfq
166200823U, // VABDsv16i8
165152247U, // VABDsv2i32
165676535U, // VABDsv4i16
165152247U, // VABDsv4i32
165676535U, // VABDsv8i16
166200823U, // VABDsv8i8
167773687U, // VABDuv16i8
166725111U, // VABDuv2i32
167249399U, // VABDuv4i16
166725111U, // VABDuv4i32
167249399U, // VABDuv8i16
167773687U, // VABDuv8i8
755557884U, // VABSD
756082172U, // VABSS
756082172U, // VABSfd
756082172U, // VABSfd_sfp
756082172U, // VABSfq
770180604U, // VABSv16i8
769132028U, // VABSv2i32
769656316U, // VABSv4i16
769132028U, // VABSv4i32
769656316U, // VABSv8i16
770180604U, // VABSv8i8
152102401U, // VACGEd
152102401U, // VACGEq
152102407U, // VACGTd
152102407U, // VACGTq
151578125U, // VADDD
168298002U, // VADDHNv2i32
168822290U, // VADDHNv4i16
169346578U, // VADDHNv8i8
165152281U, // VADDLsv2i64
165676569U, // VADDLsv4i32
166200857U, // VADDLsv8i16
166725145U, // VADDLuv2i64
167249433U, // VADDLuv4i32
167773721U, // VADDLuv8i16
152102413U, // VADDS
165152287U, // VADDWsv2i64
165676575U, // VADDWsv4i32
166200863U, // VADDWsv8i16
166725151U, // VADDWuv2i64
167249439U, // VADDWuv4i32
167773727U, // VADDWuv8i16
152102413U, // VADDfd
152102413U, // VADDfd_sfp
152102413U, // VADDfq
169870861U, // VADDv16i8
168297997U, // VADDv1i64
168822285U, // VADDv2i32
168297997U, // VADDv2i64
169346573U, // VADDv4i16
168822285U, // VADDv4i32
169346573U, // VADDv8i16
169870861U, // VADDv8i8
135816741U, // VANDd
135816741U, // VANDq
135816746U, // VBICd
135816746U, // VBICq
806905391U, // VBIFd
806905391U, // VBIFq
806905396U, // VBITd
806905396U, // VBITq
806905401U, // VBSLd
806905401U, // VBSLq
152102462U, // VCEQfd
152102462U, // VCEQfq
169870910U, // VCEQv16i8
168822334U, // VCEQv2i32
169346622U, // VCEQv4i16
168822334U, // VCEQv4i32
169346622U, // VCEQv8i16
169870910U, // VCEQv8i8
773850686U, // VCEQzv16i8
756082238U, // VCEQzv2f32
772802110U, // VCEQzv2i32
756082238U, // VCEQzv4f32
773326398U, // VCEQzv4i16
772802110U, // VCEQzv4i32
773326398U, // VCEQzv8i16
773850686U, // VCEQzv8i8
152102467U, // VCGEfd
152102467U, // VCGEfq
166200899U, // VCGEsv16i8
165152323U, // VCGEsv2i32
165676611U, // VCGEsv4i16
165152323U, // VCGEsv4i32
165676611U, // VCGEsv8i16
166200899U, // VCGEsv8i8
167773763U, // VCGEuv16i8
166725187U, // VCGEuv2i32
167249475U, // VCGEuv4i16
166725187U, // VCGEuv4i32
167249475U, // VCGEuv8i16
167773763U, // VCGEuv8i8
770180675U, // VCGEzv16i8
756082243U, // VCGEzv2f32
769132099U, // VCGEzv2i32
756082243U, // VCGEzv4f32
769656387U, // VCGEzv4i16
769132099U, // VCGEzv4i32
769656387U, // VCGEzv8i16
770180675U, // VCGEzv8i8
152102472U, // VCGTfd
152102472U, // VCGTfq
166200904U, // VCGTsv16i8
165152328U, // VCGTsv2i32
165676616U, // VCGTsv4i16
165152328U, // VCGTsv4i32
165676616U, // VCGTsv8i16
166200904U, // VCGTsv8i8
167773768U, // VCGTuv16i8
166725192U, // VCGTuv2i32
167249480U, // VCGTuv4i16
166725192U, // VCGTuv4i32
167249480U, // VCGTuv8i16
167773768U, // VCGTuv8i8
770180680U, // VCGTzv16i8
756082248U, // VCGTzv2f32
769132104U, // VCGTzv2i32
756082248U, // VCGTzv4f32
769656392U, // VCGTzv4i16
769132104U, // VCGTzv4i32
769656392U, // VCGTzv8i16
770180680U, // VCGTzv8i8
770180685U, // VCLEzv16i8
756082253U, // VCLEzv2f32
769132109U, // VCLEzv2i32
756082253U, // VCLEzv4f32
769656397U, // VCLEzv4i16
769132109U, // VCLEzv4i32
769656397U, // VCLEzv8i16
770180685U, // VCLEzv8i8
770180690U, // VCLSv16i8
769132114U, // VCLSv2i32
769656402U, // VCLSv4i16
769132114U, // VCLSv4i32
769656402U, // VCLSv8i16
770180690U, // VCLSv8i8
770180695U, // VCLTzv16i8
756082263U, // VCLTzv2f32
769132119U, // VCLTzv2i32
756082263U, // VCLTzv4f32
769656407U, // VCLTzv4i16
769132119U, // VCLTzv4i32
769656407U, // VCLTzv8i16
770180695U, // VCLTzv8i8
773850716U, // VCLZv16i8
772802140U, // VCLZv2i32
773326428U, // VCLZv4i16
772802140U, // VCLZv4i32
773326428U, // VCLZv8i16
773850716U, // VCLZv8i8
755557985U, // VCMPD
755557990U, // VCMPED
756082278U, // VCMPES
352962150U, // VCMPEZD
353486438U, // VCMPEZS
756082273U, // VCMPS
352962145U, // VCMPZD
353486433U, // VCMPZS
774399596U, // VCNTd
774399596U, // VCNTq
774899313U, // VCVTBHS
775423601U, // VCVTBSH
775947895U, // VCVTDS
776472183U, // VCVTSD
774899324U, // VCVTTHS
775423612U, // VCVTTSH
777119351U, // VCVTf2sd
777119351U, // VCVTf2sd_sfp
777119351U, // VCVTf2sq
777643639U, // VCVTf2ud
777643639U, // VCVTf2ud_sfp
777643639U, // VCVTf2uq
173074039U, // VCVTf2xsd
173074039U, // VCVTf2xsq
173598327U, // VCVTf2xud
173598327U, // VCVTf2xuq
778167927U, // VCVTs2fd
778167927U, // VCVTs2fd_sfp
778167927U, // VCVTs2fq
778692215U, // VCVTu2fd
778692215U, // VCVTu2fd_sfp
778692215U, // VCVTu2fq
174122615U, // VCVTxs2fd
174122615U, // VCVTxs2fq
174646903U, // VCVTxu2fd
174646903U, // VCVTxu2fq
151578242U, // VDIVD
152102530U, // VDIVS
779118215U, // VDUP16d
779118215U, // VDUP16q
779642503U, // VDUP32d
779642503U, // VDUP32q
774399623U, // VDUP8d
774399623U, // VDUP8q
175138439U, // VDUPLN16d
175138439U, // VDUPLN16q
175662727U, // VDUPLN32d
175662727U, // VDUPLN32q
170419847U, // VDUPLN8d
170419847U, // VDUPLN8q
175662727U, // VDUPLNfd
175662727U, // VDUPLNfq
779642503U, // VDUPfd
779642503U, // VDUPfdf
779642503U, // VDUPfq
779642503U, // VDUPfqf
135816844U, // VEORd
135816844U, // VEORq
846227089U, // VEXTd16
846751377U, // VEXTd32
841508497U, // VEXTd8
846751377U, // VEXTdf
846227089U, // VEXTq16
846751377U, // VEXTq32
841508497U, // VEXTq8
846751377U, // VEXTqf
175661401U, // VGETLNi32
165675353U, // VGETLNs16
166199641U, // VGETLNs8
167248217U, // VGETLNu16
167772505U, // VGETLNu8
166200982U, // VHADDsv16i8
165152406U, // VHADDsv2i32
165676694U, // VHADDsv4i16
165152406U, // VHADDsv4i32
165676694U, // VHADDsv8i16
166200982U, // VHADDsv8i8
167773846U, // VHADDuv16i8
166725270U, // VHADDuv2i32
167249558U, // VHADDuv4i16
166725270U, // VHADDuv4i32
167249558U, // VHADDuv8i16
167773846U, // VHADDuv8i8
166200988U, // VHSUBsv16i8
165152412U, // VHSUBsv2i32
165676700U, // VHSUBsv4i16
165152412U, // VHSUBsv4i32
165676700U, // VHSUBsv8i16
166200988U, // VHSUBsv8i8
167773852U, // VHSUBuv16i8
166725276U, // VHSUBuv2i32
167249564U, // VHSUBuv4i16
166725276U, // VHSUBuv4i32
167249564U, // VHSUBuv8i16
167773852U, // VHSUBuv8i8
243295906U, // VLD1d16
1317037730U, // VLD1d16Q
1384146594U, // VLD1d16T
243820194U, // VLD1d32
1317562018U, // VLD1d32Q
1384670882U, // VLD1d32T
244344482U, // VLD1d64
244868770U, // VLD1d8
1318610594U, // VLD1d8Q
1385719458U, // VLD1d8T
243820194U, // VLD1df
242353826U, // VLD1q16
242878114U, // VLD1q32
245499554U, // VLD1q64
237635234U, // VLD1q8
242878114U, // VLD1qf
1451255463U, // VLD2LNd16
1451779751U, // VLD2LNd32
1452828327U, // VLD2LNd8
1451255463U, // VLD2LNq16a
1451255463U, // VLD2LNq16b
1451779751U, // VLD2LNq32a
1451779751U, // VLD2LNq32b
645949095U, // VLD2d16
645949095U, // VLD2d16D
646473383U, // VLD2d32
646473383U, // VLD2d32D
646997666U, // VLD2d64
647521959U, // VLD2d8
647521959U, // VLD2d8D
1317037735U, // VLD2q16
1317562023U, // VLD2q32
1318610599U, // VLD2q8
1518364332U, // VLD3LNd16
1518888620U, // VLD3LNd32
1519937196U, // VLD3LNd8
1518364332U, // VLD3LNq16a
1518364332U, // VLD3LNq16b
1518888620U, // VLD3LNq32a
1518888620U, // VLD3LNq32b
1384146604U, // VLD3d16
1384670892U, // VLD3d32
1385195170U, // VLD3d64
1385719468U, // VLD3d8
1317037740U, // VLD3q16a
1317037740U, // VLD3q16b
1317562028U, // VLD3q32a
1317562028U, // VLD3q32b
1318610604U, // VLD3q8a
1318610604U, // VLD3q8b
1585473201U, // VLD4LNd16
1585997489U, // VLD4LNd32
1587046065U, // VLD4LNd8
1585473201U, // VLD4LNq16a
1585473201U, // VLD4LNq16b
1585997489U, // VLD4LNq32a
1585997489U, // VLD4LNq32b
1317037745U, // VLD4d16
1317562033U, // VLD4d32
1318086306U, // VLD4d64
1318610609U, // VLD4d8
1451255473U, // VLD4q16a
1451255473U, // VLD4q16b
1451779761U, // VLD4q32a
1451779761U, // VLD4q32b
1452828337U, // VLD4q8a
1452828337U, // VLD4q8b
1610614454U, // VLDMD
1610614454U, // VLDMS
178284219U, // VLDRD
135931584U, // VLDRQ
175662779U, // VLDRS
152102599U, // VMAXfd
152102599U, // VMAXfd_sfp
152102599U, // VMAXfq
166201031U, // VMAXsv16i8
165152455U, // VMAXsv2i32
165676743U, // VMAXsv4i16
165152455U, // VMAXsv4i32
165676743U, // VMAXsv8i16
166201031U, // VMAXsv8i8
167773895U, // VMAXuv16i8
166725319U, // VMAXuv2i32
167249607U, // VMAXuv4i16
166725319U, // VMAXuv4i32
167249607U, // VMAXuv8i16
167773895U, // VMAXuv8i8
152102604U, // VMINfd
152102604U, // VMINfd_sfp
152102604U, // VMINfq
166201036U, // VMINsv16i8
165152460U, // VMINsv2i32
165676748U, // VMINsv4i16
165152460U, // VMINsv4i32
165676748U, // VMINsv8i16
166201036U, // VMINsv8i8
167773900U, // VMINuv16i8
166725324U, // VMINuv2i32
167249612U, // VMINuv4i16
166725324U, // VMINuv4i32
167249612U, // VMINuv8i16
167773900U, // VMINuv8i8
822666961U, // VMLAD
232277718U, // VMLALslsv2i32
232802006U, // VMLALslsv4i16
233850582U, // VMLALsluv2i32
234374870U, // VMLALsluv4i16
836257494U, // VMLALsv2i64
836781782U, // VMLALsv4i32
837306070U, // VMLALsv8i16
837830358U, // VMLALuv2i64
838354646U, // VMLALuv4i32
838878934U, // VMLALuv8i16
823191249U, // VMLAS
823191249U, // VMLAfd
823191249U, // VMLAfq
219211473U, // VMLAslfd
219211473U, // VMLAslfq
235947729U, // VMLAslv2i32
236472017U, // VMLAslv4i16
235947729U, // VMLAslv4i32
236472017U, // VMLAslv8i16
840976081U, // VMLAv16i8
839927505U, // VMLAv2i32
840451793U, // VMLAv4i16
839927505U, // VMLAv4i32
840451793U, // VMLAv8i16
840976081U, // VMLAv8i8
822666972U, // VMLSD
232277729U, // VMLSLslsv2i32
232802017U, // VMLSLslsv4i16
233850593U, // VMLSLsluv2i32
234374881U, // VMLSLsluv4i16
836257505U, // VMLSLsv2i64
836781793U, // VMLSLsv4i32
837306081U, // VMLSLsv8i16
837830369U, // VMLSLuv2i64
838354657U, // VMLSLuv4i32
838878945U, // VMLSLuv8i16
823191260U, // VMLSS
823191260U, // VMLSfd
823191260U, // VMLSfq
219211484U, // VMLSslfd
219211484U, // VMLSslfq
235947740U, // VMLSslv2i32
236472028U, // VMLSslv4i16
235947740U, // VMLSslv4i32
236472028U, // VMLSslv8i16
840976092U, // VMLSv16i8
839927516U, // VMLSv2i32
840451804U, // VMLSv4i16
839927516U, // VMLSv4i32
840451804U, // VMLSv8i16
840976092U, // VMLSv8i8
755556697U, // VMOVD
135815513U, // VMOVDRR
151576921U, // VMOVDcc
739795289U, // VMOVDneon
769132263U, // VMOVLsv2i64
769656551U, // VMOVLsv4i32
770180839U, // VMOVLsv8i16
770705127U, // VMOVLuv2i64
771229415U, // VMOVLuv4i32
771753703U, // VMOVLuv8i16
772277997U, // VMOVNv2i32
772802285U, // VMOVNv4i16
773326573U, // VMOVNv8i8
739795289U, // VMOVQ
135815513U, // VMOVRRD
806904153U, // VMOVRRS
739795289U, // VMOVRS
756080985U, // VMOVS
739795289U, // VMOVSR
806904153U, // VMOVSRR
152101209U, // VMOVScc
773996889U, // VMOVv16i8
772432217U, // VMOVv1i64
772964697U, // VMOVv2i32
772432217U, // VMOVv2i64
773497177U, // VMOVv4i16
772964697U, // VMOVv4i32
773497177U, // VMOVv8i16
773996889U, // VMOVv8i8
337142110U, // VMRS
380110579U, // VMSR
151578360U, // VMULD
179308285U, // VMULLp
836241149U, // VMULLslsv2i32
836765437U, // VMULLslsv4i16
837814013U, // VMULLsluv2i32
838338301U, // VMULLsluv4i16
165152509U, // VMULLsv2i64
165676797U, // VMULLsv4i32
166201085U, // VMULLsv8i16
166725373U, // VMULLuv2i64
167249661U, // VMULLuv4i32
167773949U, // VMULLuv8i16
152102648U, // VMULS
152102648U, // VMULfd
152102648U, // VMULfd_sfp
152102648U, // VMULfq
179308280U, // VMULpd
179308280U, // VMULpq
823191288U, // VMULslfd
823191288U, // VMULslfq
839911160U, // VMULslv2i32
840435448U, // VMULslv4i16
839911160U, // VMULslv4i32
840435448U, // VMULslv8i16
169871096U, // VMULv16i8
168822520U, // VMULv2i32
169346808U, // VMULv4i16
168822520U, // VMULv4i32
169346808U, // VMULv8i16
169871096U, // VMULv8i8
739796739U, // VMVNd
739796739U, // VMVNq
755558152U, // VNEGD
151578376U, // VNEGDcc
756082440U, // VNEGS
152102664U, // VNEGScc
756082440U, // VNEGf32q
756082440U, // VNEGfd
756082440U, // VNEGfd_sfp
769656584U, // VNEGs16d
769656584U, // VNEGs16q
769132296U, // VNEGs32d
769132296U, // VNEGs32q
770180872U, // VNEGs8d
770180872U, // VNEGs8q
822667021U, // VNMLAD
823191309U, // VNMLAS
822667027U, // VNMLSD
823191315U, // VNMLSS
151578393U, // VNMULD
152102681U, // VNMULS
135816991U, // VORNd
135816991U, // VORNq
135816996U, // VORRd
135816996U, // VORRq
166217513U, // VPADALsv16i8
165168937U, // VPADALsv2i32
165693225U, // VPADALsv4i16
165168937U, // VPADALsv4i32
165693225U, // VPADALsv8i16
166217513U, // VPADALsv8i8
167790377U, // VPADALuv16i8
166741801U, // VPADALuv2i32
167266089U, // VPADALuv4i16
166741801U, // VPADALuv4i32
167266089U, // VPADALuv8i16
167790377U, // VPADALuv8i8
770180912U, // VPADDLsv16i8
769132336U, // VPADDLsv2i32
769656624U, // VPADDLsv4i16
769132336U, // VPADDLsv4i32
769656624U, // VPADDLsv8i16
770180912U, // VPADDLsv8i8
771753776U, // VPADDLuv16i8
770705200U, // VPADDLuv2i32
771229488U, // VPADDLuv4i16
770705200U, // VPADDLuv4i32
771229488U, // VPADDLuv8i16
771753776U, // VPADDLuv8i8
152102711U, // VPADDf
169346871U, // VPADDi16
168822583U, // VPADDi32
169871159U, // VPADDi8
152102717U, // VPMAXf
165676861U, // VPMAXs16
165152573U, // VPMAXs32
166201149U, // VPMAXs8
167249725U, // VPMAXu16
166725437U, // VPMAXu32
167774013U, // VPMAXu8
152102723U, // VPMINf
165676867U, // VPMINs16
165152579U, // VPMINs32
166201155U, // VPMINs8
167249731U, // VPMINu16
166725443U, // VPMINu32
167774019U, // VPMINu8
770180937U, // VQABSv16i8
769132361U, // VQABSv2i32
769656649U, // VQABSv4i16
769132361U, // VQABSv4i32
769656649U, // VQABSv8i16
770180937U, // VQABSv8i8
166201167U, // VQADDsv16i8
179832655U, // VQADDsv1i64
165152591U, // VQADDsv2i32
179832655U, // VQADDsv2i64
165676879U, // VQADDsv4i16
165152591U, // VQADDsv4i32
165676879U, // VQADDsv8i16
166201167U, // VQADDsv8i8
167774031U, // VQADDuv16i8
180356943U, // VQADDuv1i64
166725455U, // VQADDuv2i32
180356943U, // VQADDuv2i64
167249743U, // VQADDuv4i16
166725455U, // VQADDuv4i32
167249743U, // VQADDuv8i16
167774031U, // VQADDuv8i8
232277845U, // VQDMLALslv2i32
232802133U, // VQDMLALslv4i16
836257621U, // VQDMLALv2i64
836781909U, // VQDMLALv4i32
232277853U, // VQDMLSLslv2i32
232802141U, // VQDMLSLslv4i16
836257629U, // VQDMLSLv2i64
836781917U, // VQDMLSLv4i32
836241253U, // VQDMULHslv2i32
836765541U, // VQDMULHslv4i16
836241253U, // VQDMULHslv4i32
836765541U, // VQDMULHslv8i16
165152613U, // VQDMULHv2i32
165676901U, // VQDMULHv4i16
165152613U, // VQDMULHv4i32
165676901U, // VQDMULHv8i16
836241261U, // VQDMULLslv2i32
836765549U, // VQDMULLslv4i16
165152621U, // VQDMULLv2i64
165676909U, // VQDMULLv4i32
783812469U, // VQMOVNsuv2i32
769132405U, // VQMOVNsuv4i16
769656693U, // VQMOVNsuv8i8
783812477U, // VQMOVNsv2i32
769132413U, // VQMOVNsv4i16
769656701U, // VQMOVNsv8i8
784336765U, // VQMOVNuv2i32
770705277U, // VQMOVNuv4i16
771229565U, // VQMOVNuv8i8
770180996U, // VQNEGv16i8
769132420U, // VQNEGv2i32
769656708U, // VQNEGv4i16
769132420U, // VQNEGv4i32
769656708U, // VQNEGv8i16
770180996U, // VQNEGv8i8
836241290U, // VQRDMULHslv2i32
836765578U, // VQRDMULHslv4i16
836241290U, // VQRDMULHslv4i32
836765578U, // VQRDMULHslv8i16
165152650U, // VQRDMULHv2i32
165676938U, // VQRDMULHv4i16
165152650U, // VQRDMULHv4i32
165676938U, // VQRDMULHv8i16
166201235U, // VQRSHLsv16i8
179832723U, // VQRSHLsv1i64
165152659U, // VQRSHLsv2i32
179832723U, // VQRSHLsv2i64
165676947U, // VQRSHLsv4i16
165152659U, // VQRSHLsv4i32
165676947U, // VQRSHLsv8i16
166201235U, // VQRSHLsv8i8
167774099U, // VQRSHLuv16i8
180357011U, // VQRSHLuv1i64
166725523U, // VQRSHLuv2i32
180357011U, // VQRSHLuv2i64
167249811U, // VQRSHLuv4i16
166725523U, // VQRSHLuv4i32
167249811U, // VQRSHLuv8i16
167774099U, // VQRSHLuv8i8
179832730U, // VQRSHRNsv2i32
165152666U, // VQRSHRNsv4i16
165676954U, // VQRSHRNsv8i8
180357018U, // VQRSHRNuv2i32
166725530U, // VQRSHRNuv4i16
167249818U, // VQRSHRNuv8i8
179832738U, // VQRSHRUNv2i32
165152674U, // VQRSHRUNv4i16
165676962U, // VQRSHRUNv8i8
166201259U, // VQSHLsiv16i8
179832747U, // VQSHLsiv1i64
165152683U, // VQSHLsiv2i32
179832747U, // VQSHLsiv2i64
165676971U, // VQSHLsiv4i16
165152683U, // VQSHLsiv4i32
165676971U, // VQSHLsiv8i16
166201259U, // VQSHLsiv8i8
166201265U, // VQSHLsuv16i8
179832753U, // VQSHLsuv1i64
165152689U, // VQSHLsuv2i32
179832753U, // VQSHLsuv2i64
165676977U, // VQSHLsuv4i16
165152689U, // VQSHLsuv4i32
165676977U, // VQSHLsuv8i16
166201265U, // VQSHLsuv8i8
166201259U, // VQSHLsv16i8
179832747U, // VQSHLsv1i64
165152683U, // VQSHLsv2i32
179832747U, // VQSHLsv2i64
165676971U, // VQSHLsv4i16
165152683U, // VQSHLsv4i32
165676971U, // VQSHLsv8i16
166201259U, // VQSHLsv8i8
167774123U, // VQSHLuiv16i8
180357035U, // VQSHLuiv1i64
166725547U, // VQSHLuiv2i32
180357035U, // VQSHLuiv2i64
167249835U, // VQSHLuiv4i16
166725547U, // VQSHLuiv4i32
167249835U, // VQSHLuiv8i16
167774123U, // VQSHLuiv8i8
167774123U, // VQSHLuv16i8
180357035U, // VQSHLuv1i64
166725547U, // VQSHLuv2i32
180357035U, // VQSHLuv2i64
167249835U, // VQSHLuv4i16
166725547U, // VQSHLuv4i32
167249835U, // VQSHLuv8i16
167774123U, // VQSHLuv8i8
179832760U, // VQSHRNsv2i32
165152696U, // VQSHRNsv4i16
165676984U, // VQSHRNsv8i8
180357048U, // VQSHRNuv2i32
166725560U, // VQSHRNuv4i16
167249848U, // VQSHRNuv8i8
179832767U, // VQSHRUNv2i32
165152703U, // VQSHRUNv4i16
165676991U, // VQSHRUNv8i8
166201287U, // VQSUBsv16i8
179832775U, // VQSUBsv1i64
165152711U, // VQSUBsv2i32
179832775U, // VQSUBsv2i64
165676999U, // VQSUBsv4i16
165152711U, // VQSUBsv4i32
165676999U, // VQSUBsv8i16
166201287U, // VQSUBsv8i8
167774151U, // VQSUBuv16i8
180357063U, // VQSUBuv1i64
166725575U, // VQSUBuv2i32
180357063U, // VQSUBuv2i64
167249863U, // VQSUBuv4i16
166725575U, // VQSUBuv4i32
167249863U, // VQSUBuv8i16
167774151U, // VQSUBuv8i8
168298445U, // VRADDHNv2i32
168822733U, // VRADDHNv4i16
169347021U, // VRADDHNv8i8
770705365U, // VRECPEd
756082645U, // VRECPEfd
756082645U, // VRECPEfq
770705365U, // VRECPEq
152102876U, // VRECPSfd
152102876U, // VRECPSfq
774399971U, // VREV16d8
774399971U, // VREV16q8
779118570U, // VREV32d16
774399978U, // VREV32d8
779118570U, // VREV32q16
774399978U, // VREV32q8
779118577U, // VREV64d16
779642865U, // VREV64d32
774399985U, // VREV64d8
779642865U, // VREV64df
779118577U, // VREV64q16
779642865U, // VREV64q32
774399985U, // VREV64q8
779642865U, // VREV64qf
166201336U, // VRHADDsv16i8
165152760U, // VRHADDsv2i32
165677048U, // VRHADDsv4i16
165152760U, // VRHADDsv4i32
165677048U, // VRHADDsv8i16
166201336U, // VRHADDsv8i8
167774200U, // VRHADDuv16i8
166725624U, // VRHADDuv2i32
167249912U, // VRHADDuv4i16
166725624U, // VRHADDuv4i32
167249912U, // VRHADDuv8i16
167774200U, // VRHADDuv8i8
166201343U, // VRSHLsv16i8
179832831U, // VRSHLsv1i64
165152767U, // VRSHLsv2i32
179832831U, // VRSHLsv2i64
165677055U, // VRSHLsv4i16
165152767U, // VRSHLsv4i32
165677055U, // VRSHLsv8i16
166201343U, // VRSHLsv8i8
167774207U, // VRSHLuv16i8
180357119U, // VRSHLuv1i64
166725631U, // VRSHLuv2i32
180357119U, // VRSHLuv2i64
167249919U, // VRSHLuv4i16
166725631U, // VRSHLuv4i32
167249919U, // VRSHLuv8i16
167774207U, // VRSHLuv8i8
168298501U, // VRSHRNv2i32
168822789U, // VRSHRNv4i16
169347077U, // VRSHRNv8i8
166201356U, // VRSHRsv16i8
179832844U, // VRSHRsv1i64
165152780U, // VRSHRsv2i32
179832844U, // VRSHRsv2i64
165677068U, // VRSHRsv4i16
165152780U, // VRSHRsv4i32
165677068U, // VRSHRsv8i16
166201356U, // VRSHRsv8i8
167774220U, // VRSHRuv16i8
180357132U, // VRSHRuv1i64
166725644U, // VRSHRuv2i32
180357132U, // VRSHRuv2i64
167249932U, // VRSHRuv4i16
166725644U, // VRSHRuv4i32
167249932U, // VRSHRuv8i16
167774220U, // VRSHRuv8i8
770705426U, // VRSQRTEd
756082706U, // VRSQRTEfd
756082706U, // VRSQRTEfq
770705426U, // VRSQRTEq
152102938U, // VRSQRTSfd
152102938U, // VRSQRTSfq
837306402U, // VRSRAsv16i8
850937890U, // VRSRAsv1i64
836257826U, // VRSRAsv2i32
850937890U, // VRSRAsv2i64
836782114U, // VRSRAsv4i16
836257826U, // VRSRAsv4i32
836782114U, // VRSRAsv8i16
837306402U, // VRSRAsv8i8
838879266U, // VRSRAuv16i8
851462178U, // VRSRAuv1i64
837830690U, // VRSRAuv2i32
851462178U, // VRSRAuv2i64
838354978U, // VRSRAuv4i16
837830690U, // VRSRAuv4i32
838354978U, // VRSRAuv8i16
838879266U, // VRSRAuv8i8
168298536U, // VRSUBHNv2i32
168822824U, // VRSUBHNv4i16
169347112U, // VRSUBHNv8i8
846225753U, // VSETLNi16
846750041U, // VSETLNi32
841507161U, // VSETLNi8
169347120U, // VSHLLi16
168822832U, // VSHLLi32
169871408U, // VSHLLi8
165152816U, // VSHLLsv2i64
165677104U, // VSHLLsv4i32
166201392U, // VSHLLsv8i16
166725680U, // VSHLLuv2i64
167249968U, // VSHLLuv4i32
167774256U, // VSHLLuv8i16
169871414U, // VSHLiv16i8
168298550U, // VSHLiv1i64
168822838U, // VSHLiv2i32
168298550U, // VSHLiv2i64
169347126U, // VSHLiv4i16
168822838U, // VSHLiv4i32
169347126U, // VSHLiv8i16
169871414U, // VSHLiv8i8
166201398U, // VSHLsv16i8
179832886U, // VSHLsv1i64
165152822U, // VSHLsv2i32
179832886U, // VSHLsv2i64
165677110U, // VSHLsv4i16
165152822U, // VSHLsv4i32
165677110U, // VSHLsv8i16
166201398U, // VSHLsv8i8
167774262U, // VSHLuv16i8
180357174U, // VSHLuv1i64
166725686U, // VSHLuv2i32
180357174U, // VSHLuv2i64
167249974U, // VSHLuv4i16
166725686U, // VSHLuv4i32
167249974U, // VSHLuv8i16
167774262U, // VSHLuv8i8
168298555U, // VSHRNv2i32
168822843U, // VSHRNv4i16
169347131U, // VSHRNv8i8
166201409U, // VSHRsv16i8
179832897U, // VSHRsv1i64
165152833U, // VSHRsv2i32
179832897U, // VSHRsv2i64
165677121U, // VSHRsv4i16
165152833U, // VSHRsv4i32
165677121U, // VSHRsv8i16
166201409U, // VSHRsv8i8
167774273U, // VSHRuv16i8
180357185U, // VSHRuv1i64
166725697U, // VSHRuv2i32
180357185U, // VSHRuv2i64
167249985U, // VSHRuv4i16
166725697U, // VSHRuv4i32
167249985U, // VSHRuv8i16
167774273U, // VSHRuv8i8
180881015U, // VSHTOD
181405303U, // VSHTOS
786032247U, // VSITOD
778167927U, // VSITOS
841508934U, // VSLIv16i8
849373254U, // VSLIv1i64
846751814U, // VSLIv2i32
849373254U, // VSLIv2i64
846227526U, // VSLIv4i16
846751814U, // VSLIv4i32
846227526U, // VSLIv8i16
841508934U, // VSLIv8i8
181986935U, // VSLTOD
174122615U, // VSLTOS
755558475U, // VSQRTD
756082763U, // VSQRTS
837306449U, // VSRAsv16i8
850937937U, // VSRAsv1i64
836257873U, // VSRAsv2i32
850937937U, // VSRAsv2i64
836782161U, // VSRAsv4i16
836257873U, // VSRAsv4i32
836782161U, // VSRAsv8i16
837306449U, // VSRAsv8i8
838879313U, // VSRAuv16i8
851462225U, // VSRAuv1i64
837830737U, // VSRAuv2i32
851462225U, // VSRAuv2i64
838355025U, // VSRAuv4i16
837830737U, // VSRAuv4i32
838355025U, // VSRAuv8i16
838879313U, // VSRAuv8i8
841508950U, // VSRIv16i8
849373270U, // VSRIv1i64
846751830U, // VSRIv2i32
849373270U, // VSRIv2i64
846227542U, // VSRIv4i16
846751830U, // VSRIv4i32
846227542U, // VSRIv8i16
841508950U, // VSRIv8i8
243451995U, // VST1d16
1317193819U, // VST1d16Q
1384302683U, // VST1d16T
243976283U, // VST1d32
1317718107U, // VST1d32Q
1384826971U, // VST1d32T
244500571U, // VST1d64
245024859U, // VST1d8
1318766683U, // VST1d8Q
1385875547U, // VST1d8T
243976283U, // VST1df
242411611U, // VST1q16
242935899U, // VST1q32
245557339U, // VST1q64
237693019U, // VST1q8
242935899U, // VST1qf
1384302688U, // VST2LNd16
1384826976U, // VST2LNd32
1385875552U, // VST2LNd8
1384302688U, // VST2LNq16a
1384302688U, // VST2LNq16b
1384826976U, // VST2LNq32a
1384826976U, // VST2LNq32b
646105184U, // VST2d16
646105184U, // VST2d16D
646629472U, // VST2d32
646629472U, // VST2d32D
647153755U, // VST2d64
647678048U, // VST2d8
647678048U, // VST2d8D
1317193824U, // VST2q16
1317718112U, // VST2q32
1318766688U, // VST2q8
1317193829U, // VST3LNd16
1317718117U, // VST3LNd32
1318766693U, // VST3LNd8
1317193829U, // VST3LNq16a
1317193829U, // VST3LNq16b
1317718117U, // VST3LNq32a
1317718117U, // VST3LNq32b
1384302693U, // VST3d16
1384826981U, // VST3d32
1385351259U, // VST3d64
1385875557U, // VST3d8
1317210213U, // VST3q16a
1317210213U, // VST3q16b
1317734501U, // VST3q32a
1317734501U, // VST3q32b
1318783077U, // VST3q8a
1318783077U, // VST3q8b
1451411562U, // VST4LNd16
1451935850U, // VST4LNd32
1452984426U, // VST4LNd8
1451411562U, // VST4LNq16a
1451411562U, // VST4LNq16b
1451935850U, // VST4LNq32a
1451935850U, // VST4LNq32b
1317193834U, // VST4d16
1317718122U, // VST4d32
1318242395U, // VST4d64
1318766698U, // VST4d8
1451427946U, // VST4q16a
1451427946U, // VST4q16b
1451952234U, // VST4q32a
1451952234U, // VST4q32b
1453000810U, // VST4q8a
1453000810U, // VST4q8b
1610614895U, // VSTMD
1610614895U, // VSTMS
178284660U, // VSTRD
135932025U, // VSTRQ
175663220U, // VSTRS
151578752U, // VSUBD
168298629U, // VSUBHNv2i32
168822917U, // VSUBHNv4i16
169347205U, // VSUBHNv8i8
165152908U, // VSUBLsv2i64
165677196U, // VSUBLsv4i32
166201484U, // VSUBLsv8i16
166725772U, // VSUBLuv2i64
167250060U, // VSUBLuv4i32
167774348U, // VSUBLuv8i16
152103040U, // VSUBS
165152914U, // VSUBWsv2i64
165677202U, // VSUBWsv4i32
166201490U, // VSUBWsv8i16
166725778U, // VSUBWuv2i64
167250066U, // VSUBWuv4i32
167774354U, // VSUBWuv8i16
152103040U, // VSUBfd
152103040U, // VSUBfd_sfp
152103040U, // VSUBfq
169871488U, // VSUBv16i8
168298624U, // VSUBv1i64
168822912U, // VSUBv2i32
168298624U, // VSUBv2i64
169347200U, // VSUBv4i16
168822912U, // VSUBv4i32
169347200U, // VSUBv8i16
169871488U, // VSUBv8i8
739797144U, // VSWPd
739797144U, // VSWPq
170420381U, // VTBL1
841509021U, // VTBL2
237529245U, // VTBL3
640182429U, // VTBL4
841509026U, // VTBX1
237529250U, // VTBX2
640182434U, // VTBX3
1378379938U, // VTBX4
182453879U, // VTOSHD
182978167U, // VTOSHS
787605671U, // VTOSIRD
777119911U, // VTOSIRS
787605111U, // VTOSIZD
777119351U, // VTOSIZS
183559799U, // VTOSLD
173074039U, // VTOSLS
184026743U, // VTOUHD
184551031U, // VTOUHS
789178535U, // VTOUIRD
777644199U, // VTOUIRS
789177975U, // VTOUIZD
777643639U, // VTOUIZS
185132663U, // VTOULD
173598327U, // VTOULS
846227629U, // VTRNd16
846751917U, // VTRNd32
841509037U, // VTRNd8
846227629U, // VTRNq16
846751917U, // VTRNq32
841509037U, // VTRNq8
170420402U, // VTSTv16i8
175663282U, // VTSTv2i32
175138994U, // VTSTv4i16
175663282U, // VTSTv4i32
175138994U, // VTSTv8i16
170420402U, // VTSTv8i8
185599607U, // VUHTOD
186123895U, // VUHTOS
790750839U, // VUITOD
778692215U, // VUITOS
186705527U, // VULTOD
174646903U, // VULTOS
846227639U, // VUZPd16
846751927U, // VUZPd32
841509047U, // VUZPd8
846227639U, // VUZPq16
846751927U, // VUZPq32
841509047U, // VUZPq8
846227644U, // VZIPd16
846751932U, // VZIPd32
841509052U, // VZIPd8
846227644U, // VZIPq16
846751932U, // VZIPq32
841509052U, // VZIPq8
538970305U, // WFE
538970309U, // WFI
538970313U, // YIELD
1679319057U, // t2ADCSri
1730732049U, // t2ADCSrr
1797840913U, // t2ADCSrs
1679319057U, // t2ADCri
1730732049U, // t2ADCrr
1797840913U, // t2ADCrs
187228181U, // t2ADDSri
187228181U, // t2ADDSrr
858316821U, // t2ADDSrs
1730732058U, // t2ADDrSPi
135817423U, // t2ADDrSPi12
1797840922U, // t2ADDrSPs
1730732058U, // t2ADDri
1679321295U, // t2ADDri12
1730732058U, // t2ADDrr
1797840922U, // t2ADDrs
1679319108U, // t2ANDri
1730732100U, // t2ANDrr
1797840964U, // t2ANDrs
1730734292U, // t2ASRri
1730734292U, // t2ASRrr
69208280U, // t2B
135815244U, // t2BFC
806903888U, // t2BFI
1679319124U, // t2BICri
1730732116U, // t2BICrr
1797840980U, // t2BICrs
120586388U, // t2BR_JT
337141933U, // t2BXJ
388620468U, // t2Bcc
538968257U, // t2CLREX
739795143U, // t2CLZ
791208139U, // t2CMNzri
791208139U, // t2CMNzrr
187228363U, // t2CMNzrs
791208143U, // t2CMPri
791208143U, // t2CMPrr
187228367U, // t2CMPrs
791208143U, // t2CMPzri
791208143U, // t2CMPzrr
187228367U, // t2CMPzrs
939524307U, // t2CPS
337141975U, // t2DBG
590872948U, // t2DMBish
591397236U, // t2DMBishst
591921524U, // t2DMBnsh
592445812U, // t2DMBnshst
592970100U, // t2DMBosh
593494388U, // t2DMBoshst
594018676U, // t2DMBst
590872952U, // t2DSBish
591397240U, // t2DSBishst
591921528U, // t2DSBnsh
592445816U, // t2DSBnshst
592970104U, // t2DSBosh
593494392U, // t2DSBoshst
594018680U, // t2DSBst
1679319381U, // t2EORri
1730732373U, // t2EORrr
1797841237U, // t2EORrs
538968419U, // t2ISBsy
1811941597U, // t2IT
372U, // t2Int_MemBarrierV7
376U, // t2Int_SyncBarrierV7
1879050464U, // t2Int_eh_sjlj_setjmp
1027809679U, // t2LDM
1027809679U, // t2LDM_RET
135815580U, // t2LDRBT
806904215U, // t2LDRB_POST
806904215U, // t2LDRB_PRE
187228567U, // t2LDRBi12
135815575U, // t2LDRBi8
791208343U, // t2LDRBpci
858317207U, // t2LDRBs
806904226U, // t2LDRDi8
135815586U, // t2LDRDpci
739795367U, // t2LDREX
739795373U, // t2LDREXB
135815604U, // t2LDREXD
739795387U, // t2LDREXH
135815623U, // t2LDRHT
806904258U, // t2LDRH_POST
806904258U, // t2LDRH_PRE
187228610U, // t2LDRHi12
135815618U, // t2LDRHi8
791208386U, // t2LDRHpci
858317250U, // t2LDRHs
135815635U, // t2LDRSBT
806904269U, // t2LDRSB_POST
806904269U, // t2LDRSB_PRE
187228621U, // t2LDRSBi12
135815629U, // t2LDRSBi8
791208397U, // t2LDRSBpci
858317261U, // t2LDRSBs
135815648U, // t2LDRSHT
806904282U, // t2LDRSH_POST
806904282U, // t2LDRSH_PRE
187228634U, // t2LDRSHi12
135815642U, // t2LDRSHi8
791208410U, // t2LDRSHpci
858317274U, // t2LDRSHs
135815655U, // t2LDRT
806904211U, // t2LDR_POST
806904211U, // t2LDR_PRE
187228563U, // t2LDRi12
135815571U, // t2LDRi8
791208339U, // t2LDRpci
67111141U, // t2LDRpci_pic
858317203U, // t2LDRs
791365870U, // t2LEApcrel
187386094U, // t2LEApcrelJT
1730734322U, // t2LSLri
1730734322U, // t2LSLrr
1730734326U, // t2LSRri
1730734326U, // t2LSRrr
806904330U, // t2MLA
806904334U, // t2MLS
858319060U, // t2MOVCCasr
187228690U, // t2MOVCCi
858319090U, // t2MOVCClsl
858319094U, // t2MOVCClsr
187228690U, // t2MOVCCr
858319098U, // t2MOVCCror
135815702U, // t2MOVTi16
1967350290U, // t2MOVi
739795483U, // t2MOVi16
739795483U, // t2MOVi32imm
1967350290U, // t2MOVr
1967212798U, // t2MOVrx
67111170U, // t2MOVsra_flag
67111178U, // t2MOVsrl_flag
337142333U, // t2MRS
337142333U, // t2MRSsys
359686721U, // t2MSR
360211009U, // t2MSRsys
135815749U, // t2MUL
1967211081U, // t2MVNi
791208521U, // t2MVNr
187228745U, // t2MVNs
594543181U, // t2NOP
1679321362U, // t2ORNri
1679321362U, // t2ORNrr
1746430226U, // t2ORNrs
1679319633U, // t2ORRri
1730732625U, // t2ORRrr
1797841489U, // t2ORRrs
806904407U, // t2PKHBT
806904413U, // t2PKHTB
740002070U, // t2PLDWi12
740010262U, // t2PLDWi8
796395798U, // t2PLDWpci
797165846U, // t2PLDWr
193194262U, // t2PLDWs
740002075U, // t2PLDi12
740010267U, // t2PLDi8
796395803U, // t2PLDpci
797165851U, // t2PLDr
193194267U, // t2PLDs
740002079U, // t2PLIi12
740010271U, // t2PLIi8
796395807U, // t2PLIpci
797165855U, // t2PLIr
193194271U, // t2PLIs
135815814U, // t2QADD
135815819U, // t2QADD16
135815826U, // t2QADD8
135815832U, // t2QASX
135815837U, // t2QDADD
135815843U, // t2QDSUB
135815849U, // t2QSAX
135815854U, // t2QSUB
135815859U, // t2QSUB16
135815866U, // t2QSUB8
739795648U, // t2RBIT
791208645U, // t2REV
791208649U, // t2REV16
791208655U, // t2REVSH
337144099U, // t2RFEDB
337144105U, // t2RFEDBW
337144111U, // t2RFEIA
337144111U, // t2RFEIAW
1730734330U, // t2RORri
1730734330U, // t2RORrr
2013266654U, // t2RSBSri
1947755230U, // t2RSBSrs
187228894U, // t2RSBri
806904542U, // t2RSBrs
135815916U, // t2SADD16
135815923U, // t2SADD8
135815929U, // t2SASX
1679319812U, // t2SBCSri
1730732804U, // t2SBCSrr
1797841668U, // t2SBCSrs
1679319812U, // t2SBCri
1730732804U, // t2SBCrr
1797841668U, // t2SBCrs
806904584U, // t2SBFX
135817525U, // t2SDIV
135815949U, // t2SEL
594543397U, // t2SEV
135815977U, // t2SHADD16
135815985U, // t2SHADD8
135815992U, // t2SHASX
135815998U, // t2SHSAX
135816004U, // t2SHSUB16
135816012U, // t2SHSUB8
337142611U, // t2SMC
806904663U, // t2SMLABB
806904670U, // t2SMLABT
806904677U, // t2SMLAD
806904683U, // t2SMLADX
806904690U, // t2SMLAL
806904696U, // t2SMLALBB
806904704U, // t2SMLALBT
806904712U, // t2SMLALD
806904719U, // t2SMLALDX
806904727U, // t2SMLALTB
806904735U, // t2SMLALTT
806904743U, // t2SMLATB
806904750U, // t2SMLATT
806904757U, // t2SMLAWB
806904764U, // t2SMLAWT
806904771U, // t2SMLSD
806904777U, // t2SMLSDX
806904784U, // t2SMLSLD
806904791U, // t2SMLSLDX
806904799U, // t2SMMLA
806904805U, // t2SMMLAR
806904812U, // t2SMMLS
806904818U, // t2SMMLSR
135816185U, // t2SMMUL
135816191U, // t2SMMULR
135816198U, // t2SMUAD
135816204U, // t2SMUADX
135816211U, // t2SMULBB
135816218U, // t2SMULBT
806904865U, // t2SMULL
135816231U, // t2SMULTB
135816238U, // t2SMULTT
135816245U, // t2SMULWB
135816252U, // t2SMULWT
135816259U, // t2SMUSD
135816265U, // t2SMUSDX
365455674U, // t2SRSDB
365979962U, // t2SRSDBW
365455680U, // t2SRSIA
365979968U, // t2SRSIAW
135816276U, // t2SSAT16
806904923U, // t2SSATasr
806904923U, // t2SSATlsl
135816288U, // t2SSAX
135816293U, // t2SSUB16
135816300U, // t2SSUB8
1027810427U, // t2STM
135816328U, // t2STRBT
806880387U, // t2STRB_POST
806880387U, // t2STRB_PRE
187229315U, // t2STRBi12
135816323U, // t2STRBi8
858317955U, // t2STRBs
806904974U, // t2STRDi8
135816339U, // t2STREX
135816345U, // t2STREXB
806904992U, // t2STREXD
135816359U, // t2STREXH
135816371U, // t2STRHT
806880430U, // t2STRH_POST
806880430U, // t2STRH_PRE
187229358U, // t2STRHi12
135816366U, // t2STRHi8
858317998U, // t2STRHs
135816377U, // t2STRT
806880383U, // t2STR_POST
806880383U, // t2STR_PRE
187229311U, // t2STRi12
135816319U, // t2STRi8
858317951U, // t2STRs
187229374U, // t2SUBSri
187229374U, // t2SUBSrr
858318014U, // t2SUBSrs
1730733251U, // t2SUBrSPi
135817542U, // t2SUBrSPi12
67111243U, // t2SUBrSPi12_
67111251U, // t2SUBrSPi_
1746429123U, // t2SUBrSPs
67111260U, // t2SUBrSPs_
1730733251U, // t2SUBri
1679321414U, // t2SUBri12
1730733251U, // t2SUBrr
1797842115U, // t2SUBrs
135816404U, // t2SXTAB16rr
806905044U, // t2SXTAB16rr_rot
135816412U, // t2SXTABrr
806905052U, // t2SXTABrr_rot
135816418U, // t2SXTAHrr
806905058U, // t2SXTAHrr_rot
739796200U, // t2SXTB16r
135816424U, // t2SXTB16r_rot
791209199U, // t2SXTBr
187229423U, // t2SXTBr_rot
791209204U, // t2SXTHr
187229428U, // t2SXTHr_rot
2080377187U, // t2TBB
797165928U, // t2TBBgen
2080377196U, // t2TBH
797182321U, // t2TBHgen
791209209U, // t2TEQri
791209209U, // t2TEQrr
187229433U, // t2TEQrs
1277U, // t2TPsoft
791209237U, // t2TSTri
791209237U, // t2TSTrr
187229461U, // t2TSTrs
135816473U, // t2UADD16
135816480U, // t2UADD8
135816486U, // t2UASX
806905131U, // t2UBFX
135817589U, // t2UDIV
135816496U, // t2UHADD16
135816504U, // t2UHADD8
135816511U, // t2UHASX
135816517U, // t2UHSAX
135816523U, // t2UHSUB16
135816531U, // t2UHSUB8
806905178U, // t2UMAAL
806905184U, // t2UMLAL
806905190U, // t2UMULL
135816556U, // t2UQADD16
135816564U, // t2UQADD8
135816571U, // t2UQASX
135816577U, // t2UQSAX
135816583U, // t2UQSUB16
135816591U, // t2UQSUB8
135816598U, // t2USAD8
806905244U, // t2USADA8
135816611U, // t2USAT16
806905258U, // t2USATasr
806905258U, // t2USATlsl
135816623U, // t2USAX
135816628U, // t2USUB16
135816635U, // t2USUB8
135816641U, // t2UXTAB16rr
806905281U, // t2UXTAB16rr_rot
135816649U, // t2UXTABrr
806905289U, // t2UXTABrr_rot
135816655U, // t2UXTAHrr
806905295U, // t2UXTAHrr_rot
739796437U, // t2UXTB16r
135816661U, // t2UXTB16r_rot
791209436U, // t2UXTBr
187229660U, // t2UXTBr_rot
791209441U, // t2UXTHr
187229665U, // t2UXTHr_rot
594544833U, // t2WFE
594544837U, // t2WFI
594544841U, // t2YIELD
2206998545U, // tADC
135815194U, // tADDhirr
2206744602U, // tADDi3
2206998554U, // tADDi8
126880122U, // tADDrPCi
67127674U, // tADDrSP
67111290U, // tADDrSPi
2206744602U, // tADDrr
67389818U, // tADDspi
67127674U, // tADDspr
67127679U, // tADDspr_
69208454U, // tADJCALLSTACKDOWN
69208475U, // tADJCALLSTACKUP
2206998596U, // tAND
67127726U, // tANDsp
2206746836U, // tASRri
2207000788U, // tASRrr
69206089U, // tB
2206998612U, // tBIC
69208501U, // tBKPT
402653277U, // tBL
402653281U, // tBLXi
402653281U, // tBLXi_r9
69206113U, // tBLXr
69206113U, // tBLXr_r9
402653277U, // tBLr9
69206164U, // tBRIND
127402132U, // tBR_JTr
69206173U, // tBX
2491U, // tBX_RET
69206142U, // tBX_RET_vararg
69206173U, // tBXr9
337141940U, // tBcc
127926365U, // tBfar
67111361U, // tCBNZ
67111367U, // tCBZ
739795147U, // tCMNz
739795151U, // tCMPhir
739795151U, // tCMPi8
739795151U, // tCMPr
739795151U, // tCMPzhir
739795151U, // tCMPzi8
739795151U, // tCMPzr
939524307U, // tCPS
2206998869U, // tEOR
1879050464U, // tInt_eh_sjlj_setjmp
1027686799U, // tLDM
806904211U, // tLDR
806904215U, // tLDRB
806904215U, // tLDRBi
806904258U, // tLDRH
806904258U, // tLDRHi
135815629U, // tLDRSB
135815642U, // tLDRSH
739795347U, // tLDRcp
806904211U, // tLDRi
799539603U, // tLDRpci
67111372U, // tLDRpci_pic
135815571U, // tLDRspi
739797230U, // tLEApcrel
135817454U, // tLEApcrelJT
2206746866U, // tLSLri
2207000818U, // tLSLrr
2206746870U, // tLSRri
2207000822U, // tLSRrr
135815698U, // tMOVCCi
135815698U, // tMOVCCr
136317397U, // tMOVCCr_pseudo
67111392U, // tMOVSr
67111398U, // tMOVgpr2gpr
67111398U, // tMOVgpr2tgpr
2209473042U, // tMOVi8
67111398U, // tMOVr
67111398U, // tMOVtgpr2gpr
2206999109U, // tMUL
2209473097U, // tMVN
538968653U, // tNOP
2206999121U, // tORR
1203241557U, // tPICADD
538733035U, // tPOP
538733035U, // tPOP_RET
538733039U, // tPUSH
739795653U, // tREV
739795657U, // tREV16
739795663U, // tREVSH
2207000826U, // tROR
2209465054U, // tRSB
135815571U, // tRestore
2206999300U, // tSBC
785U, // tSETENDBE
795U, // tSETENDLE
538968869U, // tSEV
1027687547U, // tSTM
806904959U, // tSTR
806904963U, // tSTRB
806904963U, // tSTRBi
806905006U, // tSTRH
806905006U, // tSTRHi
806904959U, // tSTRi
135816319U, // tSTRspi
2206745795U, // tSUBi3
2206999747U, // tSUBi8
2206745795U, // tSUBrr
67389940U, // tSUBspi
67389788U, // tSUBspi_
337142983U, // tSVC
739796207U, // tSXTB
739796212U, // tSXTH
135816319U, // tSpill
1277U, // tTPsoft
1296U, // tTRAP
739796245U, // tTST
739796444U, // tUXTB
739796449U, // tUXTH
538970305U, // tWFE
538970309U, // tWFI
538970313U, // tYIELD
0U
};
const char *AsmStrs =
"DBG_VALUE\000adcs\t\000adc\000adds\000add\000@ ADJCALLSTACKDOWN \000@ A"
"DJCALLSTACKUP \000and\000\000b\t\000bfc\000bfi\000bic\000bkpt\000bl\t\000"
"blx\t\000bl\000mov\tlr, pc\n\tmov\tpc, \000bx\t\000add\tpc, \000ldr\tpc"
", \000mov\tpc, \000mov\tlr, pc\n\tbx\t\000bxj\000bx\000b\000cdp\000cdp2"
"\tp\000clrex\000clz\000cmn\000cmp\000cps\000dbg\000dmb\tish\000dmb\tish"
"st\000dmb\tnsh\000dmb\tnshst\000dmb\tosh\000dmb\toshst\000dmb\tst\000ds"
"b\tish\000dsb\tishst\000dsb\tnsh\000dsb\tnshst\000dsb\tosh\000dsb\toshs"
"t\000dsb\tst\000eor\000vmov\000vmrs\000isb\000mcr\tp15, 0, \000dmb\000d"
"sb\000str\tsp, [\000ldc2\000ldc\000ldm\000ldr\000ldrb\000ldrbt\000ldrd\000"
"ldrex\000ldrexb\000ldrexd\000ldrexh\000ldrh\000ldrht\000ldrsb\000ldrsbt"
"\000ldrsh\000ldrsht\000ldrt\000.set \000mcr\000mcr2\tp\000mcrr\000mcrr2"
"\tp\000mla\000mls\000mov\000movt\000movw\000movs\000mrc\000mrc2\tp\000m"
"rrc\000mrrc2\tp\000mrs\000msr\000mul\000mvn\000nop\000orr\000\n\000pkhb"
"t\000pkhtb\000pldw\t[\000pldw\t\000pld\t[\000pld\t\000pli\t[\000pli\t\000"
"qadd\000qadd16\000qadd8\000qasx\000qdadd\000qdsub\000qsax\000qsub\000qs"
"ub16\000qsub8\000rbit\000rev\000rev16\000revsh\000rfe\000rsbs\000rsb\000"
"rscs\t\000rsc\000sadd16\000sadd8\000sasx\000sbcs\t\000sbc\000sbfx\000se"
"l\000setend\tbe\000setend\tle\000sev\000shadd16\000shadd8\000shasx\000s"
"hsax\000shsub16\000shsub8\000smc\000smlabb\000smlabt\000smlad\000smladx"
"\000smlal\000smlalbb\000smlalbt\000smlald\000smlaldx\000smlaltb\000smla"
"ltt\000smlatb\000smlatt\000smlawb\000smlawt\000smlsd\000smlsdx\000smlsl"
"d\000smlsldx\000smmla\000smmlar\000smmls\000smmlsr\000smmul\000smmulr\000"
"smuad\000smuadx\000smulbb\000smulbt\000smull\000smultb\000smultt\000smu"
"lwb\000smulwt\000smusd\000smusdx\000srs\000ssat16\000ssat\000ssax\000ss"
"ub16\000ssub8\000stc2\000stc\000stm\000str\000strb\000strbt\000strd\000"
"strex\000strexb\000strexd\000strexh\000strh\000strht\000strt\000subs\000"
"sub\000svc\000swp\000swpb\000sxtab16\000sxtab\000sxtah\000sxtb16\000sxt"
"b\000sxth\000teq\000bl\t__aeabi_read_tp\000trap\000tst\000uadd16\000uad"
"d8\000uasx\000ubfx\000uhadd16\000uhadd8\000uhasx\000uhsax\000uhsub16\000"
"uhsub8\000umaal\000umlal\000umull\000uqadd16\000uqadd8\000uqasx\000uqsa"
"x\000uqsub16\000uqsub8\000usad8\000usada8\000usat16\000usat\000usax\000"
"usub16\000usub8\000uxtab16\000uxtab\000uxtah\000uxtb16\000uxtb\000uxth\000"
"vabal\000vaba\000vabdl\000vabd\000vabs\000vacge\000vacgt\000vadd\000vad"
"dhn\000vaddl\000vaddw\000vand\000vbic\000vbif\000vbit\000vbsl\000vceq\000"
"vcge\000vcgt\000vcle\000vcls\000vclt\000vclz\000vcmp\000vcmpe\000vcnt\000"
"vcvtb\000vcvt\000vcvtt\000vdiv\000vdup\000veor\000vext\000vhadd\000vhsu"
"b\000vld1\000vld2\000vld3\000vld4\000vldm\000vldr\000vldmia\000vmax\000"
"vmin\000vmla\000vmlal\000vmls\000vmlsl\000vmovl\000vmovn\000vmsr\000vmu"
"l\000vmull\000vmvn\000vneg\000vnmla\000vnmls\000vnmul\000vorn\000vorr\000"
"vpadal\000vpaddl\000vpadd\000vpmax\000vpmin\000vqabs\000vqadd\000vqdmla"
"l\000vqdmlsl\000vqdmulh\000vqdmull\000vqmovun\000vqmovn\000vqneg\000vqr"
"dmulh\000vqrshl\000vqrshrn\000vqrshrun\000vqshl\000vqshlu\000vqshrn\000"
"vqshrun\000vqsub\000vraddhn\000vrecpe\000vrecps\000vrev16\000vrev32\000"
"vrev64\000vrhadd\000vrshl\000vrshrn\000vrshr\000vrsqrte\000vrsqrts\000v"
"rsra\000vrsubhn\000vshll\000vshl\000vshrn\000vshr\000vsli\000vsqrt\000v"
"sra\000vsri\000vst1\000vst2\000vst3\000vst4\000vstm\000vstr\000vstmia\000"
"vsub\000vsubhn\000vsubl\000vsubw\000vswp\000vtbl\000vtbx\000vcvtr\000vt"
"rn\000vtst\000vuzp\000vzip\000wfe\000wfi\000yield\000addw\000asr\000b.w"
"\t\000it\000str\t\000@ ldr.w\t\000adr\000lsl\000lsr\000ror\000rrx\000as"
"rs.w\t\000lsrs.w\t\000orn\000pldw\000pld\000pli\000rfeab\000rfedb\000rf"
"eia\000sdiv\000srsdb\000srsia\000subw\000@ subw\t\000@ sub.w\t\000@ sub"
"\t\000tbb\t\000tbb\000tbh\t\000tbh\000udiv\000add\t\000@ add\t\000@ tAD"
"JCALLSTACKDOWN \000@ tADJCALLSTACKUP \000@ and\t\000bkpt\t\000bx\tlr\000"
"cbnz\t\000cbz\t\000@ ldr.n\t\000@ tMOVCCr \000movs\t\000mov\t\000pop\000"
"push\000sub\t\000";
O << "\t";
// Emit the opcode for the instruction.
unsigned Bits = OpInfo[MI->getOpcode()];
assert(Bits != 0 && "Cannot print this instruction.");
O << AsmStrs+(Bits & 4095)-1;
// Fragment 0 encoded into 6 bits for 33 unique commands.
switch ((Bits >> 26) & 63) {
default: // unreachable.
case 0:
// DBG_VALUE, CLREX, DMBish, DMBishst, DMBnsh, DMBnshst, DMBosh, DMBoshst...
return;
break;
case 1:
// ADCSSri, ADCSSrr, ADCSSrs, ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, B...
printOperand(MI, 0);
break;
case 2:
// ADCri, ADCrr, ADDSri, ADDSrr, ADDri, ADDrr, ANDri, ANDrr, BFC, BFI, BI...
printPredicateOperand(MI, 3);
break;
case 3:
// ADCrs, ADDSrs, ADDrs, ANDrs, BICrs, EORrs, LDC2L_OFFSET, LDC2L_POST, L...
printPredicateOperand(MI, 5);
break;
case 4:
// ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, ATOMIC_CMP_SWAP_I8, ATOMIC_L...
PrintSpecial(MI, "comment");
break;
case 5:
// BKPT, BL_pred, BLr9_pred, BXJ, Bcc, DBG, MRS, MRSsys, MSR, MSRi, MSRsy...
printPredicateOperand(MI, 1);
break;
case 6:
// BL, BLr9, tBL, tBLXi, tBLXi_r9, tBLr9
printOperand(MI, 0, "call");
return;
break;
case 7:
// BR_JTm, PLDWr, PLDr, PLIr
printAddrMode2Operand(MI, 0);
break;
case 8:
// BX_RET, FMSTAT, MOVPCLR, NOP, SEV, TRAP, WFE, WFI, YIELD, t2CLREX, t2D...
printPredicateOperand(MI, 0);
break;
case 9:
// CDP, LDRD_POST, LDRD_PRE, MCR, MRC, STRD_POST, STRD_PRE, VLD2d16, VLD2...
printPredicateOperand(MI, 6);
break;
case 10:
// CDP2, MCR2, MCRR2, MRC2, MRRC2
printNoHashImmediate(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 11:
// CLZ, CMNzri, CMNzrr, CMPri, CMPrr, CMPzri, CMPzrr, FCONSTD, FCONSTS, L...
printPredicateOperand(MI, 2);
break;
case 12:
// CMNzrs, CMPrs, CMPzrs, LDC2L_OPTION, LDC2_OPTION, LDCL_OPTION, LDC_OPT...
printPredicateOperand(MI, 4);
break;
case 13:
// CONSTPOOL_ENTRY
printCPInstOperand(MI, 0, "label");
O << ' ';
printCPInstOperand(MI, 1, "cpentry");
return;
break;
case 14:
// CPS, t2CPS, tCPS
printOperand(MI, 0, "cps");
return;
break;
case 15:
// LDM, LDM_RET, RFE, RFEW, SRS, SRSW, STM, t2LDM, t2LDM_RET, t2STM, tLDM...
printAddrMode4Operand(MI, 0, "submode");
break;
case 16:
// LEApcrel, LEApcrelJT
PrintSpecial(MI, "private");
O << "PCRELV";
PrintSpecial(MI, "uid");
O << ", (";
printOperand(MI, 1);
break;
case 17:
// PICADD, tPICADD
printPCLabel(MI, 2);
break;
case 18:
// PICLDR, PICLDRB, PICLDRH, PICLDRSB, PICLDRSH, PICSTR, PICSTRB, PICSTRH
printAddrModePCOperand(MI, 1, "label");
break;
case 19:
// VLD1d16Q, VLD1d32Q, VLD1d8Q, VLD2q16, VLD2q32, VLD2q8, VLD3q16a, VLD3q...
printPredicateOperand(MI, 8);
break;
case 20:
// VLD1d16T, VLD1d32T, VLD1d8T, VLD3d16, VLD3d32, VLD3d64, VLD3d8, VST1d1...
printPredicateOperand(MI, 7);
break;
case 21:
// VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16a, VLD2LNq16b, VLD2LNq32a, VL...
printPredicateOperand(MI, 9);
break;
case 22:
// VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16a, VLD3LNq16b, VLD3LNq32a, VL...
printPredicateOperand(MI, 11);
break;
case 23:
// VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16a, VLD4LNq16b, VLD4LNq32a, VL...
printPredicateOperand(MI, 13);
break;
case 24:
// VLDMD, VLDMS, VSTMD, VSTMS
printAddrMode5Operand(MI, 0, "submode");
printPredicateOperand(MI, 2);
O << "\t";
printAddrMode5Operand(MI, 0, "base");
O << ", ";
printRegisterList(MI, 4);
return;
break;
case 25:
// t2ADCSri, t2ADCSrr, t2ADCri, t2ADCrr, t2ADDrSPi, t2ADDri, t2ADDri12, t...
printSBitModifierOperand(MI, 5);
printPredicateOperand(MI, 3);
break;
case 26:
// t2ADCSrs, t2ADCrs, t2ADDrSPs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2OR...
printSBitModifierOperand(MI, 6);
printPredicateOperand(MI, 4);
break;
case 27:
// t2IT
printThumbITMask(MI, 1);
O << "\t";
printMandatoryPredicateOperand(MI, 0);
return;
break;
case 28:
// t2Int_eh_sjlj_setjmp, tInt_eh_sjlj_setjmp
printOperand(MI, 1);
O << ", [";
printOperand(MI, 0);
O << ", #8]\t@ begin eh.setjmp\n\tmov\t";
printOperand(MI, 1);
O << ", pc\n\tadds\t";
printOperand(MI, 1);
O << ", #9\n\tstr\t";
printOperand(MI, 1);
O << ", [";
printOperand(MI, 0);
O << ", #4]\n\tmovs\tr0, #0\n\tb\t1f\n\tmovs\tr0, #1\t@ end eh.setjmp\n1:";
return;
break;
case 29:
// t2MOVi, t2MOVr, t2MOVrx, t2MVNi, t2RSBSrs
printSBitModifierOperand(MI, 4);
break;
case 30:
// t2RSBSri
printSBitModifierOperand(MI, 3);
O << ".w\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 31:
// t2TBB, t2TBH
printTBAddrMode(MI, 0);
O << "\n";
printJT2BlockOperand(MI, 1);
return;
break;
case 32:
// tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
printSBitModifierOperand(MI, 1);
break;
}
// Fragment 1 encoded into 7 bits for 120 unique commands.
switch ((Bits >> 19) & 127) {
default: // unreachable.
case 0:
// ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MCR2, MCRR2, MRC2, MRRC2, PLDWi, ...
O << ", ";
break;
case 1:
// ADCri, ADCrr, ADDri, ADDrr, ANDri, ANDrr, BICri, BICrr, EORri, EORrr, ...
printSBitModifierOperand(MI, 5);
O << "\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
break;
case 2:
// ADCrs, ADDrs, ANDrs, BICrs, EORrs, ORRrs, RSBrs, RSCrs, SBCrs, SUBrs
printSBitModifierOperand(MI, 7);
O << "\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printSORegOperand(MI, 2);
return;
break;
case 3:
// ADDSri, ADDSrr, ADDSrs, BFC, BFI, BKPT, BL_pred, BLr9_pred, BXJ, Bcc, ...
O << "\t";
break;
case 4:
// ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, BLXr9, BMOVPCRX, BMOVPCRXr9,...
return;
break;
case 5:
// ATOMIC_CMP_SWAP_I16
O << " ATOMIC_CMP_SWAP_I16 PSEUDO!";
return;
break;
case 6:
// ATOMIC_CMP_SWAP_I32
O << " ATOMIC_CMP_SWAP_I32 PSEUDO!";
return;
break;
case 7:
// ATOMIC_CMP_SWAP_I8
O << " ATOMIC_CMP_SWAP_I8 PSEUDO!";
return;
break;
case 8:
// ATOMIC_LOAD_ADD_I16
O << " ATOMIC_LOAD_ADD_I16 PSEUDO!";
return;
break;
case 9:
// ATOMIC_LOAD_ADD_I32
O << " ATOMIC_LOAD_ADD_I32 PSEUDO!";
return;
break;
case 10:
// ATOMIC_LOAD_ADD_I8
O << " ATOMIC_LOAD_ADD_I8 PSEUDO!";
return;
break;
case 11:
// ATOMIC_LOAD_AND_I16
O << " ATOMIC_LOAD_AND_I16 PSEUDO!";
return;
break;
case 12:
// ATOMIC_LOAD_AND_I32
O << " ATOMIC_LOAD_AND_I32 PSEUDO!";
return;
break;
case 13:
// ATOMIC_LOAD_AND_I8
O << " ATOMIC_LOAD_AND_I8 PSEUDO!";
return;
break;
case 14:
// ATOMIC_LOAD_NAND_I16
O << " ATOMIC_LOAD_NAND_I16 PSEUDO!";
return;
break;
case 15:
// ATOMIC_LOAD_NAND_I32
O << " ATOMIC_LOAD_NAND_I32 PSEUDO!";
return;
break;
case 16:
// ATOMIC_LOAD_NAND_I8
O << " ATOMIC_LOAD_NAND_I8 PSEUDO!";
return;
break;
case 17:
// ATOMIC_LOAD_OR_I16
O << " ATOMIC_LOAD_OR_I16 PSEUDO!";
return;
break;
case 18:
// ATOMIC_LOAD_OR_I32
O << " ATOMIC_LOAD_OR_I32 PSEUDO!";
return;
break;
case 19:
// ATOMIC_LOAD_OR_I8
O << " ATOMIC_LOAD_OR_I8 PSEUDO!";
return;
break;
case 20:
// ATOMIC_LOAD_SUB_I16
O << " ATOMIC_LOAD_SUB_I16 PSEUDO!";
return;
break;
case 21:
// ATOMIC_LOAD_SUB_I32
O << " ATOMIC_LOAD_SUB_I32 PSEUDO!";
return;
break;
case 22:
// ATOMIC_LOAD_SUB_I8
O << " ATOMIC_LOAD_SUB_I8 PSEUDO!";
return;
break;
case 23:
// ATOMIC_LOAD_XOR_I16
O << " ATOMIC_LOAD_XOR_I16 PSEUDO!";
return;
break;
case 24:
// ATOMIC_LOAD_XOR_I32
O << " ATOMIC_LOAD_XOR_I32 PSEUDO!";
return;
break;
case 25:
// ATOMIC_LOAD_XOR_I8
O << " ATOMIC_LOAD_XOR_I8 PSEUDO!";
return;
break;
case 26:
// ATOMIC_SWAP_I16
O << " ATOMIC_SWAP_I16 PSEUDO!";
return;
break;
case 27:
// ATOMIC_SWAP_I32
O << " ATOMIC_SWAP_I32 PSEUDO!";
return;
break;
case 28:
// ATOMIC_SWAP_I8
O << " ATOMIC_SWAP_I8 PSEUDO!";
return;
break;
case 29:
// BR_JTm, BR_JTr
O << " \n";
break;
case 30:
// BX_RET
O << "\tlr";
return;
break;
case 31:
// CDP, LDC2_OFFSET, LDC2_OPTION, LDC2_POST, LDC2_PRE, LDC_OFFSET, LDC_OP...
O << "\tp";
printNoHashImmediate(MI, 0);
break;
case 32:
// CDP2
O << ", cr";
printNoHashImmediate(MI, 2);
O << ", cr";
printNoHashImmediate(MI, 3);
O << ", cr";
printNoHashImmediate(MI, 4);
O << ", ";
printOperand(MI, 5);
return;
break;
case 33:
// FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VMLAD, V...
O << ".f64\t";
printOperand(MI, 0);
break;
case 34:
// FCONSTS, VABDfd, VABDfq, VABSS, VABSfd, VABSfd_sfp, VABSfq, VACGEd, VA...
O << ".f32\t";
printOperand(MI, 0);
break;
case 35:
// FMSTAT
O << "\tapsr_nzcv, fpscr";
return;
break;
case 36:
// Int_MemBarrierV6
O << ", c7, c10, 5";
return;
break;
case 37:
// Int_SyncBarrierV6
O << ", c7, c10, 4";
return;
break;
case 38:
// Int_eh_sjlj_setjmp
O << ", #+8] @ eh_setjmp begin\n\tadd\t";
printOperand(MI, 1);
O << ", pc, #8\n\tstr\t";
printOperand(MI, 1);
O << ", [";
printOperand(MI, 0);
O << ", #+4]\n\tmov\tr0, #0\n\tadd\tpc, pc, #0\n\tmov\tr0, #1 @ eh_setjmp end";
return;
break;
case 39:
// LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDCL_OFFSET, LDCL_O...
O << "l\tp";
printNoHashImmediate(MI, 0);
O << ", cr";
printNoHashImmediate(MI, 1);
break;
case 40:
// LDM, LDM_RET, STM, t2LDM, t2LDM_RET, t2MOVi, t2MOVr, t2MOVrx, t2MVNi, ...
printPredicateOperand(MI, 2);
break;
case 41:
// LEApcrel
O << "-(";
PrintSpecial(MI, "private");
O << "PCRELL";
PrintSpecial(MI, "uid");
O << "+8))\n";
PrintSpecial(MI, "private");
O << "PCRELL";
PrintSpecial(MI, "uid");
O << ":\n\tadd";
printPredicateOperand(MI, 2);
O << "\t";
printOperand(MI, 0);
O << ", pc, #";
PrintSpecial(MI, "private");
O << "PCRELV";
PrintSpecial(MI, "uid");
return;
break;
case 42:
// LEApcrelJT
O << '_';
printNoHashImmediate(MI, 2);
O << "-(";
PrintSpecial(MI, "private");
O << "PCRELL";
PrintSpecial(MI, "uid");
O << "+8))\n";
PrintSpecial(MI, "private");
O << "PCRELL";
PrintSpecial(MI, "uid");
O << ":\n\tadd";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", pc, #";
PrintSpecial(MI, "private");
O << "PCRELV";
PrintSpecial(MI, "uid");
return;
break;
case 43:
// MLA, MOVs, MVNs, SMLAL, SMULL, UMLAL, UMULL
printSBitModifierOperand(MI, 6);
O << "\t";
printOperand(MI, 0);
O << ", ";
break;
case 44:
// MOVPCLR
O << "\tpc, lr";
return;
break;
case 45:
// MOVi, MOVr, MOVrx, MVNi, MVNr
printSBitModifierOperand(MI, 4);
O << "\t";
printOperand(MI, 0);
O << ", ";
break;
case 46:
// MSR, MSRi, t2MSR
O << "\tcpsr, ";
break;
case 47:
// MSRsys, MSRsysi, t2MSRsys
O << "\tspsr, ";
break;
case 48:
// PICADD
O << ":\n\tadd";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", pc, ";
printOperand(MI, 1);
return;
break;
case 49:
// PICLDR
O << ":\n\tldr";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 50:
// PICLDRB
O << ":\n\tldrb";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 51:
// PICLDRH
O << ":\n\tldrh";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 52:
// PICLDRSB
O << ":\n\tldrsb";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 53:
// PICLDRSH
O << ":\n\tldrsh";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 54:
// PICSTR
O << ":\n\tstr";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 55:
// PICSTRB
O << ":\n\tstrb";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 56:
// PICSTRH
O << ":\n\tstrh";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 57:
// SRS, t2SRSDB, t2SRSIA
O << "\tsp, ";
break;
case 58:
// SRSW, t2SRSDBW, t2SRSIAW
O << "\tsp!, ";
break;
case 59:
// VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i...
O << ".s32\t";
printOperand(MI, 0);
O << ", ";
break;
case 60:
// VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i...
O << ".s16\t";
printOperand(MI, 0);
O << ", ";
break;
case 61:
// VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8...
O << ".s8\t";
printOperand(MI, 0);
O << ", ";
break;
case 62:
// VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i...
O << ".u32\t";
printOperand(MI, 0);
O << ", ";
break;
case 63:
// VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i...
O << ".u16\t";
printOperand(MI, 0);
O << ", ";
break;
case 64:
// VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8...
O << ".u8\t";
printOperand(MI, 0);
O << ", ";
break;
case 65:
// VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V...
O << ".i64\t";
printOperand(MI, 0);
O << ", ";
break;
case 66:
// VADDHNv4i16, VADDv2i32, VADDv4i32, VCEQv2i32, VCEQv4i32, VCEQzv2i32, V...
O << ".i32\t";
printOperand(MI, 0);
O << ", ";
break;
case 67:
// VADDHNv8i8, VADDv4i16, VADDv8i16, VCEQv4i16, VCEQv8i16, VCEQzv4i16, VC...
O << ".i16\t";
printOperand(MI, 0);
O << ", ";
break;
case 68:
// VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCEQzv16i8, VCEQzv8i8, VCLZv...
O << ".i8\t";
printOperand(MI, 0);
O << ", ";
break;
case 69:
// VCNTd, VCNTq, VDUP8d, VDUP8q, VDUPLN8d, VDUPLN8q, VEXTd8, VEXTq8, VLD1...
O << ".8\t";
break;
case 70:
// VCVTBHS, VCVTTHS
O << ".f16.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
return;
break;
case 71:
// VCVTBSH, VCVTTSH
O << ".f32.f16\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
return;
break;
case 72:
// VCVTDS
O << ".f64.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
return;
break;
case 73:
// VCVTSD
O << ".f32.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
return;
break;
case 74:
// VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIRS, VTOSI...
O << ".s32.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 75:
// VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIRS, VTOUI...
O << ".u32.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 76:
// VCVTs2fd, VCVTs2fd_sfp, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS, VSLTOS
O << ".f32.s32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 77:
// VCVTu2fd, VCVTu2fd_sfp, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS, VULTOS
O << ".f32.u32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 78:
// VDUP16d, VDUP16q, VDUPLN16d, VDUPLN16q, VEXTd16, VEXTq16, VLD1q16, VRE...
O << ".16\t";
break;
case 79:
// VDUP32d, VDUP32q, VDUPLN32d, VDUPLN32q, VDUPLNfd, VDUPLNfq, VDUPfd, VD...
O << ".32\t";
break;
case 80:
// VLD1d16, VLD1d16Q, VLD1d16T, VLD2LNd16, VLD2LNq16a, VLD2LNq16b, VLD2d1...
O << ".16\t{";
break;
case 81:
// VLD1d32, VLD1d32Q, VLD1d32T, VLD1df, VLD2LNd32, VLD2LNq32a, VLD2LNq32b...
O << ".32\t{";
break;
case 82:
// VLD1d64, VLD2d64, VLD3d64, VLD4d64, VST1d64, VST2d64, VST3d64, VST4d64
O << ".64\t{";
break;
case 83:
// VLD1d8, VLD1d8Q, VLD1d8T, VLD2LNd8, VLD2d8, VLD2d8D, VLD2q8, VLD3LNd8,...
O << ".8\t{";
break;
case 84:
// VLD1q64, VLDRD, VSLIv1i64, VSLIv2i64, VSRIv1i64, VSRIv2i64, VST1q64, V...
O << ".64\t";
break;
case 85:
// VMSR
O << "\tfpscr, ";
printOperand(MI, 0);
return;
break;
case 86:
// VMULLp, VMULpd, VMULpq
O << ".p8\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 87:
// VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V...
O << ".s64\t";
printOperand(MI, 0);
O << ", ";
break;
case 88:
// VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ...
O << ".u64\t";
printOperand(MI, 0);
O << ", ";
break;
case 89:
// VSHTOD
O << ".f64.s16\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 90:
// VSHTOS
O << ".f32.s16\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 91:
// VSITOD, VSLTOD
O << ".f64.s32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 92:
// VTOSHD
O << ".s16.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 93:
// VTOSHS
O << ".s16.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 94:
// VTOSIRD, VTOSIZD, VTOSLD
O << ".s32.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 95:
// VTOUHD
O << ".u16.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 96:
// VTOUHS
O << ".u16.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 97:
// VTOUIRD, VTOUIZD, VTOULD
O << ".u32.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 98:
// VUHTOD
O << ".f64.u16\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 99:
// VUHTOS
O << ".f32.u16\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 100:
// VUITOD, VULTOD
O << ".f64.u32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 101:
// t2ADCSrr, t2ADCSrs, t2ADCrr, t2ADCrs, t2ADDSri, t2ADDSrr, t2ADDSrs, t2...
O << ".w\t";
printOperand(MI, 0);
break;
case 102:
// t2BR_JT
O << "\n";
printJT2BlockOperand(MI, 2);
return;
break;
case 103:
// t2DMBish, t2DSBish
O << "\tish";
return;
break;
case 104:
// t2DMBishst, t2DSBishst
O << "\tishst";
return;
break;
case 105:
// t2DMBnsh, t2DSBnsh
O << "\tnsh";
return;
break;
case 106:
// t2DMBnshst, t2DSBnshst
O << "\tnshst";
return;
break;
case 107:
// t2DMBosh, t2DSBosh
O << "\tosh";
return;
break;
case 108:
// t2DMBoshst, t2DSBoshst
O << "\toshst";
return;
break;
case 109:
// t2DMBst, t2DSBst
O << "\tst";
return;
break;
case 110:
// t2NOP, t2SEV, t2WFE, t2WFI, t2YIELD
O << ".w";
return;
break;
case 111:
// t2PLDWpci, t2PLDpci, t2PLIpci
O << "\t[pc, ";
printOperand(MI, 1, "negzero");
O << ']';
return;
break;
case 112:
// t2PLDWr, t2PLDWs, t2PLDr, t2PLDs, t2PLIr, t2PLIs, t2TBBgen, t2TBHgen
O << "\t[";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 113:
// tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
printPredicateOperand(MI, 4);
O << "\t";
printOperand(MI, 0);
O << ", ";
break;
case 114:
// tADDrPCi
O << ", pc, ";
printThumbS4ImmOperand(MI, 1);
return;
break;
case 115:
// tBR_JTr
O << "\n\t.align\t2\n";
printJTBlockOperand(MI, 1);
return;
break;
case 116:
// tBfar
O << "\t@ far jump";
return;
break;
case 117:
// tLDRpci
O << ".n\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
return;
break;
case 118:
// tMOVi8, tMVN, tRSB
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 2);
break;
case 119:
// tPICADD
O << ":\n\tadd\t";
printOperand(MI, 0);
O << ", pc";
return;
break;
}
// Fragment 2 encoded into 6 bits for 36 unique commands.
switch ((Bits >> 13) & 63) {
default: // unreachable.
case 0:
// ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MLA, MOVr, MOVrx, MVNr, PLDWi, PL...
printOperand(MI, 1);
break;
case 1:
// ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri
printSOImmOperand(MI, 2);
return;
break;
case 2:
// ADCrr, ADDrr, ANDrr, BICrr, EORrr, MCR2, MCRR2, MRC2, MRRC2, MUL, ORRr...
printOperand(MI, 2);
break;
case 3:
// ADDSri, ADDSrr, ADDSrs, BFC, BFI, BKPT, BXJ, Bcc, CLZ, CMNzri, CMNzrr,...
printOperand(MI, 0);
break;
case 4:
// BL_pred, BLr9_pred
printOperand(MI, 0, "call");
return;
break;
case 5:
// BR_JTm
printJTBlockOperand(MI, 3);
return;
break;
case 6:
// BR_JTr
printJTBlockOperand(MI, 1);
return;
break;
case 7:
// CDP, FCONSTD, FCONSTS, LDC2L_OFFSET, LDC2L_PRE, LDCL_OFFSET, LDCL_PRE,...
O << ", ";
break;
case 8:
// LDC2L_OPTION, LDC2L_POST, LDCL_OPTION, LDCL_POST, STC2L_OPTION, STC2L_...
O << ", [";
printOperand(MI, 2);
O << "], ";
break;
case 9:
// LDC2_OFFSET, LDC2_OPTION, LDC2_POST, LDC2_PRE, LDC_OFFSET, LDC_OPTION,...
O << ", cr";
printNoHashImmediate(MI, 1);
break;
case 10:
// LDM, LDM_RET, STM, t2MOVrx, t2MVNi, tLDM, tSTM
O << "\t";
break;
case 11:
// MOVi, MVNi
printSOImmOperand(MI, 1);
return;
break;
case 12:
// MOVs, MVNs
printSORegOperand(MI, 1);
return;
break;
case 13:
// MSRi, MSRsysi
printSOImmOperand(MI, 0);
return;
break;
case 14:
// VCMPEZD, VCMPEZS, VCMPZD, VCMPZS, tRSB
O << ", #0";
return;
break;
case 15:
// VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VC...
return;
break;
case 16:
// VLD1q16, VLD1q32, VLD1q64, VLD1q8, VLD1qf
printOperand(MI, 0, "dregpair");
O << ", ";
printAddrMode6Operand(MI, 1);
return;
break;
case 17:
// VLDRQ, VSTRQ
printAddrMode4Operand(MI, 1);
O << ", ";
printOperand(MI, 0, "dregpair");
return;
break;
case 18:
// VMOVv16i8, VMOVv8i8
printHex8ImmOperand(MI, 1);
return;
break;
case 19:
// VMOVv1i64, VMOVv2i64
printHex64ImmOperand(MI, 1);
return;
break;
case 20:
// VMOVv2i32, VMOVv4i32
printHex32ImmOperand(MI, 1);
return;
break;
case 21:
// VMOVv4i16, VMOVv8i16
printHex16ImmOperand(MI, 1);
return;
break;
case 22:
// VST1d16, VST1d16Q, VST1d16T, VST1d32, VST1d32Q, VST1d32T, VST1d64, VST...
printOperand(MI, 4);
break;
case 23:
// VST1q16, VST1q32, VST1q64, VST1q8, VST1qf
printOperand(MI, 4, "dregpair");
O << ", ";
printAddrMode6Operand(MI, 0);
return;
break;
case 24:
// VST3q16a, VST3q16b, VST3q32a, VST3q32b, VST3q8a, VST3q8b, VST4q16a, VS...
printOperand(MI, 5);
O << ", ";
printOperand(MI, 6);
O << ", ";
printOperand(MI, 7);
break;
case 25:
// t2LDM, t2LDM_RET, t2STM
printAddrMode4Operand(MI, 0, "wide");
O << "\t";
printAddrMode4Operand(MI, 0);
O << ", ";
printRegisterList(MI, 4);
return;
break;
case 26:
// t2LEApcrel, t2LEApcrelJT
O << ", #";
printOperand(MI, 1);
break;
case 27:
// t2MOVi, t2MOVr
O << ".w\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
return;
break;
case 28:
// t2PLDWi12, t2PLDi12, t2PLIi12
printT2AddrModeImm12Operand(MI, 0);
return;
break;
case 29:
// t2PLDWi8, t2PLDi8, t2PLIi8
printT2AddrModeImm8Operand(MI, 0);
return;
break;
case 30:
// t2PLDWr, t2PLDr, t2PLIr, t2TBBgen
O << ']';
return;
break;
case 31:
// t2PLDWs, t2PLDs, t2PLIs
O << ", lsl ";
printOperand(MI, 2);
O << ']';
return;
break;
case 32:
// t2TBHgen
O << ", lsl #1]";
return;
break;
case 33:
// tADC, tADDi8, tAND, tASRrr, tBIC, tEOR, tLSLrr, tLSRrr, tMUL, tORR, tR...
printOperand(MI, 3);
break;
case 34:
// tADDspi, tSUBspi, tSUBspi_
printThumbS4ImmOperand(MI, 2);
return;
break;
case 35:
// tPOP, tPOP_RET, tPUSH
printRegisterList(MI, 2);
return;
break;
}
switch (MI->getOpcode()) {
case ARM::ADCSSri:
case ARM::ADCSSrr:
case ARM::ADCSSrs:
case ARM::BFC:
case ARM::CLZ:
case ARM::CMNzri:
case ARM::CMNzrr:
case ARM::CMNzrs:
case ARM::CMPri:
case ARM::CMPrr:
case ARM::CMPrs:
case ARM::CMPzri:
case ARM::CMPzrr:
case ARM::CMPzrs:
case ARM::LDC2_OFFSET:
case ARM::LDC_OFFSET:
case ARM::LDR:
case ARM::LDRB:
case ARM::LDRD:
case ARM::LDRH:
case ARM::LDRSB:
case ARM::LDRSH:
case ARM::LDRcp:
case ARM::MOVCCi:
case ARM::MOVCCr:
case ARM::MOVCCs:
case ARM::MOVTi16:
case ARM::MOVi16:
case ARM::MOVi2pieces:
case ARM::RBIT:
case ARM::REV:
case ARM::REV16:
case ARM::REVSH:
case ARM::RSCSri:
case ARM::RSCSrs:
case ARM::SBCSSri:
case ARM::SBCSSrr:
case ARM::SBCSSrs:
case ARM::STC2_OFFSET:
case ARM::STC_OFFSET:
case ARM::STR:
case ARM::STRB:
case ARM::STRD:
case ARM::STRH:
case ARM::SXTB16r:
case ARM::SXTBr:
case ARM::SXTHr:
case ARM::TEQri:
case ARM::TEQrr:
case ARM::TEQrs:
case ARM::TSTri:
case ARM::TSTrr:
case ARM::TSTrs:
case ARM::UXTB16r:
case ARM::UXTBr:
case ARM::UXTHr:
case ARM::VABALsv2i64:
case ARM::VABALsv4i32:
case ARM::VABALsv8i16:
case ARM::VABALuv2i64:
case ARM::VABALuv4i32:
case ARM::VABALuv8i16:
case ARM::VABAsv16i8:
case ARM::VABAsv2i32:
case ARM::VABAsv4i16:
case ARM::VABAsv4i32:
case ARM::VABAsv8i16:
case ARM::VABAsv8i8:
case ARM::VABAuv16i8:
case ARM::VABAuv2i32:
case ARM::VABAuv4i16:
case ARM::VABAuv4i32:
case ARM::VABAuv8i16:
case ARM::VABAuv8i8:
case ARM::VABDLsv2i64:
case ARM::VABDLsv4i32:
case ARM::VABDLsv8i16:
case ARM::VABDLuv2i64:
case ARM::VABDLuv4i32:
case ARM::VABDLuv8i16:
case ARM::VABDsv16i8:
case ARM::VABDsv2i32:
case ARM::VABDsv4i16:
case ARM::VABDsv4i32:
case ARM::VABDsv8i16:
case ARM::VABDsv8i8:
case ARM::VABDuv16i8:
case ARM::VABDuv2i32:
case ARM::VABDuv4i16:
case ARM::VABDuv4i32:
case ARM::VABDuv8i16:
case ARM::VABDuv8i8:
case ARM::VADDHNv2i32:
case ARM::VADDHNv4i16:
case ARM::VADDHNv8i8:
case ARM::VADDLsv2i64:
case ARM::VADDLsv4i32:
case ARM::VADDLsv8i16:
case ARM::VADDLuv2i64:
case ARM::VADDLuv4i32:
case ARM::VADDLuv8i16:
case ARM::VADDWsv2i64:
case ARM::VADDWsv4i32:
case ARM::VADDWsv8i16:
case ARM::VADDWuv2i64:
case ARM::VADDWuv4i32:
case ARM::VADDWuv8i16:
case ARM::VADDv16i8:
case ARM::VADDv1i64:
case ARM::VADDv2i32:
case ARM::VADDv2i64:
case ARM::VADDv4i16:
case ARM::VADDv4i32:
case ARM::VADDv8i16:
case ARM::VADDv8i8:
case ARM::VCEQv16i8:
case ARM::VCEQv2i32:
case ARM::VCEQv4i16:
case ARM::VCEQv4i32:
case ARM::VCEQv8i16:
case ARM::VCEQv8i8:
case ARM::VCGEsv16i8:
case ARM::VCGEsv2i32:
case ARM::VCGEsv4i16:
case ARM::VCGEsv4i32:
case ARM::VCGEsv8i16:
case ARM::VCGEsv8i8:
case ARM::VCGEuv16i8:
case ARM::VCGEuv2i32:
case ARM::VCGEuv4i16:
case ARM::VCGEuv4i32:
case ARM::VCGEuv8i16:
case ARM::VCGEuv8i8:
case ARM::VCGTsv16i8:
case ARM::VCGTsv2i32:
case ARM::VCGTsv4i16:
case ARM::VCGTsv4i32:
case ARM::VCGTsv8i16:
case ARM::VCGTsv8i8:
case ARM::VCGTuv16i8:
case ARM::VCGTuv2i32:
case ARM::VCGTuv4i16:
case ARM::VCGTuv4i32:
case ARM::VCGTuv8i16:
case ARM::VCGTuv8i8:
case ARM::VCNTd:
case ARM::VCNTq:
case ARM::VDUP16d:
case ARM::VDUP16q:
case ARM::VDUP32d:
case ARM::VDUP32q:
case ARM::VDUP8d:
case ARM::VDUP8q:
case ARM::VDUPfd:
case ARM::VDUPfdf:
case ARM::VDUPfq:
case ARM::VDUPfqf:
case ARM::VHADDsv16i8:
case ARM::VHADDsv2i32:
case ARM::VHADDsv4i16:
case ARM::VHADDsv4i32:
case ARM::VHADDsv8i16:
case ARM::VHADDsv8i8:
case ARM::VHADDuv16i8:
case ARM::VHADDuv2i32:
case ARM::VHADDuv4i16:
case ARM::VHADDuv4i32:
case ARM::VHADDuv8i16:
case ARM::VHADDuv8i8:
case ARM::VHSUBsv16i8:
case ARM::VHSUBsv2i32:
case ARM::VHSUBsv4i16:
case ARM::VHSUBsv4i32:
case ARM::VHSUBsv8i16:
case ARM::VHSUBsv8i8:
case ARM::VHSUBuv16i8:
case ARM::VHSUBuv2i32:
case ARM::VHSUBuv4i16:
case ARM::VHSUBuv4i32:
case ARM::VHSUBuv8i16:
case ARM::VHSUBuv8i8:
case ARM::VLDRD:
case ARM::VLDRS:
case ARM::VMAXsv16i8:
case ARM::VMAXsv2i32:
case ARM::VMAXsv4i16:
case ARM::VMAXsv4i32:
case ARM::VMAXsv8i16:
case ARM::VMAXsv8i8:
case ARM::VMAXuv16i8:
case ARM::VMAXuv2i32:
case ARM::VMAXuv4i16:
case ARM::VMAXuv4i32:
case ARM::VMAXuv8i16:
case ARM::VMAXuv8i8:
case ARM::VMINsv16i8:
case ARM::VMINsv2i32:
case ARM::VMINsv4i16:
case ARM::VMINsv4i32:
case ARM::VMINsv8i16:
case ARM::VMINsv8i8:
case ARM::VMINuv16i8:
case ARM::VMINuv2i32:
case ARM::VMINuv4i16:
case ARM::VMINuv4i32:
case ARM::VMINuv8i16:
case ARM::VMINuv8i8:
case ARM::VMLALsv2i64:
case ARM::VMLALsv4i32:
case ARM::VMLALsv8i16:
case ARM::VMLALuv2i64:
case ARM::VMLALuv4i32:
case ARM::VMLALuv8i16:
case ARM::VMLAv16i8:
case ARM::VMLAv2i32:
case ARM::VMLAv4i16:
case ARM::VMLAv4i32:
case ARM::VMLAv8i16:
case ARM::VMLAv8i8:
case ARM::VMLSLsv2i64:
case ARM::VMLSLsv4i32:
case ARM::VMLSLsv8i16:
case ARM::VMLSLuv2i64:
case ARM::VMLSLuv4i32:
case ARM::VMLSLuv8i16:
case ARM::VMLSv16i8:
case ARM::VMLSv2i32:
case ARM::VMLSv4i16:
case ARM::VMLSv4i32:
case ARM::VMLSv8i16:
case ARM::VMLSv8i8:
case ARM::VMOVDneon:
case ARM::VMOVQ:
case ARM::VMOVRS:
case ARM::VMOVSR:
case ARM::VMULLsv2i64:
case ARM::VMULLsv4i32:
case ARM::VMULLsv8i16:
case ARM::VMULLuv2i64:
case ARM::VMULLuv4i32:
case ARM::VMULLuv8i16:
case ARM::VMULv16i8:
case ARM::VMULv2i32:
case ARM::VMULv4i16:
case ARM::VMULv4i32:
case ARM::VMULv8i16:
case ARM::VMULv8i8:
case ARM::VMVNd:
case ARM::VMVNq:
case ARM::VPADDi16:
case ARM::VPADDi32:
case ARM::VPADDi8:
case ARM::VPMAXs16:
case ARM::VPMAXs32:
case ARM::VPMAXs8:
case ARM::VPMAXu16:
case ARM::VPMAXu32:
case ARM::VPMAXu8:
case ARM::VPMINs16:
case ARM::VPMINs32:
case ARM::VPMINs8:
case ARM::VPMINu16:
case ARM::VPMINu32:
case ARM::VPMINu8:
case ARM::VQADDsv16i8:
case ARM::VQADDsv1i64:
case ARM::VQADDsv2i32:
case ARM::VQADDsv2i64:
case ARM::VQADDsv4i16:
case ARM::VQADDsv4i32:
case ARM::VQADDsv8i16:
case ARM::VQADDsv8i8:
case ARM::VQADDuv16i8:
case ARM::VQADDuv1i64:
case ARM::VQADDuv2i32:
case ARM::VQADDuv2i64:
case ARM::VQADDuv4i16:
case ARM::VQADDuv4i32:
case ARM::VQADDuv8i16:
case ARM::VQADDuv8i8:
case ARM::VQDMLALv2i64:
case ARM::VQDMLALv4i32:
case ARM::VQDMLSLv2i64:
case ARM::VQDMLSLv4i32:
case ARM::VQDMULHv2i32:
case ARM::VQDMULHv4i16:
case ARM::VQDMULHv4i32:
case ARM::VQDMULHv8i16:
case ARM::VQDMULLv2i64:
case ARM::VQDMULLv4i32:
case ARM::VQRDMULHv2i32:
case ARM::VQRDMULHv4i16:
case ARM::VQRDMULHv4i32:
case ARM::VQRDMULHv8i16:
case ARM::VQRSHLsv16i8:
case ARM::VQRSHLsv1i64:
case ARM::VQRSHLsv2i32:
case ARM::VQRSHLsv2i64:
case ARM::VQRSHLsv4i16:
case ARM::VQRSHLsv4i32:
case ARM::VQRSHLsv8i16:
case ARM::VQRSHLsv8i8:
case ARM::VQRSHLuv16i8:
case ARM::VQRSHLuv1i64:
case ARM::VQRSHLuv2i32:
case ARM::VQRSHLuv2i64:
case ARM::VQRSHLuv4i16:
case ARM::VQRSHLuv4i32:
case ARM::VQRSHLuv8i16:
case ARM::VQRSHLuv8i8:
case ARM::VQRSHRNsv2i32:
case ARM::VQRSHRNsv4i16:
case ARM::VQRSHRNsv8i8:
case ARM::VQRSHRNuv2i32:
case ARM::VQRSHRNuv4i16:
case ARM::VQRSHRNuv8i8:
case ARM::VQRSHRUNv2i32:
case ARM::VQRSHRUNv4i16:
case ARM::VQRSHRUNv8i8:
case ARM::VQSHLsiv16i8:
case ARM::VQSHLsiv1i64:
case ARM::VQSHLsiv2i32:
case ARM::VQSHLsiv2i64:
case ARM::VQSHLsiv4i16:
case ARM::VQSHLsiv4i32:
case ARM::VQSHLsiv8i16:
case ARM::VQSHLsiv8i8:
case ARM::VQSHLsuv16i8:
case ARM::VQSHLsuv1i64:
case ARM::VQSHLsuv2i32:
case ARM::VQSHLsuv2i64:
case ARM::VQSHLsuv4i16:
case ARM::VQSHLsuv4i32:
case ARM::VQSHLsuv8i16:
case ARM::VQSHLsuv8i8:
case ARM::VQSHLsv16i8:
case ARM::VQSHLsv1i64:
case ARM::VQSHLsv2i32:
case ARM::VQSHLsv2i64:
case ARM::VQSHLsv4i16:
case ARM::VQSHLsv4i32:
case ARM::VQSHLsv8i16:
case ARM::VQSHLsv8i8:
case ARM::VQSHLuiv16i8:
case ARM::VQSHLuiv1i64:
case ARM::VQSHLuiv2i32:
case ARM::VQSHLuiv2i64:
case ARM::VQSHLuiv4i16:
case ARM::VQSHLuiv4i32:
case ARM::VQSHLuiv8i16:
case ARM::VQSHLuiv8i8:
case ARM::VQSHLuv16i8:
case ARM::VQSHLuv1i64:
case ARM::VQSHLuv2i32:
case ARM::VQSHLuv2i64:
case ARM::VQSHLuv4i16:
case ARM::VQSHLuv4i32:
case ARM::VQSHLuv8i16:
case ARM::VQSHLuv8i8:
case ARM::VQSHRNsv2i32:
case ARM::VQSHRNsv4i16:
case ARM::VQSHRNsv8i8:
case ARM::VQSHRNuv2i32:
case ARM::VQSHRNuv4i16:
case ARM::VQSHRNuv8i8:
case ARM::VQSHRUNv2i32:
case ARM::VQSHRUNv4i16:
case ARM::VQSHRUNv8i8:
case ARM::VQSUBsv16i8:
case ARM::VQSUBsv1i64:
case ARM::VQSUBsv2i32:
case ARM::VQSUBsv2i64:
case ARM::VQSUBsv4i16:
case ARM::VQSUBsv4i32:
case ARM::VQSUBsv8i16:
case ARM::VQSUBsv8i8:
case ARM::VQSUBuv16i8:
case ARM::VQSUBuv1i64:
case ARM::VQSUBuv2i32:
case ARM::VQSUBuv2i64:
case ARM::VQSUBuv4i16:
case ARM::VQSUBuv4i32:
case ARM::VQSUBuv8i16:
case ARM::VQSUBuv8i8:
case ARM::VRADDHNv2i32:
case ARM::VRADDHNv4i16:
case ARM::VRADDHNv8i8:
case ARM::VREV16d8:
case ARM::VREV16q8:
case ARM::VREV32d16:
case ARM::VREV32d8:
case ARM::VREV32q16:
case ARM::VREV32q8:
case ARM::VREV64d16:
case ARM::VREV64d32:
case ARM::VREV64d8:
case ARM::VREV64df:
case ARM::VREV64q16:
case ARM::VREV64q32:
case ARM::VREV64q8:
case ARM::VREV64qf:
case ARM::VRHADDsv16i8:
case ARM::VRHADDsv2i32:
case ARM::VRHADDsv4i16:
case ARM::VRHADDsv4i32:
case ARM::VRHADDsv8i16:
case ARM::VRHADDsv8i8:
case ARM::VRHADDuv16i8:
case ARM::VRHADDuv2i32:
case ARM::VRHADDuv4i16:
case ARM::VRHADDuv4i32:
case ARM::VRHADDuv8i16:
case ARM::VRHADDuv8i8:
case ARM::VRSHLsv16i8:
case ARM::VRSHLsv1i64:
case ARM::VRSHLsv2i32:
case ARM::VRSHLsv2i64:
case ARM::VRSHLsv4i16:
case ARM::VRSHLsv4i32:
case ARM::VRSHLsv8i16:
case ARM::VRSHLsv8i8:
case ARM::VRSHLuv16i8:
case ARM::VRSHLuv1i64:
case ARM::VRSHLuv2i32:
case ARM::VRSHLuv2i64:
case ARM::VRSHLuv4i16:
case ARM::VRSHLuv4i32:
case ARM::VRSHLuv8i16:
case ARM::VRSHLuv8i8:
case ARM::VRSHRNv2i32:
case ARM::VRSHRNv4i16:
case ARM::VRSHRNv8i8:
case ARM::VRSHRsv16i8:
case ARM::VRSHRsv1i64:
case ARM::VRSHRsv2i32:
case ARM::VRSHRsv2i64:
case ARM::VRSHRsv4i16:
case ARM::VRSHRsv4i32:
case ARM::VRSHRsv8i16:
case ARM::VRSHRsv8i8:
case ARM::VRSHRuv16i8:
case ARM::VRSHRuv1i64:
case ARM::VRSHRuv2i32:
case ARM::VRSHRuv2i64:
case ARM::VRSHRuv4i16:
case ARM::VRSHRuv4i32:
case ARM::VRSHRuv8i16:
case ARM::VRSHRuv8i8:
case ARM::VRSRAsv16i8:
case ARM::VRSRAsv1i64:
case ARM::VRSRAsv2i32:
case ARM::VRSRAsv2i64:
case ARM::VRSRAsv4i16:
case ARM::VRSRAsv4i32:
case ARM::VRSRAsv8i16:
case ARM::VRSRAsv8i8:
case ARM::VRSRAuv16i8:
case ARM::VRSRAuv1i64:
case ARM::VRSRAuv2i32:
case ARM::VRSRAuv2i64:
case ARM::VRSRAuv4i16:
case ARM::VRSRAuv4i32:
case ARM::VRSRAuv8i16:
case ARM::VRSRAuv8i8:
case ARM::VRSUBHNv2i32:
case ARM::VRSUBHNv4i16:
case ARM::VRSUBHNv8i8:
case ARM::VSHLLi16:
case ARM::VSHLLi32:
case ARM::VSHLLi8:
case ARM::VSHLLsv2i64:
case ARM::VSHLLsv4i32:
case ARM::VSHLLsv8i16:
case ARM::VSHLLuv2i64:
case ARM::VSHLLuv4i32:
case ARM::VSHLLuv8i16:
case ARM::VSHLiv16i8:
case ARM::VSHLiv1i64:
case ARM::VSHLiv2i32:
case ARM::VSHLiv2i64:
case ARM::VSHLiv4i16:
case ARM::VSHLiv4i32:
case ARM::VSHLiv8i16:
case ARM::VSHLiv8i8:
case ARM::VSHLsv16i8:
case ARM::VSHLsv1i64:
case ARM::VSHLsv2i32:
case ARM::VSHLsv2i64:
case ARM::VSHLsv4i16:
case ARM::VSHLsv4i32:
case ARM::VSHLsv8i16:
case ARM::VSHLsv8i8:
case ARM::VSHLuv16i8:
case ARM::VSHLuv1i64:
case ARM::VSHLuv2i32:
case ARM::VSHLuv2i64:
case ARM::VSHLuv4i16:
case ARM::VSHLuv4i32:
case ARM::VSHLuv8i16:
case ARM::VSHLuv8i8:
case ARM::VSHRNv2i32:
case ARM::VSHRNv4i16:
case ARM::VSHRNv8i8:
case ARM::VSHRsv16i8:
case ARM::VSHRsv1i64:
case ARM::VSHRsv2i32:
case ARM::VSHRsv2i64:
case ARM::VSHRsv4i16:
case ARM::VSHRsv4i32:
case ARM::VSHRsv8i16:
case ARM::VSHRsv8i8:
case ARM::VSHRuv16i8:
case ARM::VSHRuv1i64:
case ARM::VSHRuv2i32:
case ARM::VSHRuv2i64:
case ARM::VSHRuv4i16:
case ARM::VSHRuv4i32:
case ARM::VSHRuv8i16:
case ARM::VSHRuv8i8:
case ARM::VSRAsv16i8:
case ARM::VSRAsv1i64:
case ARM::VSRAsv2i32:
case ARM::VSRAsv2i64:
case ARM::VSRAsv4i16:
case ARM::VSRAsv4i32:
case ARM::VSRAsv8i16:
case ARM::VSRAsv8i8:
case ARM::VSRAuv16i8:
case ARM::VSRAuv1i64:
case ARM::VSRAuv2i32:
case ARM::VSRAuv2i64:
case ARM::VSRAuv4i16:
case ARM::VSRAuv4i32:
case ARM::VSRAuv8i16:
case ARM::VSRAuv8i8:
case ARM::VSTRD:
case ARM::VSTRS:
case ARM::VSUBHNv2i32:
case ARM::VSUBHNv4i16:
case ARM::VSUBHNv8i8:
case ARM::VSUBLsv2i64:
case ARM::VSUBLsv4i32:
case ARM::VSUBLsv8i16:
case ARM::VSUBLuv2i64:
case ARM::VSUBLuv4i32:
case ARM::VSUBLuv8i16:
case ARM::VSUBWsv2i64:
case ARM::VSUBWsv4i32:
case ARM::VSUBWsv8i16:
case ARM::VSUBWuv2i64:
case ARM::VSUBWuv4i32:
case ARM::VSUBWuv8i16:
case ARM::VSUBv16i8:
case ARM::VSUBv1i64:
case ARM::VSUBv2i32:
case ARM::VSUBv2i64:
case ARM::VSUBv4i16:
case ARM::VSUBv4i32:
case ARM::VSUBv8i16:
case ARM::VSUBv8i8:
case ARM::VSWPd:
case ARM::VSWPq:
case ARM::VTRNd16:
case ARM::VTRNd32:
case ARM::VTRNd8:
case ARM::VTRNq16:
case ARM::VTRNq32:
case ARM::VTRNq8:
case ARM::VUZPd16:
case ARM::VUZPd32:
case ARM::VUZPd8:
case ARM::VUZPq16:
case ARM::VUZPq32:
case ARM::VUZPq8:
case ARM::VZIPd16:
case ARM::VZIPd32:
case ARM::VZIPd8:
case ARM::VZIPq16:
case ARM::VZIPq32:
case ARM::VZIPq8:
case ARM::t2BFC:
case ARM::t2CLZ:
case ARM::t2LDRBT:
case ARM::t2LDRBi8:
case ARM::t2LDRDi8:
case ARM::t2LDRDpci:
case ARM::t2LDRHT:
case ARM::t2LDRHi8:
case ARM::t2LDRSBT:
case ARM::t2LDRSBi8:
case ARM::t2LDRSHT:
case ARM::t2LDRSHi8:
case ARM::t2LDRT:
case ARM::t2LDRi8:
case ARM::t2MOVTi16:
case ARM::t2MOVi16:
case ARM::t2RBIT:
case ARM::t2STRBT:
case ARM::t2STRBi8:
case ARM::t2STRDi8:
case ARM::t2STRHT:
case ARM::t2STRHi8:
case ARM::t2STRT:
case ARM::t2STRi8:
case ARM::t2SUBrSPi12_:
case ARM::t2SUBrSPi_:
case ARM::t2SUBrSPs_:
case ARM::t2SXTB16r:
case ARM::t2UXTB16r:
case ARM::tADDhirr:
case ARM::tADDi3:
case ARM::tADDrSPi:
case ARM::tADDrr:
case ARM::tASRri:
case ARM::tCMNz:
case ARM::tCMPhir:
case ARM::tCMPi8:
case ARM::tCMPr:
case ARM::tCMPzhir:
case ARM::tCMPzi8:
case ARM::tCMPzr:
case ARM::tLDR:
case ARM::tLDRB:
case ARM::tLDRBi:
case ARM::tLDRH:
case ARM::tLDRHi:
case ARM::tLDRSB:
case ARM::tLDRSH:
case ARM::tLDRcp:
case ARM::tLDRi:
case ARM::tLDRspi:
case ARM::tLSLri:
case ARM::tLSRri:
case ARM::tMOVCCi:
case ARM::tMOVCCr:
case ARM::tMUL:
case ARM::tREV:
case ARM::tREV16:
case ARM::tREVSH:
case ARM::tRestore:
case ARM::tSTR:
case ARM::tSTRB:
case ARM::tSTRBi:
case ARM::tSTRH:
case ARM::tSTRHi:
case ARM::tSTRi:
case ARM::tSTRspi:
case ARM::tSUBi3:
case ARM::tSUBrr:
case ARM::tSXTB:
case ARM::tSXTH:
case ARM::tSpill:
case ARM::tTST:
case ARM::tUXTB:
case ARM::tUXTH:
O << ", ";
switch (MI->getOpcode()) {
case ARM::ADCSSri:
case ARM::MOVCCi:
case ARM::RSCSri:
case ARM::SBCSSri: printSOImmOperand(MI, 2); break;
case ARM::ADCSSrr:
case ARM::MOVCCr:
case ARM::MOVTi16:
case ARM::SBCSSrr:
case ARM::VABDLsv2i64:
case ARM::VABDLsv4i32:
case ARM::VABDLsv8i16:
case ARM::VABDLuv2i64:
case ARM::VABDLuv4i32:
case ARM::VABDLuv8i16:
case ARM::VABDsv16i8:
case ARM::VABDsv2i32:
case ARM::VABDsv4i16:
case ARM::VABDsv4i32:
case ARM::VABDsv8i16:
case ARM::VABDsv8i8:
case ARM::VABDuv16i8:
case ARM::VABDuv2i32:
case ARM::VABDuv4i16:
case ARM::VABDuv4i32:
case ARM::VABDuv8i16:
case ARM::VABDuv8i8:
case ARM::VADDHNv2i32:
case ARM::VADDHNv4i16:
case ARM::VADDHNv8i8:
case ARM::VADDLsv2i64:
case ARM::VADDLsv4i32:
case ARM::VADDLsv8i16:
case ARM::VADDLuv2i64:
case ARM::VADDLuv4i32:
case ARM::VADDLuv8i16:
case ARM::VADDWsv2i64:
case ARM::VADDWsv4i32:
case ARM::VADDWsv8i16:
case ARM::VADDWuv2i64:
case ARM::VADDWuv4i32:
case ARM::VADDWuv8i16:
case ARM::VADDv16i8:
case ARM::VADDv1i64:
case ARM::VADDv2i32:
case ARM::VADDv2i64:
case ARM::VADDv4i16:
case ARM::VADDv4i32:
case ARM::VADDv8i16:
case ARM::VADDv8i8:
case ARM::VCEQv16i8:
case ARM::VCEQv2i32:
case ARM::VCEQv4i16:
case ARM::VCEQv4i32:
case ARM::VCEQv8i16:
case ARM::VCEQv8i8:
case ARM::VCGEsv16i8:
case ARM::VCGEsv2i32:
case ARM::VCGEsv4i16:
case ARM::VCGEsv4i32:
case ARM::VCGEsv8i16:
case ARM::VCGEsv8i8:
case ARM::VCGEuv16i8:
case ARM::VCGEuv2i32:
case ARM::VCGEuv4i16:
case ARM::VCGEuv4i32:
case ARM::VCGEuv8i16:
case ARM::VCGEuv8i8:
case ARM::VCGTsv16i8:
case ARM::VCGTsv2i32:
case ARM::VCGTsv4i16:
case ARM::VCGTsv4i32:
case ARM::VCGTsv8i16:
case ARM::VCGTsv8i8:
case ARM::VCGTuv16i8:
case ARM::VCGTuv2i32:
case ARM::VCGTuv4i16:
case ARM::VCGTuv4i32:
case ARM::VCGTuv8i16:
case ARM::VCGTuv8i8:
case ARM::VHADDsv16i8:
case ARM::VHADDsv2i32:
case ARM::VHADDsv4i16:
case ARM::VHADDsv4i32:
case ARM::VHADDsv8i16:
case ARM::VHADDsv8i8:
case ARM::VHADDuv16i8:
case ARM::VHADDuv2i32:
case ARM::VHADDuv4i16:
case ARM::VHADDuv4i32:
case ARM::VHADDuv8i16:
case ARM::VHADDuv8i8:
case ARM::VHSUBsv16i8:
case ARM::VHSUBsv2i32:
case ARM::VHSUBsv4i16:
case ARM::VHSUBsv4i32:
case ARM::VHSUBsv8i16:
case ARM::VHSUBsv8i8:
case ARM::VHSUBuv16i8:
case ARM::VHSUBuv2i32:
case ARM::VHSUBuv4i16:
case ARM::VHSUBuv4i32:
case ARM::VHSUBuv8i16:
case ARM::VHSUBuv8i8:
case ARM::VMAXsv16i8:
case ARM::VMAXsv2i32:
case ARM::VMAXsv4i16:
case ARM::VMAXsv4i32:
case ARM::VMAXsv8i16:
case ARM::VMAXsv8i8:
case ARM::VMAXuv16i8:
case ARM::VMAXuv2i32:
case ARM::VMAXuv4i16:
case ARM::VMAXuv4i32:
case ARM::VMAXuv8i16:
case ARM::VMAXuv8i8:
case ARM::VMINsv16i8:
case ARM::VMINsv2i32:
case ARM::VMINsv4i16:
case ARM::VMINsv4i32:
case ARM::VMINsv8i16:
case ARM::VMINsv8i8:
case ARM::VMINuv16i8:
case ARM::VMINuv2i32:
case ARM::VMINuv4i16:
case ARM::VMINuv4i32:
case ARM::VMINuv8i16:
case ARM::VMINuv8i8:
case ARM::VMULLsv2i64:
case ARM::VMULLsv4i32:
case ARM::VMULLsv8i16:
case ARM::VMULLuv2i64:
case ARM::VMULLuv4i32:
case ARM::VMULLuv8i16:
case ARM::VMULv16i8:
case ARM::VMULv2i32:
case ARM::VMULv4i16:
case ARM::VMULv4i32:
case ARM::VMULv8i16:
case ARM::VMULv8i8:
case ARM::VPADDi16:
case ARM::VPADDi32:
case ARM::VPADDi8:
case ARM::VPMAXs16:
case ARM::VPMAXs32:
case ARM::VPMAXs8:
case ARM::VPMAXu16:
case ARM::VPMAXu32:
case ARM::VPMAXu8:
case ARM::VPMINs16:
case ARM::VPMINs32:
case ARM::VPMINs8:
case ARM::VPMINu16:
case ARM::VPMINu32:
case ARM::VPMINu8:
case ARM::VQADDsv16i8:
case ARM::VQADDsv1i64:
case ARM::VQADDsv2i32:
case ARM::VQADDsv2i64:
case ARM::VQADDsv4i16:
case ARM::VQADDsv4i32:
case ARM::VQADDsv8i16:
case ARM::VQADDsv8i8:
case ARM::VQADDuv16i8:
case ARM::VQADDuv1i64:
case ARM::VQADDuv2i32:
case ARM::VQADDuv2i64:
case ARM::VQADDuv4i16:
case ARM::VQADDuv4i32:
case ARM::VQADDuv8i16:
case ARM::VQADDuv8i8:
case ARM::VQDMULHv2i32:
case ARM::VQDMULHv4i16:
case ARM::VQDMULHv4i32:
case ARM::VQDMULHv8i16:
case ARM::VQDMULLv2i64:
case ARM::VQDMULLv4i32:
case ARM::VQRDMULHv2i32:
case ARM::VQRDMULHv4i16:
case ARM::VQRDMULHv4i32:
case ARM::VQRDMULHv8i16:
case ARM::VQRSHLsv16i8:
case ARM::VQRSHLsv1i64:
case ARM::VQRSHLsv2i32:
case ARM::VQRSHLsv2i64:
case ARM::VQRSHLsv4i16:
case ARM::VQRSHLsv4i32:
case ARM::VQRSHLsv8i16:
case ARM::VQRSHLsv8i8:
case ARM::VQRSHLuv16i8:
case ARM::VQRSHLuv1i64:
case ARM::VQRSHLuv2i32:
case ARM::VQRSHLuv2i64:
case ARM::VQRSHLuv4i16:
case ARM::VQRSHLuv4i32:
case ARM::VQRSHLuv8i16:
case ARM::VQRSHLuv8i8:
case ARM::VQRSHRNsv2i32:
case ARM::VQRSHRNsv4i16:
case ARM::VQRSHRNsv8i8:
case ARM::VQRSHRNuv2i32:
case ARM::VQRSHRNuv4i16:
case ARM::VQRSHRNuv8i8:
case ARM::VQRSHRUNv2i32:
case ARM::VQRSHRUNv4i16:
case ARM::VQRSHRUNv8i8:
case ARM::VQSHLsiv16i8:
case ARM::VQSHLsiv1i64:
case ARM::VQSHLsiv2i32:
case ARM::VQSHLsiv2i64:
case ARM::VQSHLsiv4i16:
case ARM::VQSHLsiv4i32:
case ARM::VQSHLsiv8i16:
case ARM::VQSHLsiv8i8:
case ARM::VQSHLsuv16i8:
case ARM::VQSHLsuv1i64:
case ARM::VQSHLsuv2i32:
case ARM::VQSHLsuv2i64:
case ARM::VQSHLsuv4i16:
case ARM::VQSHLsuv4i32:
case ARM::VQSHLsuv8i16:
case ARM::VQSHLsuv8i8:
case ARM::VQSHLsv16i8:
case ARM::VQSHLsv1i64:
case ARM::VQSHLsv2i32:
case ARM::VQSHLsv2i64:
case ARM::VQSHLsv4i16:
case ARM::VQSHLsv4i32:
case ARM::VQSHLsv8i16:
case ARM::VQSHLsv8i8:
case ARM::VQSHLuiv16i8:
case ARM::VQSHLuiv1i64:
case ARM::VQSHLuiv2i32:
case ARM::VQSHLuiv2i64:
case ARM::VQSHLuiv4i16:
case ARM::VQSHLuiv4i32:
case ARM::VQSHLuiv8i16:
case ARM::VQSHLuiv8i8:
case ARM::VQSHLuv16i8:
case ARM::VQSHLuv1i64:
case ARM::VQSHLuv2i32:
case ARM::VQSHLuv2i64:
case ARM::VQSHLuv4i16:
case ARM::VQSHLuv4i32:
case ARM::VQSHLuv8i16:
case ARM::VQSHLuv8i8:
case ARM::VQSHRNsv2i32:
case ARM::VQSHRNsv4i16:
case ARM::VQSHRNsv8i8:
case ARM::VQSHRNuv2i32:
case ARM::VQSHRNuv4i16:
case ARM::VQSHRNuv8i8:
case ARM::VQSHRUNv2i32:
case ARM::VQSHRUNv4i16:
case ARM::VQSHRUNv8i8:
case ARM::VQSUBsv16i8:
case ARM::VQSUBsv1i64:
case ARM::VQSUBsv2i32:
case ARM::VQSUBsv2i64:
case ARM::VQSUBsv4i16:
case ARM::VQSUBsv4i32:
case ARM::VQSUBsv8i16:
case ARM::VQSUBsv8i8:
case ARM::VQSUBuv16i8:
case ARM::VQSUBuv1i64:
case ARM::VQSUBuv2i32:
case ARM::VQSUBuv2i64:
case ARM::VQSUBuv4i16:
case ARM::VQSUBuv4i32:
case ARM::VQSUBuv8i16:
case ARM::VQSUBuv8i8:
case ARM::VRADDHNv2i32:
case ARM::VRADDHNv4i16:
case ARM::VRADDHNv8i8:
case ARM::VRHADDsv16i8:
case ARM::VRHADDsv2i32:
case ARM::VRHADDsv4i16:
case ARM::VRHADDsv4i32:
case ARM::VRHADDsv8i16:
case ARM::VRHADDsv8i8:
case ARM::VRHADDuv16i8:
case ARM::VRHADDuv2i32:
case ARM::VRHADDuv4i16:
case ARM::VRHADDuv4i32:
case ARM::VRHADDuv8i16:
case ARM::VRHADDuv8i8:
case ARM::VRSHLsv16i8:
case ARM::VRSHLsv1i64:
case ARM::VRSHLsv2i32:
case ARM::VRSHLsv2i64:
case ARM::VRSHLsv4i16:
case ARM::VRSHLsv4i32:
case ARM::VRSHLsv8i16:
case ARM::VRSHLsv8i8:
case ARM::VRSHLuv16i8:
case ARM::VRSHLuv1i64:
case ARM::VRSHLuv2i32:
case ARM::VRSHLuv2i64:
case ARM::VRSHLuv4i16:
case ARM::VRSHLuv4i32:
case ARM::VRSHLuv8i16:
case ARM::VRSHLuv8i8:
case ARM::VRSHRNv2i32:
case ARM::VRSHRNv4i16:
case ARM::VRSHRNv8i8:
case ARM::VRSHRsv16i8:
case ARM::VRSHRsv1i64:
case ARM::VRSHRsv2i32:
case ARM::VRSHRsv2i64:
case ARM::VRSHRsv4i16:
case ARM::VRSHRsv4i32:
case ARM::VRSHRsv8i16:
case ARM::VRSHRsv8i8:
case ARM::VRSHRuv16i8:
case ARM::VRSHRuv1i64:
case ARM::VRSHRuv2i32:
case ARM::VRSHRuv2i64:
case ARM::VRSHRuv4i16:
case ARM::VRSHRuv4i32:
case ARM::VRSHRuv8i16:
case ARM::VRSHRuv8i8:
case ARM::VRSUBHNv2i32:
case ARM::VRSUBHNv4i16:
case ARM::VRSUBHNv8i8:
case ARM::VSHLLi16:
case ARM::VSHLLi32:
case ARM::VSHLLi8:
case ARM::VSHLLsv2i64:
case ARM::VSHLLsv4i32:
case ARM::VSHLLsv8i16:
case ARM::VSHLLuv2i64:
case ARM::VSHLLuv4i32:
case ARM::VSHLLuv8i16:
case ARM::VSHLiv16i8:
case ARM::VSHLiv1i64:
case ARM::VSHLiv2i32:
case ARM::VSHLiv2i64:
case ARM::VSHLiv4i16:
case ARM::VSHLiv4i32:
case ARM::VSHLiv8i16:
case ARM::VSHLiv8i8:
case ARM::VSHLsv16i8:
case ARM::VSHLsv1i64:
case ARM::VSHLsv2i32:
case ARM::VSHLsv2i64:
case ARM::VSHLsv4i16:
case ARM::VSHLsv4i32:
case ARM::VSHLsv8i16:
case ARM::VSHLsv8i8:
case ARM::VSHLuv16i8:
case ARM::VSHLuv1i64:
case ARM::VSHLuv2i32:
case ARM::VSHLuv2i64:
case ARM::VSHLuv4i16:
case ARM::VSHLuv4i32:
case ARM::VSHLuv8i16:
case ARM::VSHLuv8i8:
case ARM::VSHRNv2i32:
case ARM::VSHRNv4i16:
case ARM::VSHRNv8i8:
case ARM::VSHRsv16i8:
case ARM::VSHRsv1i64:
case ARM::VSHRsv2i32:
case ARM::VSHRsv2i64:
case ARM::VSHRsv4i16:
case ARM::VSHRsv4i32:
case ARM::VSHRsv8i16:
case ARM::VSHRsv8i8:
case ARM::VSHRuv16i8:
case ARM::VSHRuv1i64:
case ARM::VSHRuv2i32:
case ARM::VSHRuv2i64:
case ARM::VSHRuv4i16:
case ARM::VSHRuv4i32:
case ARM::VSHRuv8i16:
case ARM::VSHRuv8i8:
case ARM::VSUBHNv2i32:
case ARM::VSUBHNv4i16:
case ARM::VSUBHNv8i8:
case ARM::VSUBLsv2i64:
case ARM::VSUBLsv4i32:
case ARM::VSUBLsv8i16:
case ARM::VSUBLuv2i64:
case ARM::VSUBLuv4i32:
case ARM::VSUBLuv8i16:
case ARM::VSUBWsv2i64:
case ARM::VSUBWsv4i32:
case ARM::VSUBWsv8i16:
case ARM::VSUBWuv2i64:
case ARM::VSUBWuv4i32:
case ARM::VSUBWuv8i16:
case ARM::VSUBv16i8:
case ARM::VSUBv1i64:
case ARM::VSUBv2i32:
case ARM::VSUBv2i64:
case ARM::VSUBv4i16:
case ARM::VSUBv4i32:
case ARM::VSUBv8i16:
case ARM::VSUBv8i8:
case ARM::t2LDRDpci:
case ARM::t2MOVTi16:
case ARM::t2SUBrSPi12_:
case ARM::t2SUBrSPi_:
case ARM::tADDhirr:
case ARM::tMOVCCi:
case ARM::tMOVCCr: printOperand(MI, 2); break;
case ARM::ADCSSrs:
case ARM::MOVCCs:
case ARM::RSCSrs:
case ARM::SBCSSrs: printSORegOperand(MI, 2); break;
case ARM::BFC:
case ARM::t2BFC: printBitfieldInvMaskImmOperand(MI, 2); break;
case ARM::CLZ:
case ARM::CMNzrr:
case ARM::CMPrr:
case ARM::CMPzrr:
case ARM::MOVi16:
case ARM::RBIT:
case ARM::REV:
case ARM::REV16:
case ARM::REVSH:
case ARM::SXTB16r:
case ARM::SXTBr:
case ARM::SXTHr:
case ARM::TEQrr:
case ARM::TSTrr:
case ARM::UXTB16r:
case ARM::UXTBr:
case ARM::UXTHr:
case ARM::VCNTd:
case ARM::VCNTq:
case ARM::VDUP16d:
case ARM::VDUP16q:
case ARM::VDUP32d:
case ARM::VDUP32q:
case ARM::VDUP8d:
case ARM::VDUP8q:
case ARM::VDUPfd:
case ARM::VDUPfq:
case ARM::VMOVDneon:
case ARM::VMOVQ:
case ARM::VMOVRS:
case ARM::VMOVSR:
case ARM::VMVNd:
case ARM::VMVNq:
case ARM::VREV16d8:
case ARM::VREV16q8:
case ARM::VREV32d16:
case ARM::VREV32d8:
case ARM::VREV32q16:
case ARM::VREV32q8:
case ARM::VREV64d16:
case ARM::VREV64d32:
case ARM::VREV64d8:
case ARM::VREV64df:
case ARM::VREV64q16:
case ARM::VREV64q32:
case ARM::VREV64q8:
case ARM::VREV64qf:
case ARM::VSWPd:
case ARM::VSWPq:
case ARM::VTRNd16:
case ARM::VTRNd32:
case ARM::VTRNd8:
case ARM::VTRNq16:
case ARM::VTRNq32:
case ARM::VTRNq8:
case ARM::VUZPd16:
case ARM::VUZPd32:
case ARM::VUZPd8:
case ARM::VUZPq16:
case ARM::VUZPq32:
case ARM::VUZPq8:
case ARM::VZIPd16:
case ARM::VZIPd32:
case ARM::VZIPd8:
case ARM::VZIPq16:
case ARM::VZIPq32:
case ARM::VZIPq8:
case ARM::t2CLZ:
case ARM::t2MOVi16:
case ARM::t2RBIT:
case ARM::t2SXTB16r:
case ARM::t2UXTB16r:
case ARM::tCMNz:
case ARM::tCMPhir:
case ARM::tCMPi8:
case ARM::tCMPr:
case ARM::tCMPzhir:
case ARM::tCMPzi8:
case ARM::tCMPzr:
case ARM::tLDRcp:
case ARM::tREV:
case ARM::tREV16:
case ARM::tREVSH:
case ARM::tSXTB:
case ARM::tSXTH:
case ARM::tTST:
case ARM::tUXTB:
case ARM::tUXTH: printOperand(MI, 1); break;
case ARM::CMNzri:
case ARM::CMPri:
case ARM::CMPzri:
case ARM::TEQri:
case ARM::TSTri: printSOImmOperand(MI, 1); break;
case ARM::CMNzrs:
case ARM::CMPrs:
case ARM::CMPzrs:
case ARM::TEQrs:
case ARM::TSTrs: printSORegOperand(MI, 1); break;
case ARM::LDC2_OFFSET:
case ARM::LDC_OFFSET:
case ARM::STC2_OFFSET:
case ARM::STC_OFFSET: printAddrMode2Operand(MI, 2); break;
case ARM::LDR:
case ARM::LDRB:
case ARM::LDRcp:
case ARM::STR:
case ARM::STRB: printAddrMode2Operand(MI, 1); break;
case ARM::LDRD:
case ARM::STRD: printAddrMode3Operand(MI, 2); break;
case ARM::LDRH:
case ARM::LDRSB:
case ARM::LDRSH:
case ARM::STRH: printAddrMode3Operand(MI, 1); break;
case ARM::MOVi2pieces: printSOImm2PartOperand(MI, 1); break;
case ARM::VABALsv2i64:
case ARM::VABALsv4i32:
case ARM::VABALsv8i16:
case ARM::VABALuv2i64:
case ARM::VABALuv4i32:
case ARM::VABALuv8i16:
case ARM::VABAsv16i8:
case ARM::VABAsv2i32:
case ARM::VABAsv4i16:
case ARM::VABAsv4i32:
case ARM::VABAsv8i16:
case ARM::VABAsv8i8:
case ARM::VABAuv16i8:
case ARM::VABAuv2i32:
case ARM::VABAuv4i16:
case ARM::VABAuv4i32:
case ARM::VABAuv8i16:
case ARM::VABAuv8i8:
case ARM::VMLALsv2i64:
case ARM::VMLALsv4i32:
case ARM::VMLALsv8i16:
case ARM::VMLALuv2i64:
case ARM::VMLALuv4i32:
case ARM::VMLALuv8i16:
case ARM::VMLAv16i8:
case ARM::VMLAv2i32:
case ARM::VMLAv4i16:
case ARM::VMLAv4i32:
case ARM::VMLAv8i16:
case ARM::VMLAv8i8:
case ARM::VMLSLsv2i64:
case ARM::VMLSLsv4i32:
case ARM::VMLSLsv8i16:
case ARM::VMLSLuv2i64:
case ARM::VMLSLuv4i32:
case ARM::VMLSLuv8i16:
case ARM::VMLSv16i8:
case ARM::VMLSv2i32:
case ARM::VMLSv4i16:
case ARM::VMLSv4i32:
case ARM::VMLSv8i16:
case ARM::VMLSv8i8:
case ARM::VQDMLALv2i64:
case ARM::VQDMLALv4i32:
case ARM::VQDMLSLv2i64:
case ARM::VQDMLSLv4i32:
case ARM::VRSRAsv16i8:
case ARM::VRSRAsv1i64:
case ARM::VRSRAsv2i32:
case ARM::VRSRAsv2i64:
case ARM::VRSRAsv4i16:
case ARM::VRSRAsv4i32:
case ARM::VRSRAsv8i16:
case ARM::VRSRAsv8i8:
case ARM::VRSRAuv16i8:
case ARM::VRSRAuv1i64:
case ARM::VRSRAuv2i32:
case ARM::VRSRAuv2i64:
case ARM::VRSRAuv4i16:
case ARM::VRSRAuv4i32:
case ARM::VRSRAuv8i16:
case ARM::VRSRAuv8i8:
case ARM::VSRAsv16i8:
case ARM::VSRAsv1i64:
case ARM::VSRAsv2i32:
case ARM::VSRAsv2i64:
case ARM::VSRAsv4i16:
case ARM::VSRAsv4i32:
case ARM::VSRAsv8i16:
case ARM::VSRAsv8i8:
case ARM::VSRAuv16i8:
case ARM::VSRAuv1i64:
case ARM::VSRAuv2i32:
case ARM::VSRAuv2i64:
case ARM::VSRAuv4i16:
case ARM::VSRAuv4i32:
case ARM::VSRAuv8i16:
case ARM::VSRAuv8i8:
case ARM::tADDi3:
case ARM::tADDrr:
case ARM::tASRri:
case ARM::tLSLri:
case ARM::tLSRri:
case ARM::tSUBi3:
case ARM::tSUBrr: printOperand(MI, 3); break;
case ARM::VDUPfdf:
case ARM::VDUPfqf: printOperand(MI, 1, "lane"); break;
case ARM::VLDRD:
case ARM::VLDRS:
case ARM::VSTRD:
case ARM::VSTRS: printAddrMode5Operand(MI, 1); break;
case ARM::t2LDRBT:
case ARM::t2LDRBi8:
case ARM::t2LDRHT:
case ARM::t2LDRHi8:
case ARM::t2LDRSBT:
case ARM::t2LDRSBi8:
case ARM::t2LDRSHT:
case ARM::t2LDRSHi8:
case ARM::t2LDRT:
case ARM::t2LDRi8:
case ARM::t2STRBT:
case ARM::t2STRBi8:
case ARM::t2STRHT:
case ARM::t2STRHi8:
case ARM::t2STRT:
case ARM::t2STRi8: printT2AddrModeImm8Operand(MI, 1); break;
case ARM::t2LDRDi8:
case ARM::t2STRDi8: printT2AddrModeImm8s4Operand(MI, 2); break;
case ARM::t2SUBrSPs_: printT2SOOperand(MI, 2); break;
case ARM::tADDrSPi: printThumbS4ImmOperand(MI, 2); break;
case ARM::tLDR:
case ARM::tLDRi:
case ARM::tSTR:
case ARM::tSTRi: printThumbAddrModeS4Operand(MI, 1); break;
case ARM::tLDRB:
case ARM::tLDRBi:
case ARM::tSTRB:
case ARM::tSTRBi: printThumbAddrModeS1Operand(MI, 1); break;
case ARM::tLDRH:
case ARM::tLDRHi:
case ARM::tSTRH:
case ARM::tSTRHi: printThumbAddrModeS2Operand(MI, 1); break;
case ARM::tLDRSB:
case ARM::tLDRSH: printThumbAddrModeRROperand(MI, 1); break;
case ARM::tLDRspi:
case ARM::tRestore:
case ARM::tSTRspi:
case ARM::tSpill: printThumbAddrModeSPOperand(MI, 1); break;
case ARM::tMUL: printOperand(MI, 0); break;
}
return;
break;
case ARM::ADCrr:
case ARM::ADDrr:
case ARM::ANDrr:
case ARM::BICrr:
case ARM::BKPT:
case ARM::BXJ:
case ARM::Bcc:
case ARM::DBG:
case ARM::EORrr:
case ARM::MOVr:
case ARM::MSR:
case ARM::MSRsys:
case ARM::MUL:
case ARM::MVNr:
case ARM::ORRrr:
case ARM::RFE:
case ARM::SBCrr:
case ARM::SMC:
case ARM::SRS:
case ARM::SRSW:
case ARM::SUBrr:
case ARM::SVC:
case ARM::VABSv16i8:
case ARM::VABSv2i32:
case ARM::VABSv4i16:
case ARM::VABSv4i32:
case ARM::VABSv8i16:
case ARM::VABSv8i8:
case ARM::VCLSv16i8:
case ARM::VCLSv2i32:
case ARM::VCLSv4i16:
case ARM::VCLSv4i32:
case ARM::VCLSv8i16:
case ARM::VCLSv8i8:
case ARM::VCLZv16i8:
case ARM::VCLZv2i32:
case ARM::VCLZv4i16:
case ARM::VCLZv4i32:
case ARM::VCLZv8i16:
case ARM::VCLZv8i8:
case ARM::VMOVLsv2i64:
case ARM::VMOVLsv4i32:
case ARM::VMOVLsv8i16:
case ARM::VMOVLuv2i64:
case ARM::VMOVLuv4i32:
case ARM::VMOVLuv8i16:
case ARM::VMOVNv2i32:
case ARM::VMOVNv4i16:
case ARM::VMOVNv8i8:
case ARM::VNEGs16d:
case ARM::VNEGs16q:
case ARM::VNEGs32d:
case ARM::VNEGs32q:
case ARM::VNEGs8d:
case ARM::VNEGs8q:
case ARM::VPADALsv16i8:
case ARM::VPADALsv2i32:
case ARM::VPADALsv4i16:
case ARM::VPADALsv4i32:
case ARM::VPADALsv8i16:
case ARM::VPADALsv8i8:
case ARM::VPADALuv16i8:
case ARM::VPADALuv2i32:
case ARM::VPADALuv4i16:
case ARM::VPADALuv4i32:
case ARM::VPADALuv8i16:
case ARM::VPADALuv8i8:
case ARM::VPADDLsv16i8:
case ARM::VPADDLsv2i32:
case ARM::VPADDLsv4i16:
case ARM::VPADDLsv4i32:
case ARM::VPADDLsv8i16:
case ARM::VPADDLsv8i8:
case ARM::VPADDLuv16i8:
case ARM::VPADDLuv2i32:
case ARM::VPADDLuv4i16:
case ARM::VPADDLuv4i32:
case ARM::VPADDLuv8i16:
case ARM::VPADDLuv8i8:
case ARM::VQABSv16i8:
case ARM::VQABSv2i32:
case ARM::VQABSv4i16:
case ARM::VQABSv4i32:
case ARM::VQABSv8i16:
case ARM::VQABSv8i8:
case ARM::VQMOVNsuv2i32:
case ARM::VQMOVNsuv4i16:
case ARM::VQMOVNsuv8i8:
case ARM::VQMOVNsv2i32:
case ARM::VQMOVNsv4i16:
case ARM::VQMOVNsv8i8:
case ARM::VQMOVNuv2i32:
case ARM::VQMOVNuv4i16:
case ARM::VQMOVNuv8i8:
case ARM::VQNEGv16i8:
case ARM::VQNEGv2i32:
case ARM::VQNEGv4i16:
case ARM::VQNEGv4i32:
case ARM::VQNEGv8i16:
case ARM::VQNEGv8i8:
case ARM::VRECPEd:
case ARM::VRECPEq:
case ARM::VRSQRTEd:
case ARM::VRSQRTEq:
case ARM::t2BXJ:
case ARM::t2DBG:
case ARM::t2LEApcrel:
case ARM::t2MSR:
case ARM::t2MSRsys:
case ARM::t2RFEDB:
case ARM::t2RFEIA:
case ARM::t2SMC:
case ARM::t2SRSDB:
case ARM::t2SRSDBW:
case ARM::t2SRSIA:
case ARM::t2SRSIAW:
case ARM::tADC:
case ARM::tADDi8:
case ARM::tADDrSP:
case ARM::tADDspr:
case ARM::tADDspr_:
case ARM::tAND:
case ARM::tANDsp:
case ARM::tASRrr:
case ARM::tBIC:
case ARM::tBcc:
case ARM::tCBNZ:
case ARM::tCBZ:
case ARM::tEOR:
case ARM::tLSLrr:
case ARM::tLSRrr:
case ARM::tMOVSr:
case ARM::tMOVgpr2gpr:
case ARM::tMOVgpr2tgpr:
case ARM::tMOVr:
case ARM::tMOVtgpr2gpr:
case ARM::tORR:
case ARM::tROR:
case ARM::tSBC:
case ARM::tSUBi8:
case ARM::tSVC:
return;
break;
case ARM::ADDSri:
case ARM::ADDSrr:
case ARM::ADDSrs:
case ARM::BFI:
case ARM::QADD:
case ARM::QADD16:
case ARM::QADD8:
case ARM::QASX:
case ARM::QDADD:
case ARM::QDSUB:
case ARM::QSAX:
case ARM::QSUB:
case ARM::QSUB16:
case ARM::QSUB8:
case ARM::RSBSri:
case ARM::RSBSrs:
case ARM::SADD16:
case ARM::SADD8:
case ARM::SASX:
case ARM::SEL:
case ARM::SHADD16:
case ARM::SHADD8:
case ARM::SHASX:
case ARM::SHSAX:
case ARM::SHSUB16:
case ARM::SHSUB8:
case ARM::SMMUL:
case ARM::SMMULR:
case ARM::SMUAD:
case ARM::SMUADX:
case ARM::SMULBB:
case ARM::SMULBT:
case ARM::SMULTB:
case ARM::SMULTT:
case ARM::SMULWB:
case ARM::SMULWT:
case ARM::SMUSD:
case ARM::SMUSDX:
case ARM::SSAT16:
case ARM::SSAX:
case ARM::SSUB16:
case ARM::SSUB8:
case ARM::SUBSri:
case ARM::SUBSrr:
case ARM::SUBSrs:
case ARM::SXTAB16rr:
case ARM::SXTABrr:
case ARM::SXTAHrr:
case ARM::UADD16:
case ARM::UADD8:
case ARM::UASX:
case ARM::UHADD16:
case ARM::UHADD8:
case ARM::UHASX:
case ARM::UHSAX:
case ARM::UHSUB16:
case ARM::UHSUB8:
case ARM::UQADD16:
case ARM::UQADD8:
case ARM::UQASX:
case ARM::UQSAX:
case ARM::UQSUB16:
case ARM::UQSUB8:
case ARM::USAD8:
case ARM::USAT16:
case ARM::USAX:
case ARM::USUB16:
case ARM::USUB8:
case ARM::UXTAB16rr:
case ARM::UXTABrr:
case ARM::UXTAHrr:
case ARM::VANDd:
case ARM::VANDq:
case ARM::VBICd:
case ARM::VBICq:
case ARM::VEORd:
case ARM::VEORq:
case ARM::VMOVDRR:
case ARM::VMOVRRD:
case ARM::VORNd:
case ARM::VORNq:
case ARM::VORRd:
case ARM::VORRq:
case ARM::VTSTv16i8:
case ARM::VTSTv2i32:
case ARM::VTSTv4i16:
case ARM::VTSTv4i32:
case ARM::VTSTv8i16:
case ARM::VTSTv8i8:
case ARM::t2ADCSri:
case ARM::t2ADCri:
case ARM::t2ADDrSPi12:
case ARM::t2ADDri12:
case ARM::t2ANDri:
case ARM::t2BICri:
case ARM::t2EORri:
case ARM::t2MUL:
case ARM::t2ORNri:
case ARM::t2ORNrr:
case ARM::t2ORNrs:
case ARM::t2ORRri:
case ARM::t2QADD:
case ARM::t2QADD16:
case ARM::t2QADD8:
case ARM::t2QASX:
case ARM::t2QDADD:
case ARM::t2QDSUB:
case ARM::t2QSAX:
case ARM::t2QSUB:
case ARM::t2QSUB16:
case ARM::t2QSUB8:
case ARM::t2RSBSrs:
case ARM::t2RSBrs:
case ARM::t2SADD16:
case ARM::t2SADD8:
case ARM::t2SASX:
case ARM::t2SBCSri:
case ARM::t2SBCri:
case ARM::t2SDIV:
case ARM::t2SEL:
case ARM::t2SHADD16:
case ARM::t2SHADD8:
case ARM::t2SHASX:
case ARM::t2SHSAX:
case ARM::t2SHSUB16:
case ARM::t2SHSUB8:
case ARM::t2SMMUL:
case ARM::t2SMMULR:
case ARM::t2SMUAD:
case ARM::t2SMUADX:
case ARM::t2SMULBB:
case ARM::t2SMULBT:
case ARM::t2SMULTB:
case ARM::t2SMULTT:
case ARM::t2SMULWB:
case ARM::t2SMULWT:
case ARM::t2SMUSD:
case ARM::t2SMUSDX:
case ARM::t2SSAT16:
case ARM::t2SSAX:
case ARM::t2SSUB16:
case ARM::t2SSUB8:
case ARM::t2SUBrSPi12:
case ARM::t2SUBrSPs:
case ARM::t2SUBri12:
case ARM::t2SXTAB16rr:
case ARM::t2SXTABrr:
case ARM::t2SXTAHrr:
case ARM::t2UADD16:
case ARM::t2UADD8:
case ARM::t2UASX:
case ARM::t2UDIV:
case ARM::t2UHADD16:
case ARM::t2UHADD8:
case ARM::t2UHASX:
case ARM::t2UHSAX:
case ARM::t2UHSUB16:
case ARM::t2UHSUB8:
case ARM::t2UQADD16:
case ARM::t2UQADD8:
case ARM::t2UQASX:
case ARM::t2UQSAX:
case ARM::t2UQSUB16:
case ARM::t2UQSUB8:
case ARM::t2USAD8:
case ARM::t2USAT16:
case ARM::t2USAX:
case ARM::t2USUB16:
case ARM::t2USUB8:
case ARM::t2UXTAB16rr:
case ARM::t2UXTABrr:
case ARM::t2UXTAHrr:
O << ", ";
printOperand(MI, 1);
O << ", ";
switch (MI->getOpcode()) {
case ARM::ADDSri:
case ARM::RSBSri:
case ARM::SUBSri: printSOImmOperand(MI, 2); break;
case ARM::ADDSrr:
case ARM::QADD:
case ARM::QADD16:
case ARM::QADD8:
case ARM::QASX:
case ARM::QDADD:
case ARM::QDSUB:
case ARM::QSAX:
case ARM::QSUB:
case ARM::QSUB16:
case ARM::QSUB8:
case ARM::SADD16:
case ARM::SADD8:
case ARM::SASX:
case ARM::SEL:
case ARM::SHADD16:
case ARM::SHADD8:
case ARM::SHASX:
case ARM::SHSAX:
case ARM::SHSUB16:
case ARM::SHSUB8:
case ARM::SMMUL:
case ARM::SMMULR:
case ARM::SMUAD:
case ARM::SMUADX:
case ARM::SMULBB:
case ARM::SMULBT:
case ARM::SMULTB:
case ARM::SMULTT:
case ARM::SMULWB:
case ARM::SMULWT:
case ARM::SMUSD:
case ARM::SMUSDX:
case ARM::SSAT16:
case ARM::SSAX:
case ARM::SSUB16:
case ARM::SSUB8:
case ARM::SUBSrr:
case ARM::SXTAB16rr:
case ARM::SXTABrr:
case ARM::SXTAHrr:
case ARM::UADD16:
case ARM::UADD8:
case ARM::UASX:
case ARM::UHADD16:
case ARM::UHADD8:
case ARM::UHASX:
case ARM::UHSAX:
case ARM::UHSUB16:
case ARM::UHSUB8:
case ARM::UQADD16:
case ARM::UQADD8:
case ARM::UQASX:
case ARM::UQSAX:
case ARM::UQSUB16:
case ARM::UQSUB8:
case ARM::USAD8:
case ARM::USAT16:
case ARM::USAX:
case ARM::USUB16:
case ARM::USUB8:
case ARM::UXTAB16rr:
case ARM::UXTABrr:
case ARM::UXTAHrr:
case ARM::VANDd:
case ARM::VANDq:
case ARM::VBICd:
case ARM::VBICq:
case ARM::VEORd:
case ARM::VEORq:
case ARM::VMOVDRR:
case ARM::VMOVRRD:
case ARM::VORNd:
case ARM::VORNq:
case ARM::VORRd:
case ARM::VORRq:
case ARM::VTSTv16i8:
case ARM::VTSTv2i32:
case ARM::VTSTv4i16:
case ARM::VTSTv4i32:
case ARM::VTSTv8i16:
case ARM::VTSTv8i8:
case ARM::t2ADCSri:
case ARM::t2ADCri:
case ARM::t2ADDrSPi12:
case ARM::t2ADDri12:
case ARM::t2ANDri:
case ARM::t2BICri:
case ARM::t2EORri:
case ARM::t2MUL:
case ARM::t2ORNri:
case ARM::t2ORNrr:
case ARM::t2ORRri:
case ARM::t2QADD:
case ARM::t2QADD16:
case ARM::t2QADD8:
case ARM::t2QASX:
case ARM::t2QDADD:
case ARM::t2QDSUB:
case ARM::t2QSAX:
case ARM::t2QSUB:
case ARM::t2QSUB16:
case ARM::t2QSUB8:
case ARM::t2SADD16:
case ARM::t2SADD8:
case ARM::t2SASX:
case ARM::t2SBCSri:
case ARM::t2SBCri:
case ARM::t2SDIV:
case ARM::t2SEL:
case ARM::t2SHADD16:
case ARM::t2SHADD8:
case ARM::t2SHASX:
case ARM::t2SHSAX:
case ARM::t2SHSUB16:
case ARM::t2SHSUB8:
case ARM::t2SMMUL:
case ARM::t2SMMULR:
case ARM::t2SMUAD:
case ARM::t2SMUADX:
case ARM::t2SMULBB:
case ARM::t2SMULBT:
case ARM::t2SMULTB:
case ARM::t2SMULTT:
case ARM::t2SMULWB:
case ARM::t2SMULWT:
case ARM::t2SMUSD:
case ARM::t2SMUSDX:
case ARM::t2SSAT16:
case ARM::t2SSAX:
case ARM::t2SSUB16:
case ARM::t2SSUB8:
case ARM::t2SUBrSPi12:
case ARM::t2SUBri12:
case ARM::t2SXTAB16rr:
case ARM::t2SXTABrr:
case ARM::t2SXTAHrr:
case ARM::t2UADD16:
case ARM::t2UADD8:
case ARM::t2UASX:
case ARM::t2UDIV:
case ARM::t2UHADD16:
case ARM::t2UHADD8:
case ARM::t2UHASX:
case ARM::t2UHSAX:
case ARM::t2UHSUB16:
case ARM::t2UHSUB8:
case ARM::t2UQADD16:
case ARM::t2UQADD8:
case ARM::t2UQASX:
case ARM::t2UQSAX:
case ARM::t2UQSUB16:
case ARM::t2UQSUB8:
case ARM::t2USAD8:
case ARM::t2USAT16:
case ARM::t2USAX:
case ARM::t2USUB16:
case ARM::t2USUB8:
case ARM::t2UXTAB16rr:
case ARM::t2UXTABrr:
case ARM::t2UXTAHrr: printOperand(MI, 2); break;
case ARM::ADDSrs:
case ARM::RSBSrs:
case ARM::SUBSrs: printSORegOperand(MI, 2); break;
case ARM::BFI: printBitfieldInvMaskImmOperand(MI, 2); break;
case ARM::t2ORNrs:
case ARM::t2RSBSrs:
case ARM::t2RSBrs:
case ARM::t2SUBrSPs: printT2SOOperand(MI, 2); break;
}
return;
break;
case ARM::BR_JTadd:
O << " \n";
printJTBlockOperand(MI, 2);
return;
break;
case ARM::CDP:
printOperand(MI, 1);
O << ", cr";
printNoHashImmediate(MI, 2);
O << ", cr";
printNoHashImmediate(MI, 3);
O << ", cr";
printNoHashImmediate(MI, 4);
O << ", ";
printOperand(MI, 5);
return;
break;
case ARM::FCONSTD:
case ARM::FCONSTS:
case ARM::LDC2L_OFFSET:
case ARM::LDC2L_OPTION:
case ARM::LDC2L_POST:
case ARM::LDCL_OFFSET:
case ARM::LDCL_OPTION:
case ARM::LDCL_POST:
case ARM::MOVrx:
case ARM::MRS:
case ARM::MRSsys:
case ARM::PLDWi:
case ARM::PLDi:
case ARM::PLIi:
case ARM::RFEW:
case ARM::STC2L_OFFSET:
case ARM::STC2L_OPTION:
case ARM::STC2L_POST:
case ARM::STCL_OFFSET:
case ARM::STCL_OPTION:
case ARM::STCL_POST:
case ARM::VABSD:
case ARM::VABSS:
case ARM::VABSfd:
case ARM::VABSfd_sfp:
case ARM::VABSfq:
case ARM::VCEQzv16i8:
case ARM::VCEQzv2i32:
case ARM::VCEQzv4i16:
case ARM::VCEQzv4i32:
case ARM::VCEQzv8i16:
case ARM::VCEQzv8i8:
case ARM::VCGEzv16i8:
case ARM::VCGEzv2i32:
case ARM::VCGEzv4i16:
case ARM::VCGEzv4i32:
case ARM::VCGEzv8i16:
case ARM::VCGEzv8i8:
case ARM::VCGTzv16i8:
case ARM::VCGTzv2i32:
case ARM::VCGTzv4i16:
case ARM::VCGTzv4i32:
case ARM::VCGTzv8i16:
case ARM::VCGTzv8i8:
case ARM::VCLEzv16i8:
case ARM::VCLEzv2i32:
case ARM::VCLEzv4i16:
case ARM::VCLEzv4i32:
case ARM::VCLEzv8i16:
case ARM::VCLEzv8i8:
case ARM::VCLTzv16i8:
case ARM::VCLTzv2i32:
case ARM::VCLTzv4i16:
case ARM::VCLTzv4i32:
case ARM::VCLTzv8i16:
case ARM::VCLTzv8i8:
case ARM::VCMPD:
case ARM::VCMPED:
case ARM::VCMPES:
case ARM::VCMPS:
case ARM::VCVTf2xsd:
case ARM::VCVTf2xsq:
case ARM::VCVTf2xud:
case ARM::VCVTf2xuq:
case ARM::VCVTxs2fd:
case ARM::VCVTxs2fq:
case ARM::VCVTxu2fd:
case ARM::VCVTxu2fq:
case ARM::VMOVD:
case ARM::VMOVDcc:
case ARM::VMOVS:
case ARM::VMOVScc:
case ARM::VMRS:
case ARM::VNEGD:
case ARM::VNEGDcc:
case ARM::VNEGS:
case ARM::VNEGScc:
case ARM::VNEGf32q:
case ARM::VNEGfd:
case ARM::VNEGfd_sfp:
case ARM::VRECPEfd:
case ARM::VRECPEfq:
case ARM::VRSQRTEfd:
case ARM::VRSQRTEfq:
case ARM::VSLTOD:
case ARM::VSLTOS:
case ARM::VSQRTD:
case ARM::VSQRTS:
case ARM::VTOSLD:
case ARM::VTOSLS:
case ARM::VTOULD:
case ARM::VTOULS:
case ARM::VULTOD:
case ARM::VULTOS:
case ARM::t2CMNzri:
case ARM::t2CMNzrr:
case ARM::t2CMNzrs:
case ARM::t2CMPri:
case ARM::t2CMPrr:
case ARM::t2CMPrs:
case ARM::t2CMPzri:
case ARM::t2CMPzrr:
case ARM::t2CMPzrs:
case ARM::t2LDRBi12:
case ARM::t2LDRBpci:
case ARM::t2LDRBs:
case ARM::t2LDRHi12:
case ARM::t2LDRHpci:
case ARM::t2LDRHs:
case ARM::t2LDRSBi12:
case ARM::t2LDRSBpci:
case ARM::t2LDRSBs:
case ARM::t2LDRSHi12:
case ARM::t2LDRSHpci:
case ARM::t2LDRSHs:
case ARM::t2LDRi12:
case ARM::t2LDRpci:
case ARM::t2LDRs:
case ARM::t2MOVCCi:
case ARM::t2MOVCCr:
case ARM::t2MOVsra_flag:
case ARM::t2MOVsrl_flag:
case ARM::t2MRS:
case ARM::t2MRSsys:
case ARM::t2MVNr:
case ARM::t2MVNs:
case ARM::t2REV:
case ARM::t2REV16:
case ARM::t2REVSH:
case ARM::t2RFEDBW:
case ARM::t2RFEIAW:
case ARM::t2STRBi12:
case ARM::t2STRBs:
case ARM::t2STRHi12:
case ARM::t2STRHs:
case ARM::t2STRi12:
case ARM::t2STRs:
case ARM::t2SXTBr:
case ARM::t2SXTHr:
case ARM::t2TEQri:
case ARM::t2TEQrr:
case ARM::t2TEQrs:
case ARM::t2TSTri:
case ARM::t2TSTrr:
case ARM::t2TSTrs:
case ARM::t2UXTBr:
case ARM::t2UXTHr:
switch (MI->getOpcode()) {
case ARM::FCONSTD: printVFPf64ImmOperand(MI, 1); break;
case ARM::FCONSTS: printVFPf32ImmOperand(MI, 1); break;
case ARM::LDC2L_OFFSET:
case ARM::LDCL_OFFSET:
case ARM::STC2L_OFFSET:
case ARM::STCL_OFFSET: printAddrMode2Operand(MI, 2); break;
case ARM::LDC2L_OPTION:
case ARM::LDCL_OPTION:
case ARM::STC2L_OPTION:
case ARM::STCL_OPTION: printNoHashImmediate(MI, 3); break;
case ARM::LDC2L_POST:
case ARM::LDCL_POST:
case ARM::STC2L_POST:
case ARM::STCL_POST: printAddrMode2OffsetOperand(MI, 3); break;
case ARM::MOVrx: O << ", rrx"; break;
case ARM::MRS:
case ARM::t2MRS: O << ", cpsr"; break;
case ARM::MRSsys:
case ARM::t2MRSsys: O << ", spsr"; break;
case ARM::PLDWi:
case ARM::PLDi:
case ARM::PLIi: O << ']'; break;
case ARM::RFEW:
case ARM::t2RFEDBW:
case ARM::t2RFEIAW: O << '!'; break;
case ARM::VABSD:
case ARM::VABSS:
case ARM::VABSfd:
case ARM::VABSfd_sfp:
case ARM::VABSfq:
case ARM::VCMPD:
case ARM::VCMPED:
case ARM::VCMPES:
case ARM::VCMPS:
case ARM::VMOVD:
case ARM::VMOVS:
case ARM::VNEGD:
case ARM::VNEGS:
case ARM::VNEGf32q:
case ARM::VNEGfd:
case ARM::VNEGfd_sfp:
case ARM::VRECPEfd:
case ARM::VRECPEfq:
case ARM::VRSQRTEfd:
case ARM::VRSQRTEfq:
case ARM::VSQRTD:
case ARM::VSQRTS:
case ARM::t2CMNzri:
case ARM::t2CMNzrr:
case ARM::t2CMPri:
case ARM::t2CMPrr:
case ARM::t2CMPzri:
case ARM::t2CMPzrr:
case ARM::t2LDRBpci:
case ARM::t2LDRHpci:
case ARM::t2LDRSBpci:
case ARM::t2LDRSHpci:
case ARM::t2LDRpci:
case ARM::t2MVNr:
case ARM::t2REV:
case ARM::t2REV16:
case ARM::t2REVSH:
case ARM::t2SXTBr:
case ARM::t2SXTHr:
case ARM::t2TEQri:
case ARM::t2TEQrr:
case ARM::t2TSTri:
case ARM::t2TSTrr:
case ARM::t2UXTBr:
case ARM::t2UXTHr: printOperand(MI, 1); break;
case ARM::VCEQzv16i8:
case ARM::VCEQzv2i32:
case ARM::VCEQzv4i16:
case ARM::VCEQzv4i32:
case ARM::VCEQzv8i16:
case ARM::VCEQzv8i8:
case ARM::VCGEzv16i8:
case ARM::VCGEzv2i32:
case ARM::VCGEzv4i16:
case ARM::VCGEzv4i32:
case ARM::VCGEzv8i16:
case ARM::VCGEzv8i8:
case ARM::VCGTzv16i8:
case ARM::VCGTzv2i32:
case ARM::VCGTzv4i16:
case ARM::VCGTzv4i32:
case ARM::VCGTzv8i16:
case ARM::VCGTzv8i8:
case ARM::VCLEzv16i8:
case ARM::VCLEzv2i32:
case ARM::VCLEzv4i16:
case ARM::VCLEzv4i32:
case ARM::VCLEzv8i16:
case ARM::VCLEzv8i8:
case ARM::VCLTzv16i8:
case ARM::VCLTzv2i32:
case ARM::VCLTzv4i16:
case ARM::VCLTzv4i32:
case ARM::VCLTzv8i16:
case ARM::VCLTzv8i8: O << ", #0"; break;
case ARM::VCVTf2xsd:
case ARM::VCVTf2xsq:
case ARM::VCVTf2xud:
case ARM::VCVTf2xuq:
case ARM::VCVTxs2fd:
case ARM::VCVTxs2fq:
case ARM::VCVTxu2fd:
case ARM::VCVTxu2fq:
case ARM::VMOVDcc:
case ARM::VMOVScc:
case ARM::VNEGDcc:
case ARM::VNEGScc:
case ARM::VSLTOD:
case ARM::VSLTOS:
case ARM::VTOSLD:
case ARM::VTOSLS:
case ARM::VTOULD:
case ARM::VTOULS:
case ARM::VULTOD:
case ARM::VULTOS:
case ARM::t2MOVCCi:
case ARM::t2MOVCCr: printOperand(MI, 2); break;
case ARM::VMRS: O << ", fpscr"; break;
case ARM::t2CMNzrs:
case ARM::t2CMPrs:
case ARM::t2CMPzrs:
case ARM::t2MVNs:
case ARM::t2TEQrs:
case ARM::t2TSTrs: printT2SOOperand(MI, 1); break;
case ARM::t2LDRBi12:
case ARM::t2LDRHi12:
case ARM::t2LDRSBi12:
case ARM::t2LDRSHi12:
case ARM::t2LDRi12:
case ARM::t2STRBi12:
case ARM::t2STRHi12:
case ARM::t2STRi12: printT2AddrModeImm12Operand(MI, 1); break;
case ARM::t2LDRBs:
case ARM::t2LDRHs:
case ARM::t2LDRSBs:
case ARM::t2LDRSHs:
case ARM::t2LDRs:
case ARM::t2STRBs:
case ARM::t2STRHs:
case ARM::t2STRs: printT2AddrModeSoRegOperand(MI, 1); break;
case ARM::t2MOVsra_flag:
case ARM::t2MOVsrl_flag: O << ", #1"; break;
}
return;
break;
case ARM::LDC2L_PRE:
case ARM::LDCL_PRE:
case ARM::STC2L_PRE:
case ARM::STCL_PRE:
printAddrMode2Operand(MI, 2);
O << '!';
return;
break;
case ARM::LDC2_OPTION:
case ARM::LDC2_POST:
case ARM::LDC_OPTION:
case ARM::LDC_POST:
case ARM::LDRBT:
case ARM::LDRB_POST:
case ARM::LDRHT:
case ARM::LDRH_POST:
case ARM::LDRSBT:
case ARM::LDRSB_POST:
case ARM::LDRSHT:
case ARM::LDRSH_POST:
case ARM::LDRT:
case ARM::LDR_POST:
case ARM::STC2_OPTION:
case ARM::STC2_POST:
case ARM::STC_OPTION:
case ARM::STC_POST:
case ARM::STRBT:
case ARM::STRB_POST:
case ARM::STRHT:
case ARM::STRH_POST:
case ARM::STRT:
case ARM::STR_POST:
case ARM::t2LDRB_POST:
case ARM::t2LDRH_POST:
case ARM::t2LDRSB_POST:
case ARM::t2LDRSH_POST:
case ARM::t2LDR_POST:
case ARM::t2STRB_POST:
case ARM::t2STRH_POST:
case ARM::t2STR_POST:
O << ", [";
printOperand(MI, 2);
O << "], ";
switch (MI->getOpcode()) {
case ARM::LDC2_OPTION:
case ARM::LDC_OPTION:
case ARM::STC2_OPTION:
case ARM::STC_OPTION: printOperand(MI, 3); break;
case ARM::LDC2_POST:
case ARM::LDC_POST:
case ARM::LDRBT:
case ARM::LDRB_POST:
case ARM::LDRSBT:
case ARM::LDRT:
case ARM::LDR_POST:
case ARM::STC2_POST:
case ARM::STC_POST:
case ARM::STRBT:
case ARM::STRB_POST:
case ARM::STRT:
case ARM::STR_POST: printAddrMode2OffsetOperand(MI, 3); break;
case ARM::LDRHT:
case ARM::LDRH_POST:
case ARM::LDRSB_POST:
case ARM::LDRSHT:
case ARM::LDRSH_POST:
case ARM::STRHT:
case ARM::STRH_POST: printAddrMode3OffsetOperand(MI, 3); break;
case ARM::t2LDRB_POST:
case ARM::t2LDRH_POST:
case ARM::t2LDRSB_POST:
case ARM::t2LDRSH_POST:
case ARM::t2LDR_POST:
case ARM::t2STRB_POST:
case ARM::t2STRH_POST:
case ARM::t2STR_POST: printT2AddrModeImm8OffsetOperand(MI, 3); break;
}
return;
break;
case ARM::LDC2_PRE:
case ARM::LDC_PRE:
case ARM::LDRB_PRE:
case ARM::LDRH_PRE:
case ARM::LDRSB_PRE:
case ARM::LDRSH_PRE:
case ARM::LDR_PRE:
case ARM::STC2_PRE:
case ARM::STC_PRE:
case ARM::t2LDRB_PRE:
case ARM::t2LDRH_PRE:
case ARM::t2LDRSB_PRE:
case ARM::t2LDRSH_PRE:
case ARM::t2LDR_PRE:
O << ", ";
switch (MI->getOpcode()) {
case ARM::LDC2_PRE:
case ARM::LDC_PRE:
case ARM::LDRB_PRE:
case ARM::LDR_PRE:
case ARM::STC2_PRE:
case ARM::STC_PRE: printAddrMode2Operand(MI, 2); break;
case ARM::LDRH_PRE:
case ARM::LDRSB_PRE:
case ARM::LDRSH_PRE: printAddrMode3Operand(MI, 2); break;
case ARM::t2LDRB_PRE:
case ARM::t2LDRH_PRE:
case ARM::t2LDRSB_PRE:
case ARM::t2LDRSH_PRE:
case ARM::t2LDR_PRE: printT2AddrModeImm8Operand(MI, 2); break;
}
O << '!';
return;
break;
case ARM::LDM:
case ARM::LDM_RET:
case ARM::STM:
case ARM::tLDM:
case ARM::tSTM:
printAddrMode4Operand(MI, 0);
O << ", ";
printRegisterList(MI, 4);
return;
break;
case ARM::LDRD_POST:
case ARM::STRD_POST:
O << ", ";
switch (MI->getOpcode()) {
case ARM::LDRD_POST: printOperand(MI, 1); break;
case ARM::STRD_POST: printOperand(MI, 2); break;
}
O << ", [";
printOperand(MI, 3);
O << "], ";
printAddrMode3OffsetOperand(MI, 4);
return;
break;
case ARM::LDRD_PRE:
O << ", ";
printOperand(MI, 1);
O << ", ";
printAddrMode3Operand(MI, 3);
O << '!';
return;
break;
case ARM::LDREX:
case ARM::LDREXB:
case ARM::LDREXH:
case ARM::t2LDREX:
case ARM::t2LDREXB:
case ARM::t2LDREXH:
O << ", [";
printOperand(MI, 1);
O << ']';
return;
break;
case ARM::LDREXD:
case ARM::STREX:
case ARM::STREXB:
case ARM::STREXH:
case ARM::SWP:
case ARM::SWPB:
case ARM::t2LDREXD:
case ARM::t2STREX:
case ARM::t2STREXB:
case ARM::t2STREXH:
O << ", ";
printOperand(MI, 1);
O << ", [";
printOperand(MI, 2);
O << ']';
return;
break;
case ARM::MCR:
case ARM::MRC:
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << ", cr";
printNoHashImmediate(MI, 3);
O << ", cr";
printNoHashImmediate(MI, 4);
O << ", ";
printOperand(MI, 5);
return;
break;
case ARM::MCR2:
case ARM::MRC2:
O << ", cr";
printNoHashImmediate(MI, 3);
O << ", cr";
printNoHashImmediate(MI, 4);
O << ", ";
printOperand(MI, 5);
return;
break;
case ARM::MCRR:
case ARM::MRRC:
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << ", cr";
printNoHashImmediate(MI, 4);
return;
break;
case ARM::MCRR2:
case ARM::MRRC2:
O << ", ";
printOperand(MI, 3);
O << ", cr";
printNoHashImmediate(MI, 4);
return;
break;
case ARM::MLA:
case ARM::SMLAL:
case ARM::SMULL:
case ARM::UMLAL:
case ARM::UMULL:
case ARM::VBIFd:
case ARM::VBIFq:
case ARM::VBITd:
case ARM::VBITq:
case ARM::VBSLd:
case ARM::VBSLq:
case ARM::VSLIv16i8:
case ARM::VSLIv1i64:
case ARM::VSLIv2i32:
case ARM::VSLIv2i64:
case ARM::VSLIv4i16:
case ARM::VSLIv4i32:
case ARM::VSLIv8i16:
case ARM::VSLIv8i8:
case ARM::VSRIv16i8:
case ARM::VSRIv1i64:
case ARM::VSRIv2i32:
case ARM::VSRIv2i64:
case ARM::VSRIv4i16:
case ARM::VSRIv4i32:
case ARM::VSRIv8i16:
case ARM::VSRIv8i8:
O << ", ";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
return;
break;
case ARM::MLS:
case ARM::PKHBT:
case ARM::PKHTB:
case ARM::SBFX:
case ARM::SMLABB:
case ARM::SMLABT:
case ARM::SMLAD:
case ARM::SMLADX:
case ARM::SMLALBB:
case ARM::SMLALBT:
case ARM::SMLALD:
case ARM::SMLALDX:
case ARM::SMLALTB:
case ARM::SMLALTT:
case ARM::SMLATB:
case ARM::SMLATT:
case ARM::SMLAWB:
case ARM::SMLAWT:
case ARM::SMLSD:
case ARM::SMLSDX:
case ARM::SMLSLD:
case ARM::SMLSLDX:
case ARM::SMMLA:
case ARM::SMMLAR:
case ARM::SMMLS:
case ARM::SMMLSR:
case ARM::SSATasr:
case ARM::SSATlsl:
case ARM::SXTAB16rr_rot:
case ARM::SXTABrr_rot:
case ARM::SXTAHrr_rot:
case ARM::UBFX:
case ARM::UMAAL:
case ARM::USADA8:
case ARM::USATasr:
case ARM::USATlsl:
case ARM::UXTAB16rr_rot:
case ARM::UXTABrr_rot:
case ARM::UXTAHrr_rot:
case ARM::VEXTd16:
case ARM::VEXTd32:
case ARM::VEXTd8:
case ARM::VEXTdf:
case ARM::VEXTq16:
case ARM::VEXTq32:
case ARM::VEXTq8:
case ARM::VEXTqf:
case ARM::VMOVRRS:
case ARM::VMOVSRR:
case ARM::t2BFI:
case ARM::t2MLA:
case ARM::t2MLS:
case ARM::t2PKHBT:
case ARM::t2PKHTB:
case ARM::t2SBFX:
case ARM::t2SMLABB:
case ARM::t2SMLABT:
case ARM::t2SMLAD:
case ARM::t2SMLADX:
case ARM::t2SMLAL:
case ARM::t2SMLALBB:
case ARM::t2SMLALBT:
case ARM::t2SMLALD:
case ARM::t2SMLALDX:
case ARM::t2SMLALTB:
case ARM::t2SMLALTT:
case ARM::t2SMLATB:
case ARM::t2SMLATT:
case ARM::t2SMLAWB:
case ARM::t2SMLAWT:
case ARM::t2SMLSD:
case ARM::t2SMLSDX:
case ARM::t2SMLSLD:
case ARM::t2SMLSLDX:
case ARM::t2SMMLA:
case ARM::t2SMMLAR:
case ARM::t2SMMLS:
case ARM::t2SMMLSR:
case ARM::t2SMULL:
case ARM::t2SSATasr:
case ARM::t2SSATlsl:
case ARM::t2SXTAB16rr_rot:
case ARM::t2SXTABrr_rot:
case ARM::t2SXTAHrr_rot:
case ARM::t2UBFX:
case ARM::t2UMAAL:
case ARM::t2UMLAL:
case ARM::t2UMULL:
case ARM::t2USADA8:
case ARM::t2USATasr:
case ARM::t2USATlsl:
case ARM::t2UXTAB16rr_rot:
case ARM::t2UXTABrr_rot:
case ARM::t2UXTAHrr_rot:
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
switch (MI->getOpcode()) {
case ARM::MLS:
case ARM::SBFX:
case ARM::SMLABB:
case ARM::SMLABT:
case ARM::SMLAD:
case ARM::SMLADX:
case ARM::SMLALBB:
case ARM::SMLALBT:
case ARM::SMLALD:
case ARM::SMLALDX:
case ARM::SMLALTB:
case ARM::SMLALTT:
case ARM::SMLATB:
case ARM::SMLATT:
case ARM::SMLAWB:
case ARM::SMLAWT:
case ARM::SMLSD:
case ARM::SMLSDX:
case ARM::SMLSLD:
case ARM::SMLSLDX:
case ARM::SMMLA:
case ARM::SMMLAR:
case ARM::SMMLS:
case ARM::SMMLSR:
case ARM::UBFX:
case ARM::UMAAL:
case ARM::USADA8:
case ARM::VEXTd16:
case ARM::VEXTd32:
case ARM::VEXTd8:
case ARM::VEXTdf:
case ARM::VEXTq16:
case ARM::VEXTq32:
case ARM::VEXTq8:
case ARM::VEXTqf:
case ARM::VMOVRRS:
case ARM::VMOVSRR:
case ARM::t2BFI:
case ARM::t2MLA:
case ARM::t2MLS:
case ARM::t2SBFX:
case ARM::t2SMLABB:
case ARM::t2SMLABT:
case ARM::t2SMLAD:
case ARM::t2SMLADX:
case ARM::t2SMLAL:
case ARM::t2SMLALBB:
case ARM::t2SMLALBT:
case ARM::t2SMLALD:
case ARM::t2SMLALDX:
case ARM::t2SMLALTB:
case ARM::t2SMLALTT:
case ARM::t2SMLATB:
case ARM::t2SMLATT:
case ARM::t2SMLAWB:
case ARM::t2SMLAWT:
case ARM::t2SMLSD:
case ARM::t2SMLSDX:
case ARM::t2SMLSLD:
case ARM::t2SMLSLDX:
case ARM::t2SMMLA:
case ARM::t2SMMLAR:
case ARM::t2SMMLS:
case ARM::t2SMMLSR:
case ARM::t2SMULL:
case ARM::t2UBFX:
case ARM::t2UMAAL:
case ARM::t2UMLAL:
case ARM::t2UMULL:
case ARM::t2USADA8: O << ", "; break;
case ARM::PKHBT:
case ARM::SSATlsl:
case ARM::USATlsl:
case ARM::t2PKHBT:
case ARM::t2SSATlsl:
case ARM::t2USATlsl: O << ", lsl "; break;
case ARM::PKHTB:
case ARM::SSATasr:
case ARM::USATasr:
case ARM::t2PKHTB:
case ARM::t2SSATasr:
case ARM::t2USATasr: O << ", asr "; break;
case ARM::SXTAB16rr_rot:
case ARM::SXTABrr_rot:
case ARM::SXTAHrr_rot:
case ARM::UXTAB16rr_rot:
case ARM::UXTABrr_rot:
case ARM::UXTAHrr_rot:
case ARM::t2SXTAB16rr_rot:
case ARM::t2SXTABrr_rot:
case ARM::t2SXTAHrr_rot:
case ARM::t2UXTAB16rr_rot:
case ARM::t2UXTABrr_rot:
case ARM::t2UXTAHrr_rot: O << ", ror "; break;
}
printOperand(MI, 3);
return;
break;
case ARM::MOVi32imm:
case ARM::t2MOVi32imm:
O << ", ";
printOperand(MI, 1, "lo16");
O << "\n\tmovt";
printPredicateOperand(MI, 2);
O << "\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1, "hi16");
return;
break;
case ARM::MOVsra_flag:
case ARM::MOVsrl_flag:
O << ", ";
printOperand(MI, 1);
switch (MI->getOpcode()) {
case ARM::MOVsra_flag: O << ", asr #1"; break;
case ARM::MOVsrl_flag: O << ", lsr #1"; break;
}
return;
break;
case ARM::STRB_PRE:
case ARM::STRH_PRE:
case ARM::STR_PRE:
case ARM::t2STRB_PRE:
case ARM::t2STRH_PRE:
case ARM::t2STR_PRE:
O << ", [";
printOperand(MI, 2);
O << ", ";
switch (MI->getOpcode()) {
case ARM::STRB_PRE:
case ARM::STR_PRE: printAddrMode2OffsetOperand(MI, 3); break;
case ARM::STRH_PRE: printAddrMode3OffsetOperand(MI, 3); break;
case ARM::t2STRB_PRE:
case ARM::t2STRH_PRE:
case ARM::t2STR_PRE: printT2AddrModeImm8OffsetOperand(MI, 3); break;
}
O << "]!";
return;
break;
case ARM::STRD_PRE:
O << ", ";
printOperand(MI, 2);
O << ", [";
printOperand(MI, 3);
O << ", ";
printAddrMode3OffsetOperand(MI, 4);
O << "]!";
return;
break;
case ARM::STREXD:
case ARM::t2STREXD:
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << ", [";
printOperand(MI, 3);
O << ']';
return;
break;
case ARM::SXTB16r_rot:
case ARM::SXTBr_rot:
case ARM::SXTHr_rot:
case ARM::UXTB16r_rot:
case ARM::UXTBr_rot:
case ARM::UXTHr_rot:
case ARM::t2SXTB16r_rot:
case ARM::t2UXTB16r_rot:
O << ", ";
printOperand(MI, 1);
O << ", ror ";
printOperand(MI, 2);
return;
break;
case ARM::VABDfd:
case ARM::VABDfq:
case ARM::VACGEd:
case ARM::VACGEq:
case ARM::VACGTd:
case ARM::VACGTq:
case ARM::VADDD:
case ARM::VADDS:
case ARM::VADDfd:
case ARM::VADDfd_sfp:
case ARM::VADDfq:
case ARM::VCEQfd:
case ARM::VCEQfq:
case ARM::VCGEfd:
case ARM::VCGEfq:
case ARM::VCGTfd:
case ARM::VCGTfq:
case ARM::VDIVD:
case ARM::VDIVS:
case ARM::VMAXfd:
case ARM::VMAXfd_sfp:
case ARM::VMAXfq:
case ARM::VMINfd:
case ARM::VMINfd_sfp:
case ARM::VMINfq:
case ARM::VMULD:
case ARM::VMULS:
case ARM::VMULfd:
case ARM::VMULfd_sfp:
case ARM::VMULfq:
case ARM::VNMULD:
case ARM::VNMULS:
case ARM::VPADDf:
case ARM::VPMAXf:
case ARM::VPMINf:
case ARM::VRECPSfd:
case ARM::VRECPSfq:
case ARM::VRSQRTSfd:
case ARM::VRSQRTSfq:
case ARM::VSUBD:
case ARM::VSUBS:
case ARM::VSUBfd:
case ARM::VSUBfd_sfp:
case ARM::VSUBfq:
case ARM::t2ADCSrr:
case ARM::t2ADCSrs:
case ARM::t2ADCrr:
case ARM::t2ADCrs:
case ARM::t2ADDSri:
case ARM::t2ADDSrr:
case ARM::t2ADDSrs:
case ARM::t2ADDrSPi:
case ARM::t2ADDrSPs:
case ARM::t2ADDri:
case ARM::t2ADDrr:
case ARM::t2ADDrs:
case ARM::t2ANDrr:
case ARM::t2ANDrs:
case ARM::t2ASRri:
case ARM::t2ASRrr:
case ARM::t2BICrr:
case ARM::t2BICrs:
case ARM::t2EORrr:
case ARM::t2EORrs:
case ARM::t2LSLri:
case ARM::t2LSLrr:
case ARM::t2LSRri:
case ARM::t2LSRrr:
case ARM::t2ORRrr:
case ARM::t2ORRrs:
case ARM::t2RORri:
case ARM::t2RORrr:
case ARM::t2RSBri:
case ARM::t2SBCSrr:
case ARM::t2SBCSrs:
case ARM::t2SBCrr:
case ARM::t2SBCrs:
case ARM::t2SUBSri:
case ARM::t2SUBSrr:
case ARM::t2SUBSrs:
case ARM::t2SUBrSPi:
case ARM::t2SUBri:
case ARM::t2SUBrr:
case ARM::t2SUBrs:
printOperand(MI, 1);
O << ", ";
switch (MI->getOpcode()) {
case ARM::VABDfd:
case ARM::VABDfq:
case ARM::VACGEd:
case ARM::VACGEq:
case ARM::VACGTd:
case ARM::VACGTq:
case ARM::VADDD:
case ARM::VADDS:
case ARM::VADDfd:
case ARM::VADDfd_sfp:
case ARM::VADDfq:
case ARM::VCEQfd:
case ARM::VCEQfq:
case ARM::VCGEfd:
case ARM::VCGEfq:
case ARM::VCGTfd:
case ARM::VCGTfq:
case ARM::VDIVD:
case ARM::VDIVS:
case ARM::VMAXfd:
case ARM::VMAXfd_sfp:
case ARM::VMAXfq:
case ARM::VMINfd:
case ARM::VMINfd_sfp:
case ARM::VMINfq:
case ARM::VMULD:
case ARM::VMULS:
case ARM::VMULfd:
case ARM::VMULfd_sfp:
case ARM::VMULfq:
case ARM::VNMULD:
case ARM::VNMULS:
case ARM::VPADDf:
case ARM::VPMAXf:
case ARM::VPMINf:
case ARM::VRECPSfd:
case ARM::VRECPSfq:
case ARM::VRSQRTSfd:
case ARM::VRSQRTSfq:
case ARM::VSUBD:
case ARM::VSUBS:
case ARM::VSUBfd:
case ARM::VSUBfd_sfp:
case ARM::VSUBfq:
case ARM::t2ADCSrr:
case ARM::t2ADCrr:
case ARM::t2ADDSri:
case ARM::t2ADDSrr:
case ARM::t2ADDrSPi:
case ARM::t2ADDri:
case ARM::t2ADDrr:
case ARM::t2ANDrr:
case ARM::t2ASRri:
case ARM::t2ASRrr:
case ARM::t2BICrr:
case ARM::t2EORrr:
case ARM::t2LSLri:
case ARM::t2LSLrr:
case ARM::t2LSRri:
case ARM::t2LSRrr:
case ARM::t2ORRrr:
case ARM::t2RORri:
case ARM::t2RORrr:
case ARM::t2RSBri:
case ARM::t2SBCSrr:
case ARM::t2SBCrr:
case ARM::t2SUBSri:
case ARM::t2SUBSrr:
case ARM::t2SUBrSPi:
case ARM::t2SUBri:
case ARM::t2SUBrr: printOperand(MI, 2); break;
case ARM::t2ADCSrs:
case ARM::t2ADCrs:
case ARM::t2ADDSrs:
case ARM::t2ADDrSPs:
case ARM::t2ADDrs:
case ARM::t2ANDrs:
case ARM::t2BICrs:
case ARM::t2EORrs:
case ARM::t2ORRrs:
case ARM::t2SBCSrs:
case ARM::t2SBCrs:
case ARM::t2SUBSrs:
case ARM::t2SUBrs: printT2SOOperand(MI, 2); break;
}
return;
break;
case ARM::VCEQzv2f32:
case ARM::VCEQzv4f32:
case ARM::VCGEzv2f32:
case ARM::VCGEzv4f32:
case ARM::VCGTzv2f32:
case ARM::VCGTzv4f32:
case ARM::VCLEzv2f32:
case ARM::VCLEzv4f32:
case ARM::VCLTzv2f32:
case ARM::VCLTzv4f32:
printOperand(MI, 1);
O << ", #0";
return;
break;
case ARM::VDUPLN16d:
case ARM::VDUPLN16q:
case ARM::VDUPLN32d:
case ARM::VDUPLN32q:
case ARM::VDUPLN8d:
case ARM::VDUPLN8q:
case ARM::VDUPLNfd:
case ARM::VDUPLNfq:
case ARM::VGETLNi32:
O << ", ";
printOperand(MI, 1);
O << '[';
printNoHashImmediate(MI, 2);
O << ']';
return;
break;
case ARM::VGETLNs16:
case ARM::VGETLNs8:
case ARM::VGETLNu16:
case ARM::VGETLNu8:
O << '[';
printNoHashImmediate(MI, 2);
O << ']';
return;
break;
case ARM::VLD1d16:
case ARM::VLD1d32:
case ARM::VLD1d64:
case ARM::VLD1d8:
case ARM::VLD1df:
case ARM::VST1d16:
case ARM::VST1d32:
case ARM::VST1d64:
case ARM::VST1d8:
case ARM::VST1df:
case ARM::VST3q16a:
case ARM::VST3q16b:
case ARM::VST3q32a:
case ARM::VST3q32b:
case ARM::VST3q8a:
case ARM::VST3q8b:
O << "}, ";
switch (MI->getOpcode()) {
case ARM::VLD1d16:
case ARM::VLD1d32:
case ARM::VLD1d64:
case ARM::VLD1d8:
case ARM::VLD1df:
case ARM::VST3q16a:
case ARM::VST3q16b:
case ARM::VST3q32a:
case ARM::VST3q32b:
case ARM::VST3q8a:
case ARM::VST3q8b: printAddrMode6Operand(MI, 1); break;
case ARM::VST1d16:
case ARM::VST1d32:
case ARM::VST1d64:
case ARM::VST1d8:
case ARM::VST1df: printAddrMode6Operand(MI, 0); break;
}
return;
break;
case ARM::VLD1d16Q:
case ARM::VLD1d32Q:
case ARM::VLD1d8Q:
case ARM::VLD2q16:
case ARM::VLD2q32:
case ARM::VLD2q8:
case ARM::VLD4d16:
case ARM::VLD4d32:
case ARM::VLD4d64:
case ARM::VLD4d8:
case ARM::VLD4q16a:
case ARM::VLD4q16b:
case ARM::VLD4q32a:
case ARM::VLD4q32b:
case ARM::VLD4q8a:
case ARM::VLD4q8b:
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << "}, ";
switch (MI->getOpcode()) {
case ARM::VLD1d16Q:
case ARM::VLD1d32Q:
case ARM::VLD1d8Q:
case ARM::VLD2q16:
case ARM::VLD2q32:
case ARM::VLD2q8:
case ARM::VLD4d16:
case ARM::VLD4d32:
case ARM::VLD4d64:
case ARM::VLD4d8: printAddrMode6Operand(MI, 4); break;
case ARM::VLD4q16a:
case ARM::VLD4q16b:
case ARM::VLD4q32a:
case ARM::VLD4q32b:
case ARM::VLD4q8a:
case ARM::VLD4q8b: printAddrMode6Operand(MI, 5); break;
}
return;
break;
case ARM::VLD1d16T:
case ARM::VLD1d32T:
case ARM::VLD1d8T:
case ARM::VLD3d16:
case ARM::VLD3d32:
case ARM::VLD3d64:
case ARM::VLD3d8:
case ARM::VLD3q16a:
case ARM::VLD3q16b:
case ARM::VLD3q32a:
case ARM::VLD3q32b:
case ARM::VLD3q8a:
case ARM::VLD3q8b:
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << "}, ";
switch (MI->getOpcode()) {
case ARM::VLD1d16T:
case ARM::VLD1d32T:
case ARM::VLD1d8T:
case ARM::VLD3d16:
case ARM::VLD3d32:
case ARM::VLD3d64:
case ARM::VLD3d8: printAddrMode6Operand(MI, 3); break;
case ARM::VLD3q16a:
case ARM::VLD3q16b:
case ARM::VLD3q32a:
case ARM::VLD3q32b:
case ARM::VLD3q8a:
case ARM::VLD3q8b: printAddrMode6Operand(MI, 4); break;
}
return;
break;
case ARM::VLD2LNd16:
case ARM::VLD2LNd32:
case ARM::VLD2LNd8:
case ARM::VLD2LNq16a:
case ARM::VLD2LNq16b:
case ARM::VLD2LNq32a:
case ARM::VLD2LNq32b:
O << '[';
printNoHashImmediate(MI, 8);
O << "], ";
printOperand(MI, 1);
O << '[';
printNoHashImmediate(MI, 8);
O << "]}, ";
printAddrMode6Operand(MI, 2);
return;
break;
case ARM::VLD2d16:
case ARM::VLD2d16D:
case ARM::VLD2d32:
case ARM::VLD2d32D:
case ARM::VLD2d64:
case ARM::VLD2d8:
case ARM::VLD2d8D:
O << ", ";
printOperand(MI, 1);
O << "}, ";
printAddrMode6Operand(MI, 2);
return;
break;
case ARM::VLD3LNd16:
case ARM::VLD3LNd32:
case ARM::VLD3LNd8:
case ARM::VLD3LNq16a:
case ARM::VLD3LNq16b:
case ARM::VLD3LNq32a:
case ARM::VLD3LNq32b:
O << '[';
printNoHashImmediate(MI, 10);
O << "], ";
printOperand(MI, 1);
O << '[';
printNoHashImmediate(MI, 10);
O << "], ";
printOperand(MI, 2);
O << '[';
printNoHashImmediate(MI, 10);
O << "]}, ";
printAddrMode6Operand(MI, 3);
return;
break;
case ARM::VLD4LNd16:
case ARM::VLD4LNd32:
case ARM::VLD4LNd8:
case ARM::VLD4LNq16a:
case ARM::VLD4LNq16b:
case ARM::VLD4LNq32a:
case ARM::VLD4LNq32b:
O << '[';
printNoHashImmediate(MI, 12);
O << "], ";
printOperand(MI, 1);
O << '[';
printNoHashImmediate(MI, 12);
O << "], ";
printOperand(MI, 2);
O << '[';
printNoHashImmediate(MI, 12);
O << "], ";
printOperand(MI, 3);
O << '[';
printNoHashImmediate(MI, 12);
O << "]}, ";
printAddrMode6Operand(MI, 4);
return;
break;
case ARM::VMLAD:
case ARM::VMLAS:
case ARM::VMLAfd:
case ARM::VMLAfq:
case ARM::VMLSD:
case ARM::VMLSS:
case ARM::VMLSfd:
case ARM::VMLSfq:
case ARM::VNMLAD:
case ARM::VNMLAS:
case ARM::VNMLSD:
case ARM::VNMLSS:
case ARM::t2MOVCCasr:
case ARM::t2MOVCClsl:
case ARM::t2MOVCClsr:
case ARM::t2MOVCCror:
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
return;
break;
case ARM::VMLALslsv2i32:
case ARM::VMLALslsv4i16:
case ARM::VMLALsluv2i32:
case ARM::VMLALsluv4i16:
case ARM::VMLAslv2i32:
case ARM::VMLAslv4i16:
case ARM::VMLAslv4i32:
case ARM::VMLAslv8i16:
case ARM::VMLSLslsv2i32:
case ARM::VMLSLslsv4i16:
case ARM::VMLSLsluv2i32:
case ARM::VMLSLsluv4i16:
case ARM::VMLSslv2i32:
case ARM::VMLSslv4i16:
case ARM::VMLSslv4i32:
case ARM::VMLSslv8i16:
case ARM::VQDMLALslv2i32:
case ARM::VQDMLALslv4i16:
case ARM::VQDMLSLslv2i32:
case ARM::VQDMLSLslv4i16:
O << ", ";
printOperand(MI, 3);
O << '[';
printNoHashImmediate(MI, 4);
O << ']';
return;
break;
case ARM::VMLAslfd:
case ARM::VMLAslfq:
case ARM::VMLSslfd:
case ARM::VMLSslfq:
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << '[';
printNoHashImmediate(MI, 4);
O << ']';
return;
break;
case ARM::VMULLslsv2i32:
case ARM::VMULLslsv4i16:
case ARM::VMULLsluv2i32:
case ARM::VMULLsluv4i16:
case ARM::VMULslv2i32:
case ARM::VMULslv4i16:
case ARM::VMULslv4i32:
case ARM::VMULslv8i16:
case ARM::VQDMULHslv2i32:
case ARM::VQDMULHslv4i16:
case ARM::VQDMULHslv4i32:
case ARM::VQDMULHslv8i16:
case ARM::VQDMULLslv2i32:
case ARM::VQDMULLslv4i16:
case ARM::VQRDMULHslv2i32:
case ARM::VQRDMULHslv4i16:
case ARM::VQRDMULHslv4i32:
case ARM::VQRDMULHslv8i16:
O << ", ";
printOperand(MI, 2);
O << '[';
printNoHashImmediate(MI, 3);
O << ']';
return;
break;
case ARM::VMULslfd:
case ARM::VMULslfq:
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << '[';
printNoHashImmediate(MI, 3);
O << ']';
return;
break;
case ARM::VSETLNi16:
case ARM::VSETLNi32:
case ARM::VSETLNi8:
O << '[';
printNoHashImmediate(MI, 3);
O << "], ";
printOperand(MI, 2);
return;
break;
case ARM::VST1d16Q:
case ARM::VST1d32Q:
case ARM::VST1d8Q:
case ARM::VST2q16:
case ARM::VST2q32:
case ARM::VST2q8:
case ARM::VST4d16:
case ARM::VST4d32:
case ARM::VST4d64:
case ARM::VST4d8:
O << ", ";
printOperand(MI, 5);
O << ", ";
printOperand(MI, 6);
O << ", ";
printOperand(MI, 7);
O << "}, ";
printAddrMode6Operand(MI, 0);
return;
break;
case ARM::VST1d16T:
case ARM::VST1d32T:
case ARM::VST1d8T:
case ARM::VST3d16:
case ARM::VST3d32:
case ARM::VST3d64:
case ARM::VST3d8:
O << ", ";
printOperand(MI, 5);
O << ", ";
printOperand(MI, 6);
O << "}, ";
printAddrMode6Operand(MI, 0);
return;
break;
case ARM::VST2LNd16:
case ARM::VST2LNd32:
case ARM::VST2LNd8:
case ARM::VST2LNq16a:
case ARM::VST2LNq16b:
case ARM::VST2LNq32a:
case ARM::VST2LNq32b:
O << '[';
printNoHashImmediate(MI, 6);
O << "], ";
printOperand(MI, 5);
O << '[';
printNoHashImmediate(MI, 6);
O << "]}, ";
printAddrMode6Operand(MI, 0);
return;
break;
case ARM::VST2d16:
case ARM::VST2d16D:
case ARM::VST2d32:
case ARM::VST2d32D:
case ARM::VST2d64:
case ARM::VST2d8:
case ARM::VST2d8D:
O << ", ";
printOperand(MI, 5);
O << "}, ";
printAddrMode6Operand(MI, 0);
return;
break;
case ARM::VST3LNd16:
case ARM::VST3LNd32:
case ARM::VST3LNd8:
case ARM::VST3LNq16a:
case ARM::VST3LNq16b:
case ARM::VST3LNq32a:
case ARM::VST3LNq32b:
O << '[';
printNoHashImmediate(MI, 7);
O << "], ";
printOperand(MI, 5);
O << '[';
printNoHashImmediate(MI, 7);
O << "], ";
printOperand(MI, 6);
O << '[';
printNoHashImmediate(MI, 7);
O << "]}, ";
printAddrMode6Operand(MI, 0);
return;
break;
case ARM::VST4LNd16:
case ARM::VST4LNd32:
case ARM::VST4LNd8:
case ARM::VST4LNq16a:
case ARM::VST4LNq16b:
case ARM::VST4LNq32a:
case ARM::VST4LNq32b:
O << '[';
printNoHashImmediate(MI, 8);
O << "], ";
printOperand(MI, 5);
O << '[';
printNoHashImmediate(MI, 8);
O << "], ";
printOperand(MI, 6);
O << '[';
printNoHashImmediate(MI, 8);
O << "], ";
printOperand(MI, 7);
O << '[';
printNoHashImmediate(MI, 8);
O << "]}, ";
printAddrMode6Operand(MI, 0);
return;
break;
case ARM::VST4q16a:
case ARM::VST4q16b:
case ARM::VST4q32a:
case ARM::VST4q32b:
case ARM::VST4q8a:
case ARM::VST4q8b:
O << ", ";
printOperand(MI, 8);
O << "}, ";
printAddrMode6Operand(MI, 1);
return;
break;
case ARM::VTBL1:
O << ", {";
printOperand(MI, 1);
O << "}, ";
printOperand(MI, 2);
return;
break;
case ARM::VTBL2:
O << ", {";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << "}, ";
printOperand(MI, 3);
return;
break;
case ARM::VTBL3:
O << ", {";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << "}, ";
printOperand(MI, 4);
return;
break;
case ARM::VTBL4:
O << ", {";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << ", ";
printOperand(MI, 4);
O << "}, ";
printOperand(MI, 5);
return;
break;
case ARM::VTBX1:
O << ", {";
printOperand(MI, 2);
O << "}, ";
printOperand(MI, 3);
return;
break;
case ARM::VTBX2:
O << ", {";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << "}, ";
printOperand(MI, 4);
return;
break;
case ARM::VTBX3:
O << ", {";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << ", ";
printOperand(MI, 4);
O << "}, ";
printOperand(MI, 5);
return;
break;
case ARM::VTBX4:
O << ", {";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << ", ";
printOperand(MI, 4);
O << ", ";
printOperand(MI, 5);
O << "}, ";
printOperand(MI, 6);
return;
break;
case ARM::t2LDRpci_pic:
case ARM::tLDRpci_pic:
O << "\n";
printPCLabel(MI, 2);
O << ":\n\tadd\t";
printOperand(MI, 0);
O << ", pc";
return;
break;
case ARM::t2LEApcrelJT:
O << '_';
printNoHashImmediate(MI, 2);
return;
break;
case ARM::t2MOVrx:
case ARM::t2MVNi:
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
return;
break;
case ARM::t2SXTBr_rot:
case ARM::t2SXTHr_rot:
case ARM::t2UXTBr_rot:
case ARM::t2UXTHr_rot:
printOperand(MI, 1);
O << ", ror ";
printOperand(MI, 2);
return;
break;
case ARM::tLEApcrel:
O << ", #";
printOperand(MI, 1);
return;
break;
case ARM::tLEApcrelJT:
O << ", #";
printOperand(MI, 1);
O << '_';
printNoHashImmediate(MI, 2);
return;
break;
}
return;
}
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
const char *ARMAsmPrinter::getRegisterName(unsigned RegNo) {
assert(RegNo && RegNo < 100 && "Invalid register number!");
static const unsigned RegAsmOffset[] = {
0, 5, 8, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51,
54, 58, 62, 66, 70, 74, 78, 82, 86, 90, 94, 97, 101, 105,
108, 111, 114, 117, 120, 123, 129, 132, 135, 138, 141, 145, 149, 153,
157, 161, 165, 168, 171, 174, 177, 180, 183, 186, 189, 192, 195, 199,
203, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237, 241, 245,
249, 253, 257, 261, 265, 269, 273, 277, 280, 284, 288, 292, 296, 300,
304, 308, 312, 316, 320, 323, 327, 331, 334, 337, 340, 343, 346, 349,
358, 0
};
const char *AsmStrs =
"cpsr\000d0\000d1\000d10\000d11\000d12\000d13\000d14\000d15\000d16\000d1"
"7\000d18\000d19\000d2\000d20\000d21\000d22\000d23\000d24\000d25\000d26\000"
"d27\000d28\000d29\000d3\000d30\000d31\000d4\000d5\000d6\000d7\000d8\000"
"d9\000fpscr\000lr\000pc\000q0\000q1\000q10\000q11\000q12\000q13\000q14\000"
"q15\000q2\000q3\000q4\000q5\000q6\000q7\000q8\000q9\000r0\000r1\000r10\000"
"r11\000r12\000r2\000r3\000r4\000r5\000r6\000r7\000r8\000r9\000s0\000s1\000"
"s10\000s11\000s12\000s13\000s14\000s15\000s16\000s17\000s18\000s19\000s"
"2\000s20\000s21\000s22\000s23\000s24\000s25\000s26\000s27\000s28\000s29"
"\000s3\000s30\000s31\000s4\000s5\000s6\000s7\000s8\000s9\000sINVALID\000"
"sp\000";
return AsmStrs+RegAsmOffset[RegNo-1];
}
#ifdef GET_INSTRUCTION_NAME
#undef GET_INSTRUCTION_NAME
/// getInstructionName: This method is automatically generated by tblgen
/// from the instruction set description. This returns the enum name of the
/// specified instruction.
const char *ARMAsmPrinter::getInstructionName(unsigned Opcode) {
assert(Opcode < 1949 && "Invalid instruction number!");
static const unsigned InstAsmOffset[] = {
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 138,
146, 154, 160, 166, 172, 179, 186, 193, 199, 205, 211, 228, 243, 249,
255, 261, 281, 301, 320, 340, 360, 379, 399, 419, 438, 459, 480, 500,
519, 538, 556, 576, 596, 615, 635, 655, 674, 690, 706, 721, 723, 727,
731, 737, 743, 749, 754, 757, 761, 767, 775, 780, 790, 799, 810, 816,
825, 832, 839, 842, 846, 853, 858, 862, 866, 871, 877, 881, 888, 895,
902, 908, 914, 920, 927, 934, 941, 957, 961, 965, 972, 981, 988, 997,
1004, 1013, 1019, 1026, 1035, 1042, 1051, 1058, 1067, 1073, 1079, 1085, 1091, 1099,
1107, 1114, 1120, 1137, 1154, 1172, 1190, 1209, 1222, 1235, 1246, 1256, 1268, 1280,
1290, 1299, 1311, 1323, 1333, 1342, 1353, 1364, 1373, 1381, 1385, 1393, 1397, 1402,
1408, 1418, 1427, 1432, 1442, 1451, 1457, 1464, 1471, 1478, 1483, 1489, 1499, 1508,
1514, 1521, 1532, 1542, 1548, 1555, 1566, 1576, 1581, 1590, 1598, 1604, 1613, 1624,
1628, 1633, 1638, 1644, 1648, 1652, 1659, 1666, 1673, 1681, 1689, 1697, 1702, 1709,
1721, 1731, 1736, 1742, 1747, 1759, 1771, 1775, 1780, 1785, 1791, 1795, 1802, 1806,
1811, 1818, 1826, 1830, 1835, 1840, 1845, 1849, 1855, 1861, 1867, 1874, 1881, 1889,
1897, 1906, 1915, 1922, 1930, 1938, 1944, 1950, 1956, 1962, 1967, 1972, 1977, 1982,
1987, 1994, 2000, 2005, 2011, 2017, 2022, 2027, 2034, 2040, 2045, 2049, 2055, 2061,
2065, 2070, 2077, 2084, 2090, 2096, 2103, 2110, 2116, 2122, 2129, 2135, 2140, 2148,
2156, 2164, 2170, 2176, 2182, 2187, 2191, 2200, 2209, 2213, 2221, 2228, 2234, 2240,
2248, 2255, 2259, 2266, 2273, 2279, 2286, 2292, 2300, 2308, 2315, 2323, 2331, 2339,
2346, 2353, 2360, 2367, 2373, 2380, 2387, 2395, 2401, 2408, 2414, 2421, 2427, 2434,
2440, 2447, 2454, 2461, 2467, 2474, 2481, 2488, 2495, 2501, 2508, 2512, 2517, 2524,
2532, 2540, 2545, 2552, 2558, 2571, 2584, 2595, 2605, 2617, 2629, 2639, 2648, 2660,
2672, 2682, 2691, 2702, 2713, 2722, 2730, 2734, 2738, 2743, 2749, 2759, 2768, 2773,
2783, 2792, 2798, 2805, 2812, 2819, 2824, 2830, 2840, 2849, 2854, 2863, 2871, 2878,
2885, 2892, 2898, 2904, 2910, 2914, 2918, 2923, 2933, 2947, 2955, 2967, 2975, 2987,
2995, 3007, 3013, 3023, 3029, 3039, 3045, 3051, 3057, 3064, 3069, 3075, 3081, 3087,
3094, 3100, 3105, 3110, 3118, 3125, 3131, 3137, 3145, 3152, 3158, 3164, 3170, 3178,
3185, 3191, 3197, 3205, 3212, 3218, 3225, 3232, 3240, 3248, 3253, 3260, 3266, 3276,
3290, 3298, 3310, 3318, 3330, 3338, 3350, 3356, 3366, 3372, 3382, 3394, 3406, 3418,
3430, 3442, 3454, 3465, 3476, 3487, 3498, 3509, 3519, 3530, 3541, 3552, 3563, 3574,
3584, 3596, 3608, 3620, 3632, 3644, 3656, 3663, 3670, 3681, 3692, 3703, 3714, 3725,
3735, 3746, 3757, 3768, 3779, 3790, 3800, 3806, 3812, 3819, 3830, 3837, 3847, 3857,
3867, 3877, 3887, 3896, 3903, 3910, 3917, 3924, 3930, 3942, 3954, 3965, 3977, 3989,
4001, 4013, 4025, 4037, 4043, 4055, 4067, 4079, 4091, 4103, 4115, 4122, 4133, 4140,
4150, 4160, 4170, 4180, 4190, 4200, 4210, 4219, 4225, 4231, 4237, 4243, 4249, 4255,
4261, 4267, 4273, 4279, 4286, 4293, 4303, 4313, 4323, 4333, 4343, 4352, 4363, 4374,
4385, 4396, 4407, 4418, 4429, 4439, 4446, 4453, 4464, 4475, 4486, 4497, 4508, 4518,
4529, 4540, 4551, 4562, 4573, 4583, 4594, 4605, 4616, 4627, 4638, 4649, 4660, 4670,
4677, 4684, 4695, 4706, 4717, 4728, 4739, 4749, 4760, 4771, 4782, 4793, 4804, 4814,
4825, 4836, 4847, 4858, 4869, 4880, 4891, 4901, 4912, 4923, 4934, 4945, 4956, 4967,
4978, 4988, 4998, 5008, 5018, 5028, 5038, 5047, 5058, 5069, 5080, 5091, 5102, 5113,
5124, 5134, 5144, 5154, 5164, 5174, 5184, 5193, 5199, 5206, 5213, 5221, 5229, 5235,
5242, 5249, 5255, 5261, 5269, 5277, 5284, 5291, 5299, 5307, 5316, 5329, 5338, 5347,
5360, 5369, 5379, 5389, 5399, 5409, 5418, 5431, 5440, 5449, 5462, 5471, 5481, 5491,
5501, 5511, 5517, 5523, 5531, 5539, 5547, 5555, 5562, 5569, 5579, 5589, 5599, 5609,
5618, 5627, 5636, 5645, 5652, 5660, 5667, 5675, 5681, 5687, 5695, 5703, 5710, 5717,
5725, 5733, 5740, 5747, 5757, 5767, 5776, 5786, 5795, 5807, 5819, 5831, 5843, 5855,
5866, 5878, 5890, 5902, 5914, 5926, 5937, 5949, 5961, 5973, 5985, 5997, 6008, 6020,
6032, 6044, 6056, 6068, 6079, 6087, 6096, 6105, 6113, 6122, 6131, 6139, 6146, 6154,
6162, 6169, 6177, 6185, 6193, 6200, 6207, 6217, 6227, 6236, 6247, 6258, 6269, 6280,
6288, 6297, 6305, 6314, 6322, 6329, 6337, 6345, 6353, 6360, 6370, 6380, 6389, 6400,
6411, 6422, 6433, 6441, 6449, 6457, 6464, 6473, 6482, 6491, 6500, 6508, 6516, 6526,
6536, 6545, 6556, 6567, 6578, 6589, 6597, 6605, 6613, 6620, 6629, 6638, 6647, 6656,
6664, 6672, 6678, 6684, 6690, 6696, 6702, 6709, 6720, 6727, 6738, 6749, 6760, 6771,
6782, 6792, 6803, 6814, 6825, 6836, 6847, 6857, 6864, 6875, 6882, 6893, 6904, 6915,
6926, 6937, 6947, 6958, 6969, 6980, 6991, 7002, 7012, 7018, 7032, 7046, 7060, 7074,
7086, 7098, 7110, 7122, 7134, 7146, 7152, 7159, 7166, 7175, 7184, 7196, 7208, 7220,
7232, 7242, 7252, 7262, 7272, 7282, 7291, 7297, 7311, 7325, 7339, 7353, 7365, 7377,
7389, 7401, 7413, 7425, 7431, 7438, 7445, 7454, 7463, 7475, 7487, 7499, 7511, 7521,
7531, 7541, 7551, 7561, 7570, 7576, 7584, 7592, 7602, 7614, 7626, 7638, 7650, 7662,
7674, 7685, 7696, 7706, 7712, 7720, 7728, 7735, 7741, 7748, 7756, 7764, 7774, 7784,
7794, 7804, 7814, 7824, 7834, 7843, 7848, 7853, 7859, 7866, 7880, 7894, 7908, 7922,
7934, 7946, 7958, 7970, 7982, 7994, 8000, 8007, 8018, 8025, 8032, 8039, 8048, 8057,
8069, 8081, 8093, 8105, 8115, 8125, 8135, 8145, 8155, 8164, 8170, 8176, 8182, 8190,
8196, 8204, 8213, 8220, 8231, 8240, 8249, 8258, 8267, 8275, 8283, 8290, 8297, 8304,
8311, 8318, 8325, 8331, 8337, 8343, 8349, 8362, 8375, 8388, 8401, 8414, 8426, 8439,
8452, 8465, 8478, 8491, 8503, 8516, 8529, 8542, 8555, 8568, 8580, 8593, 8606, 8619,
8632, 8645, 8657, 8664, 8673, 8682, 8690, 8697, 8706, 8715, 8723, 8732, 8741, 8749,
8756, 8765, 8774, 8782, 8791, 8800, 8808, 8819, 8830, 8841, 8852, 8863, 8873, 8885,
8897, 8909, 8921, 8933, 8945, 8957, 8968, 8980, 8992, 9004, 9016, 9028, 9040, 9052,
9063, 9078, 9093, 9106, 9119, 9134, 9149, 9162, 9175, 9190, 9205, 9220, 9235, 9248,
9261, 9274, 9287, 9302, 9317, 9330, 9343, 9357, 9371, 9384, 9397, 9410, 9422, 9435,
9448, 9460, 9471, 9482, 9493, 9504, 9515, 9525, 9541, 9557, 9573, 9589, 9603, 9617,
9631, 9645, 9658, 9671, 9684, 9697, 9710, 9723, 9736, 9748, 9761, 9774, 9787, 9800,
9813, 9826, 9839, 9851, 9865, 9879, 9892, 9906, 9920, 9933, 9947, 9961, 9974, 9987,
10000, 10013, 10026, 10039, 10052, 10065, 10077, 10090, 10103, 10116, 10129, 10142, 10155, 10168,
10180, 10192, 10204, 10216, 10228, 10240, 10252, 10264, 10275, 10288, 10301, 10314, 10327, 10340,
10353, 10366, 10378, 10390, 10402, 10414, 10426, 10438, 10450, 10462, 10473, 10486, 10499, 10511,
10524, 10537, 10549, 10562, 10575, 10587, 10599, 10611, 10623, 10635, 10647, 10659, 10671, 10682,
10694, 10706, 10718, 10730, 10742, 10754, 10766, 10777, 10790, 10803, 10815, 10823, 10832, 10841,
10849, 10858, 10867, 10876, 10885, 10895, 10904, 10914, 10923, 10933, 10943, 10952, 10961, 10971,
10981, 10990, 10999, 11012, 11025, 11038, 11051, 11064, 11076, 11089, 11102, 11115, 11128, 11141,
11153, 11165, 11177, 11189, 11201, 11213, 11225, 11237, 11248, 11260, 11272, 11284, 11296, 11308,
11320, 11332, 11343, 11355, 11367, 11378, 11390, 11402, 11414, 11426, 11438, 11450, 11462, 11473,
11485, 11497, 11509, 11521, 11533, 11545, 11557, 11568, 11577, 11587, 11597, 11606, 11616, 11626,
11638, 11650, 11662, 11674, 11686, 11698, 11710, 11721, 11733, 11745, 11757, 11769, 11781, 11793,
11805, 11816, 11829, 11842, 11854, 11864, 11874, 11883, 11892, 11901, 11909, 11921, 11933, 11945,
11957, 11969, 11981, 11992, 12003, 12014, 12025, 12036, 12047, 12058, 12068, 12079, 12090, 12101,
12112, 12123, 12134, 12145, 12155, 12166, 12177, 12188, 12199, 12210, 12221, 12232, 12242, 12253,
12264, 12274, 12285, 12296, 12307, 12318, 12329, 12340, 12351, 12361, 12372, 12383, 12394, 12405,
12416, 12427, 12438, 12448, 12455, 12462, 12469, 12476, 12486, 12496, 12506, 12516, 12526, 12536,
12546, 12555, 12562, 12569, 12576, 12583, 12594, 12605, 12616, 12627, 12638, 12649, 12660, 12670,
12681, 12692, 12703, 12714, 12725, 12736, 12747, 12757, 12767, 12777, 12787, 12797, 12807, 12817,
12827, 12836, 12844, 12853, 12862, 12870, 12879, 12888, 12896, 12903, 12911, 12919, 12926, 12934,
12942, 12950, 12957, 12964, 12974, 12984, 12993, 13004, 13015, 13026, 13037, 13045, 13054, 13062,
13071, 13079, 13086, 13094, 13102, 13110, 13117, 13127, 13137, 13146, 13157, 13168, 13179, 13190,
13198, 13206, 13214, 13221, 13230, 13239, 13248, 13257, 13265, 13273, 13283, 13293, 13302, 13313,
13324, 13335, 13346, 13354, 13362, 13370, 13377, 13386, 13395, 13404, 13413, 13421, 13429, 13435,
13441, 13447, 13453, 13459, 13465, 13477, 13489, 13500, 13512, 13524, 13536, 13548, 13560, 13572,
13578, 13590, 13602, 13614, 13626, 13638, 13650, 13657, 13668, 13675, 13685, 13695, 13705, 13715,
13725, 13735, 13745, 13754, 13760, 13766, 13772, 13778, 13784, 13790, 13796, 13802, 13808, 13814,
13821, 13828, 13836, 13844, 13852, 13860, 13867, 13874, 13881, 13888, 13896, 13904, 13912, 13920,
13927, 13934, 13942, 13950, 13957, 13965, 13973, 13980, 13990, 14000, 14010, 14020, 14030, 14039,
14046, 14053, 14060, 14067, 14074, 14081, 14089, 14097, 14104, 14112, 14120, 14127, 14135, 14143,
14150, 14158, 14166, 14173, 14177, 14181, 14187, 14196, 14205, 14214, 14222, 14230, 14238, 14247,
14256, 14265, 14275, 14287, 14297, 14305, 14315, 14323, 14331, 14339, 14347, 14355, 14363, 14371,
14375, 14381, 14387, 14395, 14403, 14411, 14419, 14425, 14431, 14439, 14445, 14454, 14463, 14472,
14480, 14488, 14496, 14505, 14514, 14523, 14529, 14535, 14544, 14555, 14564, 14575, 14584, 14595,
14603, 14612, 14623, 14632, 14643, 14652, 14663, 14671, 14679, 14687, 14695, 14703, 14708, 14727,
14747, 14768, 14774, 14784, 14792, 14804, 14815, 14825, 14834, 14844, 14852, 14861, 14871, 14879,
14888, 14897, 14906, 14914, 14926, 14937, 14947, 14956, 14966, 14974, 14983, 14996, 15008, 15019,
15029, 15040, 15049, 15058, 15071, 15083, 15094, 15104, 15115, 15124, 15131, 15142, 15152, 15161,
15169, 15178, 15191, 15198, 15209, 15222, 15230, 15238, 15246, 15254, 15260, 15266, 15277, 15286,
15297, 15308, 15317, 15328, 15338, 15345, 15354, 15366, 15373, 15381, 15395, 15409, 15415, 15424,
15430, 15439, 15445, 15452, 15459, 15466, 15472, 15480, 15488, 15496, 15504, 15512, 15520, 15528,
15536, 15546, 15555, 15565, 15573, 15581, 15590, 15598, 15607, 15614, 15621, 15630, 15638, 15647,
15654, 15661, 15668, 15677, 15685, 15692, 15700, 15708, 15715, 15722, 15731, 15739, 15746, 15752,
15760, 15768, 15776, 15785, 15793, 15802, 15810, 15818, 15827, 15836, 15844, 15852, 15861, 15869,
15876, 15885, 15894, 15903, 15911, 15919, 15927, 15934, 15941, 15947, 15953, 15963, 15972, 15980,
15988, 15998, 16007, 16013, 16022, 16031, 16039, 16048, 16056, 16066, 16076, 16085, 16095, 16105,
16115, 16124, 16133, 16142, 16151, 16159, 16168, 16177, 16187, 16195, 16204, 16212, 16221, 16229,
16238, 16246, 16255, 16264, 16273, 16281, 16290, 16299, 16308, 16317, 16325, 16334, 16342, 16351,
16359, 16368, 16377, 16387, 16397, 16404, 16413, 16421, 16427, 16435, 16447, 16458, 16468, 16477,
16485, 16494, 16502, 16511, 16520, 16529, 16537, 16549, 16560, 16570, 16579, 16587, 16594, 16605,
16615, 16624, 16632, 16639, 16648, 16657, 16666, 16676, 16688, 16701, 16712, 16722, 16733, 16741,
16751, 16759, 16767, 16779, 16795, 16805, 16819, 16829, 16843, 16853, 16867, 16875, 16887, 16895,
16907, 16913, 16922, 16928, 16937, 16945, 16953, 16961, 16970, 16978, 16986, 16994, 17003, 17011,
17018, 17025, 17032, 17042, 17051, 17059, 17067, 17077, 17086, 17094, 17102, 17110, 17120, 17129,
17137, 17145, 17155, 17164, 17172, 17181, 17190, 17200, 17210, 17217, 17226, 17234, 17246, 17262,
17272, 17286, 17296, 17310, 17320, 17334, 17342, 17354, 17362, 17374, 17380, 17386, 17394, 17399,
17408, 17415, 17422, 17431, 17439, 17448, 17455, 17463, 17471, 17480, 17498, 17514, 17519, 17526,
17533, 17540, 17543, 17548, 17554, 17558, 17564, 17573, 17579, 17588, 17594, 17601, 17609, 17613,
17621, 17636, 17642, 17647, 17653, 17659, 17664, 17670, 17678, 17685, 17691, 17700, 17708, 17715,
17720, 17725, 17745, 17750, 17755, 17761, 17768, 17774, 17781, 17788, 17795, 17802, 17808, 17816,
17828, 17836, 17846, 17858, 17865, 17872, 17879, 17886, 17894, 17902, 17917, 17924, 17936, 17949,
17956, 17962, 17975, 17980, 17985, 17990, 17995, 18003, 18008, 18017, 18023, 18028, 18035, 18042,
18047, 18052, 18061, 18066, 18076, 18086, 18091, 18096, 18101, 18107, 18114, 18120, 18127, 18133,
18141, 18148, 18155, 18162, 18170, 18179, 18184, 18190, 18196, 18203, 18211, 18217, 18222, 18228,
18234, 18239, 18244, 0
};
const char *Strs =
"PHI\000INLINEASM\000DBG_LABEL\000EH_LABEL\000GC_LABEL\000KILL\000EXTRAC"
"T_SUBREG\000INSERT_SUBREG\000IMPLICIT_DEF\000SUBREG_TO_REG\000COPY_TO_R"
"EGCLASS\000DBG_VALUE\000ADCSSri\000ADCSSrr\000ADCSSrs\000ADCri\000ADCrr"
"\000ADCrs\000ADDSri\000ADDSrr\000ADDSrs\000ADDri\000ADDrr\000ADDrs\000A"
"DJCALLSTACKDOWN\000ADJCALLSTACKUP\000ANDri\000ANDrr\000ANDrs\000ATOMIC_"
"CMP_SWAP_I16\000ATOMIC_CMP_SWAP_I32\000ATOMIC_CMP_SWAP_I8\000ATOMIC_LOA"
"D_ADD_I16\000ATOMIC_LOAD_ADD_I32\000ATOMIC_LOAD_ADD_I8\000ATOMIC_LOAD_A"
"ND_I16\000ATOMIC_LOAD_AND_I32\000ATOMIC_LOAD_AND_I8\000ATOMIC_LOAD_NAND"
"_I16\000ATOMIC_LOAD_NAND_I32\000ATOMIC_LOAD_NAND_I8\000ATOMIC_LOAD_OR_I"
"16\000ATOMIC_LOAD_OR_I32\000ATOMIC_LOAD_OR_I8\000ATOMIC_LOAD_SUB_I16\000"
"ATOMIC_LOAD_SUB_I32\000ATOMIC_LOAD_SUB_I8\000ATOMIC_LOAD_XOR_I16\000ATO"
"MIC_LOAD_XOR_I32\000ATOMIC_LOAD_XOR_I8\000ATOMIC_SWAP_I16\000ATOMIC_SWA"
"P_I32\000ATOMIC_SWAP_I8\000B\000BFC\000BFI\000BICri\000BICrr\000BICrs\000"
"BKPT\000BL\000BLX\000BLXr9\000BL_pred\000BLr9\000BLr9_pred\000BMOVPCRX\000"
"BMOVPCRXr9\000BRIND\000BR_JTadd\000BR_JTm\000BR_JTr\000BX\000BXJ\000BX_"
"RET\000BXr9\000Bcc\000CDP\000CDP2\000CLREX\000CLZ\000CMNzri\000CMNzrr\000"
"CMNzrs\000CMPri\000CMPrr\000CMPrs\000CMPzri\000CMPzrr\000CMPzrs\000CONS"
"TPOOL_ENTRY\000CPS\000DBG\000DMBish\000DMBishst\000DMBnsh\000DMBnshst\000"
"DMBosh\000DMBoshst\000DMBst\000DSBish\000DSBishst\000DSBnsh\000DSBnshst"
"\000DSBosh\000DSBoshst\000DSBst\000EORri\000EORrr\000EORrs\000FCONSTD\000"
"FCONSTS\000FMSTAT\000ISBsy\000Int_MemBarrierV6\000Int_MemBarrierV7\000I"
"nt_SyncBarrierV6\000Int_SyncBarrierV7\000Int_eh_sjlj_setjmp\000LDC2L_OF"
"FSET\000LDC2L_OPTION\000LDC2L_POST\000LDC2L_PRE\000LDC2_OFFSET\000LDC2_"
"OPTION\000LDC2_POST\000LDC2_PRE\000LDCL_OFFSET\000LDCL_OPTION\000LDCL_P"
"OST\000LDCL_PRE\000LDC_OFFSET\000LDC_OPTION\000LDC_POST\000LDC_PRE\000L"
"DM\000LDM_RET\000LDR\000LDRB\000LDRBT\000LDRB_POST\000LDRB_PRE\000LDRD\000"
"LDRD_POST\000LDRD_PRE\000LDREX\000LDREXB\000LDREXD\000LDREXH\000LDRH\000"
"LDRHT\000LDRH_POST\000LDRH_PRE\000LDRSB\000LDRSBT\000LDRSB_POST\000LDRS"
"B_PRE\000LDRSH\000LDRSHT\000LDRSH_POST\000LDRSH_PRE\000LDRT\000LDR_POST"
"\000LDR_PRE\000LDRcp\000LEApcrel\000LEApcrelJT\000MCR\000MCR2\000MCRR\000"
"MCRR2\000MLA\000MLS\000MOVCCi\000MOVCCr\000MOVCCs\000MOVPCLR\000MOVPCRX"
"\000MOVTi16\000MOVi\000MOVi16\000MOVi2pieces\000MOVi32imm\000MOVr\000MO"
"Vrx\000MOVs\000MOVsra_flag\000MOVsrl_flag\000MRC\000MRC2\000MRRC\000MRR"
"C2\000MRS\000MRSsys\000MSR\000MSRi\000MSRsys\000MSRsysi\000MUL\000MVNi\000"
"MVNr\000MVNs\000NOP\000ORRri\000ORRrr\000ORRrs\000PICADD\000PICLDR\000P"
"ICLDRB\000PICLDRH\000PICLDRSB\000PICLDRSH\000PICSTR\000PICSTRB\000PICST"
"RH\000PKHBT\000PKHTB\000PLDWi\000PLDWr\000PLDi\000PLDr\000PLIi\000PLIr\000"
"QADD\000QADD16\000QADD8\000QASX\000QDADD\000QDSUB\000QSAX\000QSUB\000QS"
"UB16\000QSUB8\000RBIT\000REV\000REV16\000REVSH\000RFE\000RFEW\000RSBSri"
"\000RSBSrs\000RSBri\000RSBrs\000RSCSri\000RSCSrs\000RSCri\000RSCrs\000S"
"ADD16\000SADD8\000SASX\000SBCSSri\000SBCSSrr\000SBCSSrs\000SBCri\000SBC"
"rr\000SBCrs\000SBFX\000SEL\000SETENDBE\000SETENDLE\000SEV\000SHADD16\000"
"SHADD8\000SHASX\000SHSAX\000SHSUB16\000SHSUB8\000SMC\000SMLABB\000SMLAB"
"T\000SMLAD\000SMLADX\000SMLAL\000SMLALBB\000SMLALBT\000SMLALD\000SMLALD"
"X\000SMLALTB\000SMLALTT\000SMLATB\000SMLATT\000SMLAWB\000SMLAWT\000SMLS"
"D\000SMLSDX\000SMLSLD\000SMLSLDX\000SMMLA\000SMMLAR\000SMMLS\000SMMLSR\000"
"SMMUL\000SMMULR\000SMUAD\000SMUADX\000SMULBB\000SMULBT\000SMULL\000SMUL"
"TB\000SMULTT\000SMULWB\000SMULWT\000SMUSD\000SMUSDX\000SRS\000SRSW\000S"
"SAT16\000SSATasr\000SSATlsl\000SSAX\000SSUB16\000SSUB8\000STC2L_OFFSET\000"
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"Auv8i16\000VRSRAuv8i8\000VRSUBHNv2i32\000VRSUBHNv4i16\000VRSUBHNv8i8\000"
"VSETLNi16\000VSETLNi32\000VSETLNi8\000VSHLLi16\000VSHLLi32\000VSHLLi8\000"
"VSHLLsv2i64\000VSHLLsv4i32\000VSHLLsv8i16\000VSHLLuv2i64\000VSHLLuv4i32"
"\000VSHLLuv8i16\000VSHLiv16i8\000VSHLiv1i64\000VSHLiv2i32\000VSHLiv2i64"
"\000VSHLiv4i16\000VSHLiv4i32\000VSHLiv8i16\000VSHLiv8i8\000VSHLsv16i8\000"
"VSHLsv1i64\000VSHLsv2i32\000VSHLsv2i64\000VSHLsv4i16\000VSHLsv4i32\000V"
"SHLsv8i16\000VSHLsv8i8\000VSHLuv16i8\000VSHLuv1i64\000VSHLuv2i32\000VSH"
"Luv2i64\000VSHLuv4i16\000VSHLuv4i32\000VSHLuv8i16\000VSHLuv8i8\000VSHRN"
"v2i32\000VSHRNv4i16\000VSHRNv8i8\000VSHRsv16i8\000VSHRsv1i64\000VSHRsv2"
"i32\000VSHRsv2i64\000VSHRsv4i16\000VSHRsv4i32\000VSHRsv8i16\000VSHRsv8i"
"8\000VSHRuv16i8\000VSHRuv1i64\000VSHRuv2i32\000VSHRuv2i64\000VSHRuv4i16"
"\000VSHRuv4i32\000VSHRuv8i16\000VSHRuv8i8\000VSHTOD\000VSHTOS\000VSITOD"
"\000VSITOS\000VSLIv16i8\000VSLIv1i64\000VSLIv2i32\000VSLIv2i64\000VSLIv"
"4i16\000VSLIv4i32\000VSLIv8i16\000VSLIv8i8\000VSLTOD\000VSLTOS\000VSQRT"
"D\000VSQRTS\000VSRAsv16i8\000VSRAsv1i64\000VSRAsv2i32\000VSRAsv2i64\000"
"VSRAsv4i16\000VSRAsv4i32\000VSRAsv8i16\000VSRAsv8i8\000VSRAuv16i8\000VS"
"RAuv1i64\000VSRAuv2i32\000VSRAuv2i64\000VSRAuv4i16\000VSRAuv4i32\000VSR"
"Auv8i16\000VSRAuv8i8\000VSRIv16i8\000VSRIv1i64\000VSRIv2i32\000VSRIv2i6"
"4\000VSRIv4i16\000VSRIv4i32\000VSRIv8i16\000VSRIv8i8\000VST1d16\000VST1"
"d16Q\000VST1d16T\000VST1d32\000VST1d32Q\000VST1d32T\000VST1d64\000VST1d"
"8\000VST1d8Q\000VST1d8T\000VST1df\000VST1q16\000VST1q32\000VST1q64\000V"
"ST1q8\000VST1qf\000VST2LNd16\000VST2LNd32\000VST2LNd8\000VST2LNq16a\000"
"VST2LNq16b\000VST2LNq32a\000VST2LNq32b\000VST2d16\000VST2d16D\000VST2d3"
"2\000VST2d32D\000VST2d64\000VST2d8\000VST2d8D\000VST2q16\000VST2q32\000"
"VST2q8\000VST3LNd16\000VST3LNd32\000VST3LNd8\000VST3LNq16a\000VST3LNq16"
"b\000VST3LNq32a\000VST3LNq32b\000VST3d16\000VST3d32\000VST3d64\000VST3d"
"8\000VST3q16a\000VST3q16b\000VST3q32a\000VST3q32b\000VST3q8a\000VST3q8b"
"\000VST4LNd16\000VST4LNd32\000VST4LNd8\000VST4LNq16a\000VST4LNq16b\000V"
"ST4LNq32a\000VST4LNq32b\000VST4d16\000VST4d32\000VST4d64\000VST4d8\000V"
"ST4q16a\000VST4q16b\000VST4q32a\000VST4q32b\000VST4q8a\000VST4q8b\000VS"
"TMD\000VSTMS\000VSTRD\000VSTRQ\000VSTRS\000VSUBD\000VSUBHNv2i32\000VSUB"
"HNv4i16\000VSUBHNv8i8\000VSUBLsv2i64\000VSUBLsv4i32\000VSUBLsv8i16\000V"
"SUBLuv2i64\000VSUBLuv4i32\000VSUBLuv8i16\000VSUBS\000VSUBWsv2i64\000VSU"
"BWsv4i32\000VSUBWsv8i16\000VSUBWuv2i64\000VSUBWuv4i32\000VSUBWuv8i16\000"
"VSUBfd\000VSUBfd_sfp\000VSUBfq\000VSUBv16i8\000VSUBv1i64\000VSUBv2i32\000"
"VSUBv2i64\000VSUBv4i16\000VSUBv4i32\000VSUBv8i16\000VSUBv8i8\000VSWPd\000"
"VSWPq\000VTBL1\000VTBL2\000VTBL3\000VTBL4\000VTBX1\000VTBX2\000VTBX3\000"
"VTBX4\000VTOSHD\000VTOSHS\000VTOSIRD\000VTOSIRS\000VTOSIZD\000VTOSIZS\000"
"VTOSLD\000VTOSLS\000VTOUHD\000VTOUHS\000VTOUIRD\000VTOUIRS\000VTOUIZD\000"
"VTOUIZS\000VTOULD\000VTOULS\000VTRNd16\000VTRNd32\000VTRNd8\000VTRNq16\000"
"VTRNq32\000VTRNq8\000VTSTv16i8\000VTSTv2i32\000VTSTv4i16\000VTSTv4i32\000"
"VTSTv8i16\000VTSTv8i8\000VUHTOD\000VUHTOS\000VUITOD\000VUITOS\000VULTOD"
"\000VULTOS\000VUZPd16\000VUZPd32\000VUZPd8\000VUZPq16\000VUZPq32\000VUZ"
"Pq8\000VZIPd16\000VZIPd32\000VZIPd8\000VZIPq16\000VZIPq32\000VZIPq8\000"
"WFE\000WFI\000YIELD\000t2ADCSri\000t2ADCSrr\000t2ADCSrs\000t2ADCri\000t"
"2ADCrr\000t2ADCrs\000t2ADDSri\000t2ADDSrr\000t2ADDSrs\000t2ADDrSPi\000t"
"2ADDrSPi12\000t2ADDrSPs\000t2ADDri\000t2ADDri12\000t2ADDrr\000t2ADDrs\000"
"t2ANDri\000t2ANDrr\000t2ANDrs\000t2ASRri\000t2ASRrr\000t2B\000t2BFC\000"
"t2BFI\000t2BICri\000t2BICrr\000t2BICrs\000t2BR_JT\000t2BXJ\000t2Bcc\000"
"t2CLREX\000t2CLZ\000t2CMNzri\000t2CMNzrr\000t2CMNzrs\000t2CMPri\000t2CM"
"Prr\000t2CMPrs\000t2CMPzri\000t2CMPzrr\000t2CMPzrs\000t2CPS\000t2DBG\000"
"t2DMBish\000t2DMBishst\000t2DMBnsh\000t2DMBnshst\000t2DMBosh\000t2DMBos"
"hst\000t2DMBst\000t2DSBish\000t2DSBishst\000t2DSBnsh\000t2DSBnshst\000t"
"2DSBosh\000t2DSBoshst\000t2DSBst\000t2EORri\000t2EORrr\000t2EORrs\000t2"
"ISBsy\000t2IT\000t2Int_MemBarrierV7\000t2Int_SyncBarrierV7\000t2Int_eh_"
"sjlj_setjmp\000t2LDM\000t2LDM_RET\000t2LDRBT\000t2LDRB_POST\000t2LDRB_P"
"RE\000t2LDRBi12\000t2LDRBi8\000t2LDRBpci\000t2LDRBs\000t2LDRDi8\000t2LD"
"RDpci\000t2LDREX\000t2LDREXB\000t2LDREXD\000t2LDREXH\000t2LDRHT\000t2LD"
"RH_POST\000t2LDRH_PRE\000t2LDRHi12\000t2LDRHi8\000t2LDRHpci\000t2LDRHs\000"
"t2LDRSBT\000t2LDRSB_POST\000t2LDRSB_PRE\000t2LDRSBi12\000t2LDRSBi8\000t"
"2LDRSBpci\000t2LDRSBs\000t2LDRSHT\000t2LDRSH_POST\000t2LDRSH_PRE\000t2L"
"DRSHi12\000t2LDRSHi8\000t2LDRSHpci\000t2LDRSHs\000t2LDRT\000t2LDR_POST\000"
"t2LDR_PRE\000t2LDRi12\000t2LDRi8\000t2LDRpci\000t2LDRpci_pic\000t2LDRs\000"
"t2LEApcrel\000t2LEApcrelJT\000t2LSLri\000t2LSLrr\000t2LSRri\000t2LSRrr\000"
"t2MLA\000t2MLS\000t2MOVCCasr\000t2MOVCCi\000t2MOVCClsl\000t2MOVCClsr\000"
"t2MOVCCr\000t2MOVCCror\000t2MOVTi16\000t2MOVi\000t2MOVi16\000t2MOVi32im"
"m\000t2MOVr\000t2MOVrx\000t2MOVsra_flag\000t2MOVsrl_flag\000t2MRS\000t2"
"MRSsys\000t2MSR\000t2MSRsys\000t2MUL\000t2MVNi\000t2MVNr\000t2MVNs\000t"
"2NOP\000t2ORNri\000t2ORNrr\000t2ORNrs\000t2ORRri\000t2ORRrr\000t2ORRrs\000"
"t2PKHBT\000t2PKHTB\000t2PLDWi12\000t2PLDWi8\000t2PLDWpci\000t2PLDWr\000"
"t2PLDWs\000t2PLDi12\000t2PLDi8\000t2PLDpci\000t2PLDr\000t2PLDs\000t2PLI"
"i12\000t2PLIi8\000t2PLIpci\000t2PLIr\000t2PLIs\000t2QADD\000t2QADD16\000"
"t2QADD8\000t2QASX\000t2QDADD\000t2QDSUB\000t2QSAX\000t2QSUB\000t2QSUB16"
"\000t2QSUB8\000t2RBIT\000t2REV\000t2REV16\000t2REVSH\000t2RFEDB\000t2RF"
"EDBW\000t2RFEIA\000t2RFEIAW\000t2RORri\000t2RORrr\000t2RSBSri\000t2RSBS"
"rs\000t2RSBri\000t2RSBrs\000t2SADD16\000t2SADD8\000t2SASX\000t2SBCSri\000"
"t2SBCSrr\000t2SBCSrs\000t2SBCri\000t2SBCrr\000t2SBCrs\000t2SBFX\000t2SD"
"IV\000t2SEL\000t2SEV\000t2SHADD16\000t2SHADD8\000t2SHASX\000t2SHSAX\000"
"t2SHSUB16\000t2SHSUB8\000t2SMC\000t2SMLABB\000t2SMLABT\000t2SMLAD\000t2"
"SMLADX\000t2SMLAL\000t2SMLALBB\000t2SMLALBT\000t2SMLALD\000t2SMLALDX\000"
"t2SMLALTB\000t2SMLALTT\000t2SMLATB\000t2SMLATT\000t2SMLAWB\000t2SMLAWT\000"
"t2SMLSD\000t2SMLSDX\000t2SMLSLD\000t2SMLSLDX\000t2SMMLA\000t2SMMLAR\000"
"t2SMMLS\000t2SMMLSR\000t2SMMUL\000t2SMMULR\000t2SMUAD\000t2SMUADX\000t2"
"SMULBB\000t2SMULBT\000t2SMULL\000t2SMULTB\000t2SMULTT\000t2SMULWB\000t2"
"SMULWT\000t2SMUSD\000t2SMUSDX\000t2SRSDB\000t2SRSDBW\000t2SRSIA\000t2SR"
"SIAW\000t2SSAT16\000t2SSATasr\000t2SSATlsl\000t2SSAX\000t2SSUB16\000t2S"
"SUB8\000t2STM\000t2STRBT\000t2STRB_POST\000t2STRB_PRE\000t2STRBi12\000t"
"2STRBi8\000t2STRBs\000t2STRDi8\000t2STREX\000t2STREXB\000t2STREXD\000t2"
"STREXH\000t2STRHT\000t2STRH_POST\000t2STRH_PRE\000t2STRHi12\000t2STRHi8"
"\000t2STRHs\000t2STRT\000t2STR_POST\000t2STR_PRE\000t2STRi12\000t2STRi8"
"\000t2STRs\000t2SUBSri\000t2SUBSrr\000t2SUBSrs\000t2SUBrSPi\000t2SUBrSP"
"i12\000t2SUBrSPi12_\000t2SUBrSPi_\000t2SUBrSPs\000t2SUBrSPs_\000t2SUBri"
"\000t2SUBri12\000t2SUBrr\000t2SUBrs\000t2SXTAB16rr\000t2SXTAB16rr_rot\000"
"t2SXTABrr\000t2SXTABrr_rot\000t2SXTAHrr\000t2SXTAHrr_rot\000t2SXTB16r\000"
"t2SXTB16r_rot\000t2SXTBr\000t2SXTBr_rot\000t2SXTHr\000t2SXTHr_rot\000t2"
"TBB\000t2TBBgen\000t2TBH\000t2TBHgen\000t2TEQri\000t2TEQrr\000t2TEQrs\000"
"t2TPsoft\000t2TSTri\000t2TSTrr\000t2TSTrs\000t2UADD16\000t2UADD8\000t2U"
"ASX\000t2UBFX\000t2UDIV\000t2UHADD16\000t2UHADD8\000t2UHASX\000t2UHSAX\000"
"t2UHSUB16\000t2UHSUB8\000t2UMAAL\000t2UMLAL\000t2UMULL\000t2UQADD16\000"
"t2UQADD8\000t2UQASX\000t2UQSAX\000t2UQSUB16\000t2UQSUB8\000t2USAD8\000t"
"2USADA8\000t2USAT16\000t2USATasr\000t2USATlsl\000t2USAX\000t2USUB16\000"
"t2USUB8\000t2UXTAB16rr\000t2UXTAB16rr_rot\000t2UXTABrr\000t2UXTABrr_rot"
"\000t2UXTAHrr\000t2UXTAHrr_rot\000t2UXTB16r\000t2UXTB16r_rot\000t2UXTBr"
"\000t2UXTBr_rot\000t2UXTHr\000t2UXTHr_rot\000t2WFE\000t2WFI\000t2YIELD\000"
"tADC\000tADDhirr\000tADDi3\000tADDi8\000tADDrPCi\000tADDrSP\000tADDrSPi"
"\000tADDrr\000tADDspi\000tADDspr\000tADDspr_\000tADJCALLSTACKDOWN\000tA"
"DJCALLSTACKUP\000tAND\000tANDsp\000tASRri\000tASRrr\000tB\000tBIC\000tB"
"KPT\000tBL\000tBLXi\000tBLXi_r9\000tBLXr\000tBLXr_r9\000tBLr9\000tBRIND"
"\000tBR_JTr\000tBX\000tBX_RET\000tBX_RET_vararg\000tBXr9\000tBcc\000tBf"
"ar\000tCBNZ\000tCBZ\000tCMNz\000tCMPhir\000tCMPi8\000tCMPr\000tCMPzhir\000"
"tCMPzi8\000tCMPzr\000tCPS\000tEOR\000tInt_eh_sjlj_setjmp\000tLDM\000tLD"
"R\000tLDRB\000tLDRBi\000tLDRH\000tLDRHi\000tLDRSB\000tLDRSH\000tLDRcp\000"
"tLDRi\000tLDRpci\000tLDRpci_pic\000tLDRspi\000tLEApcrel\000tLEApcrelJT\000"
"tLSLri\000tLSLrr\000tLSRri\000tLSRrr\000tMOVCCi\000tMOVCCr\000tMOVCCr_p"
"seudo\000tMOVSr\000tMOVgpr2gpr\000tMOVgpr2tgpr\000tMOVi8\000tMOVr\000tM"
"OVtgpr2gpr\000tMUL\000tMVN\000tNOP\000tORR\000tPICADD\000tPOP\000tPOP_R"
"ET\000tPUSH\000tREV\000tREV16\000tREVSH\000tROR\000tRSB\000tRestore\000"
"tSBC\000tSETENDBE\000tSETENDLE\000tSEV\000tSTM\000tSTR\000tSTRB\000tSTR"
"Bi\000tSTRH\000tSTRHi\000tSTRi\000tSTRspi\000tSUBi3\000tSUBi8\000tSUBrr"
"\000tSUBspi\000tSUBspi_\000tSVC\000tSXTB\000tSXTH\000tSpill\000tTPsoft\000"
"tTRAP\000tTST\000tUXTB\000tUXTH\000tWFE\000tWFI\000tYIELD\000";
return Strs+InstAsmOffset[Opcode];
}
#endif