//===- TableGen'erated file -------------------------------------*- C++ -*-===//
//
// Machine Code Emitter
//
// Automatically generated file, do not edit!
//
//===----------------------------------------------------------------------===//
unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
static const unsigned InstBits[] = {
0U,
0U,
0U,
0U,
0U,
0U,
0U,
0U,
0U,
0U,
0U,
0U,
45088768U, // ADCSSri
11534336U, // ADCSSrr
11534336U, // ADCSSrs
44040192U, // ADCri
10485760U, // ADCrr
10485760U, // ADCrs
42991616U, // ADDSri
9437184U, // ADDSrr
9437184U, // ADDSrs
41943040U, // ADDri
8388608U, // ADDrr
8388608U, // ADDrs
0U, // ADJCALLSTACKDOWN
0U, // ADJCALLSTACKUP
33554432U, // ANDri
0U, // ANDrr
0U, // ANDrs
0U, // ATOMIC_CMP_SWAP_I16
0U, // ATOMIC_CMP_SWAP_I32
0U, // ATOMIC_CMP_SWAP_I8
0U, // ATOMIC_LOAD_ADD_I16
0U, // ATOMIC_LOAD_ADD_I32
0U, // ATOMIC_LOAD_ADD_I8
0U, // ATOMIC_LOAD_AND_I16
0U, // ATOMIC_LOAD_AND_I32
0U, // ATOMIC_LOAD_AND_I8
0U, // ATOMIC_LOAD_NAND_I16
0U, // ATOMIC_LOAD_NAND_I32
0U, // ATOMIC_LOAD_NAND_I8
0U, // ATOMIC_LOAD_OR_I16
0U, // ATOMIC_LOAD_OR_I32
0U, // ATOMIC_LOAD_OR_I8
0U, // ATOMIC_LOAD_SUB_I16
0U, // ATOMIC_LOAD_SUB_I32
0U, // ATOMIC_LOAD_SUB_I8
0U, // ATOMIC_LOAD_XOR_I16
0U, // ATOMIC_LOAD_XOR_I32
0U, // ATOMIC_LOAD_XOR_I8
0U, // ATOMIC_SWAP_I16
0U, // ATOMIC_SWAP_I32
0U, // ATOMIC_SWAP_I8
167772160U, // B
130023455U, // BFC
130023440U, // BFI
62914560U, // BICri
29360128U, // BICrr
29360128U, // BICrs
18874480U, // BKPT
3942645760U, // BL
19922736U, // BLX
19922736U, // BLXr9
184549376U, // BL_pred
3942645760U, // BLr9
184549376U, // BLr9_pred
27324416U, // BMOVPCRX
27324416U, // BMOVPCRXr9
3778019088U, // BRIND
8450048U, // BR_JTadd
118550528U, // BR_JTm
27324416U, // BR_JTr
19922704U, // BX
18874400U, // BXJ
19922718U, // BX_RET
19922704U, // BXr9
167772160U, // Bcc
234881024U, // CDP
4261412864U, // CDP2
4117757968U, // CLREX
24055568U, // CLZ
57671680U, // CMNzri
24117248U, // CMNzrr
24117248U, // CMNzrs
55574528U, // CMPri
22020096U, // CMPrr
22020096U, // CMPrs
55574528U, // CMPzri
22020096U, // CMPzrr
22020096U, // CMPzrs
0U, // CONSTPOOL_ENTRY
4043309056U, // CPS
52429040U, // DBG
4117758043U, // DMBish
4117758042U, // DMBishst
4117758039U, // DMBnsh
4117758038U, // DMBnshst
4117758035U, // DMBosh
4117758034U, // DMBoshst
4117758046U, // DMBst
4117758027U, // DSBish
4117758026U, // DSBishst
4117758023U, // DSBnsh
4117758022U, // DSBnshst
4117758019U, // DSBosh
4117758018U, // DSBoshst
4117758030U, // DSBst
35651584U, // EORri
2097152U, // EORrr
2097152U, // EORrs
246418176U, // FCONSTD
246417920U, // FCONSTS
250739216U, // FMSTAT
4117758063U, // ISBsy
0U, // Int_MemBarrierV6
4118802527U, // Int_MemBarrierV7
0U, // Int_SyncBarrierV6
4118802511U, // Int_SyncBarrierV7
0U, // Int_eh_sjlj_setjmp
4249878528U, // LDC2L_OFFSET
4241489920U, // LDC2L_OPTION
4235198464U, // LDC2L_POST
4251975680U, // LDC2L_PRE
4245684224U, // LDC2_OFFSET
4237295616U, // LDC2_OPTION
4231004160U, // LDC2_POST
4247781376U, // LDC2_PRE
223346688U, // LDCL_OFFSET
214958080U, // LDCL_OPTION
208666624U, // LDCL_POST
225443840U, // LDCL_PRE
219152384U, // LDC_OFFSET
210763776U, // LDC_OPTION
204472320U, // LDC_POST
221249536U, // LDC_PRE
135266304U, // LDM
135266304U, // LDM_RET
84934656U, // LDR
89128960U, // LDRB
74448896U, // LDRBT
72351744U, // LDRB_POST
91226112U, // LDRB_PRE
16777424U, // LDRD
208U, // LDRD_POST
18874576U, // LDRD_PRE
26218399U, // LDREX
30412703U, // LDREXB
28315551U, // LDREXD
32509855U, // LDREXH
17825968U, // LDRH
3145904U, // LDRHT
1048752U, // LDRH_POST
19923120U, // LDRH_PRE
17826000U, // LDRSB
3145936U, // LDRSBT
1048784U, // LDRSB_POST
19923152U, // LDRSB_PRE
17826032U, // LDRSH
3145968U, // LDRSHT
1048816U, // LDRSH_POST
19923184U, // LDRSH_PRE
70254592U, // LDRT
68157440U, // LDR_POST
87031808U, // LDR_PRE
84934656U, // LDRcp
0U, // LEApcrel
33554432U, // LEApcrelJT
234881040U, // MCR
4261412880U, // MCR2
205520896U, // MCRR
4232052736U, // MCRR2
2097296U, // MLA
6291600U, // MLS
60817408U, // MOVCCi
27262976U, // MOVCCr
27262976U, // MOVCCs
27324430U, // MOVPCLR
3785420800U, // MOVPCRX
54525952U, // MOVTi16
60817408U, // MOVi
50331648U, // MOVi16
0U, // MOVi2pieces
0U, // MOVi32imm
27262976U, // MOVr
27262976U, // MOVrx
27262976U, // MOVs
27262976U, // MOVsra_flag
27262976U, // MOVsrl_flag
235929616U, // MRC
4262461456U, // MRC2
206569472U, // MRRC
4233101312U, // MRRC2
16777216U, // MRS
20971520U, // MRSsys
18874368U, // MSR
52428800U, // MSRi
23068672U, // MSRsys
56623104U, // MSRsysi
144U, // MUL
65011712U, // MVNi
31457280U, // MVNr
31457280U, // MVNs
52428800U, // NOP
58720256U, // ORRri
25165824U, // ORRrr
25165824U, // ORRrs
8388608U, // PICADD
84934656U, // PICLDR
89128960U, // PICLDRB
17825968U, // PICLDRH
17826000U, // PICLDRSB
17826032U, // PICLDRSH
83886080U, // PICSTR
88080384U, // PICSTRB
16777392U, // PICSTRH
109051920U, // PKHBT
109051984U, // PKHTB
4111466496U, // PLDWi
4145020928U, // PLDWr
4115660800U, // PLDi
4149215232U, // PLDr
4098883584U, // PLIi
4132438016U, // PLIr
16777296U, // QADD
102760464U, // QADD16
102760592U, // QADD8
102760496U, // QASX
20971600U, // QDADD
23068752U, // QDSUB
102760528U, // QSAX
18874448U, // QSUB
102760560U, // QSUB16
102760688U, // QSUB8
117378864U, // RBIT
113184560U, // REV
113184688U, // REV16
117378992U, // REVSH
4161798144U, // RFE
4163895296U, // RFEW
40894464U, // RSBSri
7340032U, // RSBSrs
39845888U, // RSBri
6291456U, // RSBrs
49283072U, // RSCSri
15728640U, // RSCSrs
48234496U, // RSCri
14680064U, // RSCrs
101711888U, // SADD16
101712016U, // SADD8
101711920U, // SASX
47185920U, // SBCSSri
13631488U, // SBCSSrr
13631488U, // SBCSSrs
46137344U, // SBCri
12582912U, // SBCrr
12582912U, // SBCrs
127926352U, // SBFX
109052080U, // SEL
4043375104U, // SETENDBE
4043374592U, // SETENDLE
52428804U, // SEV
103809040U, // SHADD16
103809168U, // SHADD8
103809072U, // SHASX
103809104U, // SHSAX
103809136U, // SHSUB16
103809264U, // SHSUB8
23068784U, // SMC
16777344U, // SMLABB
16777408U, // SMLABT
117440528U, // SMLAD
117440560U, // SMLADX
14680208U, // SMLAL
20971648U, // SMLALBB
20971712U, // SMLALBT
121634832U, // SMLALD
121634864U, // SMLALDX
20971680U, // SMLALTB
20971744U, // SMLALTT
16777376U, // SMLATB
16777440U, // SMLATT
18874496U, // SMLAWB
18874560U, // SMLAWT
117440592U, // SMLSD
117440624U, // SMLSDX
121634896U, // SMLSLD
121634928U, // SMLSLDX
122683408U, // SMMLA
122683440U, // SMMLAR
122683600U, // SMMLS
122683632U, // SMMLSR
122744848U, // SMMUL
122744880U, // SMMULR
117501968U, // SMUAD
117502000U, // SMUADX
23068800U, // SMULBB
23068864U, // SMULBT
12583056U, // SMULL
23068832U, // SMULTB
23068896U, // SMULTT
18874528U, // SMULWB
18874592U, // SMULWT
117502032U, // SMUSD
117502064U, // SMUSDX
4164943872U, // SRS
4167041024U, // SRSW
111149104U, // SSAT16
111149136U, // SSATasr
111149072U, // SSATlsl
101711952U, // SSAX
101711984U, // SSUB16
101712112U, // SSUB8
4248829952U, // STC2L_OFFSET
4240441344U, // STC2L_OPTION
4234149888U, // STC2L_POST
4250927104U, // STC2L_PRE
4244635648U, // STC2_OFFSET
4236247040U, // STC2_OPTION
4229955584U, // STC2_POST
4246732800U, // STC2_PRE
222298112U, // STCL_OFFSET
213909504U, // STCL_OPTION
207618048U, // STCL_POST
224395264U, // STCL_PRE
218103808U, // STC_OFFSET
209715200U, // STC_OPTION
203423744U, // STC_POST
220200960U, // STC_PRE
134217728U, // STM
83886080U, // STR
88080384U, // STRB
73400320U, // STRBT
71303168U, // STRB_POST
90177536U, // STRB_PRE
16777456U, // STRD
240U, // STRD_POST
18874608U, // STRD_PRE
25169808U, // STREX
29364112U, // STREXB
27266960U, // STREXD
31461264U, // STREXH
16777392U, // STRH
2097328U, // STRHT
176U, // STRH_POST
18874544U, // STRH_PRE
69206016U, // STRT
67108864U, // STR_POST
85983232U, // STR_PRE
38797312U, // SUBSri
5242880U, // SUBSrr
5242880U, // SUBSrs
37748736U, // SUBri
4194304U, // SUBrr
4194304U, // SUBrs
251658240U, // SVC
16777360U, // SWP
20971664U, // SWPB
109052016U, // SXTAB16rr
109052016U, // SXTAB16rr_rot
111149168U, // SXTABrr
111149168U, // SXTABrr_rot
112197744U, // SXTAHrr
112197744U, // SXTAHrr_rot
110035056U, // SXTB16r
110035056U, // SXTB16r_rot
112132208U, // SXTBr
112132208U, // SXTBr_rot
113180784U, // SXTHr
113180784U, // SXTHr_rot
53477376U, // TEQri
19922944U, // TEQrr
19922944U, // TEQrs
184549376U, // TPsoft
133169392U, // TRAP
51380224U, // TSTri
17825792U, // TSTrr
17825792U, // TSTrs
105906192U, // UADD16
105906320U, // UADD8
105906224U, // UASX
132120656U, // UBFX
108003344U, // UHADD16
108003472U, // UHADD8
108003376U, // UHASX
108003408U, // UHSAX
108003440U, // UHSUB16
108003568U, // UHSUB8
4194448U, // UMAAL
10485904U, // UMLAL
8388752U, // UMULL
106954768U, // UQADD16
106954896U, // UQADD8
106954800U, // UQASX
106954832U, // UQSAX
106954864U, // UQSUB16
106954992U, // UQSUB8
125890576U, // USAD8
125829136U, // USADA8
115343408U, // USAT16
115343440U, // USATasr
115343376U, // USATlsl
105906256U, // USAX
105906288U, // USUB16
105906416U, // USUB8
113246320U, // UXTAB16rr
113246320U, // UXTAB16rr_rot
115343472U, // UXTABrr
115343472U, // UXTABrr_rot
116392048U, // UXTAHrr
116392048U, // UXTAHrr_rot
114229360U, // UXTB16r
114229360U, // UXTB16r_rot
116326512U, // UXTBr
116326512U, // UXTBr_rot
117375088U, // UXTHr
117375088U, // UXTHr_rot
4070573312U, // VABALsv2i64
4069524736U, // VABALsv4i32
4068476160U, // VABALsv8i16
4087350528U, // VABALuv2i64
4086301952U, // VABALuv4i32
4085253376U, // VABALuv8i16
4060088144U, // VABAsv16i8
4062185232U, // VABAsv2i32
4061136656U, // VABAsv4i16
4062185296U, // VABAsv4i32
4061136720U, // VABAsv8i16
4060088080U, // VABAsv8i8
4076865360U, // VABAuv16i8
4078962448U, // VABAuv2i32
4077913872U, // VABAuv4i16
4078962512U, // VABAuv4i32
4077913936U, // VABAuv8i16
4076865296U, // VABAuv8i8
4070573824U, // VABDLsv2i64
4069525248U, // VABDLsv4i32
4068476672U, // VABDLsv8i16
4087351040U, // VABDLuv2i64
4086302464U, // VABDLuv4i32
4085253888U, // VABDLuv8i16
4078963968U, // VABDfd
4078964032U, // VABDfq
4060088128U, // VABDsv16i8
4062185216U, // VABDsv2i32
4061136640U, // VABDsv4i16
4062185280U, // VABDsv4i32
4061136704U, // VABDsv8i16
4060088064U, // VABDsv8i8
4076865344U, // VABDuv16i8
4078962432U, // VABDuv2i32
4077913856U, // VABDuv4i16
4078962496U, // VABDuv4i32
4077913920U, // VABDuv8i16
4076865280U, // VABDuv8i8
246418368U, // VABSD
246418112U, // VABSS
4088989440U, // VABSfd
4088989440U, // VABSfd_sfp
4088989504U, // VABSfq
4088464192U, // VABSv16i8
4088988416U, // VABSv2i32
4088726272U, // VABSv4i16
4088988480U, // VABSv4i32
4088726336U, // VABSv8i16
4088464128U, // VABSv8i8
4076867088U, // VACGEd
4076867152U, // VACGEq
4078964240U, // VACGTd
4078964304U, // VACGTq
238029568U, // VADDD
4070573056U, // VADDHNv2i32
4069524480U, // VADDHNv4i16
4068475904U, // VADDHNv8i8
4070572032U, // VADDLsv2i64
4069523456U, // VADDLsv4i32
4068474880U, // VADDLsv8i16
4087349248U, // VADDLuv2i64
4086300672U, // VADDLuv4i32
4085252096U, // VADDLuv8i16
238029312U, // VADDS
4070572288U, // VADDWsv2i64
4069523712U, // VADDWsv4i32
4068475136U, // VADDWsv8i16
4087349504U, // VADDWuv2i64
4086300928U, // VADDWuv4i32
4085252352U, // VADDWuv8i16
4060089600U, // VADDfd
4060089600U, // VADDfd_sfp
4060089664U, // VADDfq
4060088384U, // VADDv16i8
4063234048U, // VADDv1i64
4062185472U, // VADDv2i32
4063234112U, // VADDv2i64
4061136896U, // VADDv4i16
4062185536U, // VADDv4i32
4061136960U, // VADDv8i16
4060088320U, // VADDv8i8
4060086544U, // VANDd
4060086608U, // VANDq
4061135120U, // VBICd
4061135184U, // VBICq
4080009488U, // VBIFd
4080009552U, // VBIFq
4078960912U, // VBITd
4078960976U, // VBITq
4077912336U, // VBSLd
4077912400U, // VBSLq
4060089856U, // VCEQfd
4060089920U, // VCEQfq
4076865616U, // VCEQv16i8
4078962704U, // VCEQv2i32
4077914128U, // VCEQv4i16
4078962768U, // VCEQv4i32
4077914192U, // VCEQv8i16
4076865552U, // VCEQv8i8
4088463680U, // VCEQzv16i8
4088988928U, // VCEQzv2f32
4088987904U, // VCEQzv2i32
4088988992U, // VCEQzv4f32
4088725760U, // VCEQzv4i16
4088987968U, // VCEQzv4i32
4088725824U, // VCEQzv8i16
4088463616U, // VCEQzv8i8
4076867072U, // VCGEfd
4076867136U, // VCGEfq
4060087120U, // VCGEsv16i8
4062184208U, // VCGEsv2i32
4061135632U, // VCGEsv4i16
4062184272U, // VCGEsv4i32
4061135696U, // VCGEsv8i16
4060087056U, // VCGEsv8i8
4076864336U, // VCGEuv16i8
4078961424U, // VCGEuv2i32
4077912848U, // VCGEuv4i16
4078961488U, // VCGEuv4i32
4077912912U, // VCGEuv8i16
4076864272U, // VCGEuv8i8
4088463552U, // VCGEzv16i8
4088988800U, // VCGEzv2f32
4088987776U, // VCGEzv2i32
4088988864U, // VCGEzv4f32
4088725632U, // VCGEzv4i16
4088987840U, // VCGEzv4i32
4088725696U, // VCGEzv8i16
4088463488U, // VCGEzv8i8
4078964224U, // VCGTfd
4078964288U, // VCGTfq
4060087104U, // VCGTsv16i8
4062184192U, // VCGTsv2i32
4061135616U, // VCGTsv4i16
4062184256U, // VCGTsv4i32
4061135680U, // VCGTsv8i16
4060087040U, // VCGTsv8i8
4076864320U, // VCGTuv16i8
4078961408U, // VCGTuv2i32
4077912832U, // VCGTuv4i16
4078961472U, // VCGTuv4i32
4077912896U, // VCGTuv8i16
4076864256U, // VCGTuv8i8
4088463424U, // VCGTzv16i8
4088988672U, // VCGTzv2f32
4088987648U, // VCGTzv2i32
4088988736U, // VCGTzv4f32
4088725504U, // VCGTzv4i16
4088987712U, // VCGTzv4i32
4088725568U, // VCGTzv8i16
4088463360U, // VCGTzv8i8
4088463808U, // VCLEzv16i8
4088989056U, // VCLEzv2f32
4088988032U, // VCLEzv2i32
4088989120U, // VCLEzv4f32
4088725888U, // VCLEzv4i16
4088988096U, // VCLEzv4i32
4088725952U, // VCLEzv8i16
4088463744U, // VCLEzv8i8
4088398912U, // VCLSv16i8
4088923136U, // VCLSv2i32
4088660992U, // VCLSv4i16
4088923200U, // VCLSv4i32
4088661056U, // VCLSv8i16
4088398848U, // VCLSv8i8
4088463936U, // VCLTzv16i8
4088989184U, // VCLTzv2f32
4088988160U, // VCLTzv2i32
4088989248U, // VCLTzv4f32
4088726016U, // VCLTzv4i16
4088988224U, // VCLTzv4i32
4088726080U, // VCLTzv8i16
4088463872U, // VCLTzv8i8
4088399040U, // VCLZv16i8
4088923264U, // VCLZv2i32
4088661120U, // VCLZv4i16
4088923328U, // VCLZv4i32
4088661184U, // VCLZv8i16
4088398976U, // VCLZv8i8
246680384U, // VCMPD
246680512U, // VCMPED
246680256U, // VCMPES
246746048U, // VCMPEZD
246745792U, // VCMPEZS
246680128U, // VCMPS
246745920U, // VCMPZD
246745664U, // VCMPZS
4088399104U, // VCNTd
4088399168U, // VCNTq
246614592U, // VCVTBHS
246549056U, // VCVTBSH
246876864U, // VCVTDS
246877120U, // VCVTSD
246614720U, // VCVTTHS
246549184U, // VCVTTSH
4089120512U, // VCVTf2sd
4089120512U, // VCVTf2sd_sfp
4089120576U, // VCVTf2sq
4089120640U, // VCVTf2ud
4089120640U, // VCVTf2ud_sfp
4089120704U, // VCVTf2uq
4068478736U, // VCVTf2xsd
4068478800U, // VCVTf2xsq
4085255952U, // VCVTf2xud
4085256016U, // VCVTf2xuq
4089120256U, // VCVTs2fd
4089120256U, // VCVTs2fd_sfp
4089120320U, // VCVTs2fq
4089120384U, // VCVTu2fd
4089120384U, // VCVTu2fd_sfp
4089120448U, // VCVTu2fq
4068478480U, // VCVTxs2fd
4068478544U, // VCVTxs2fq
4085255696U, // VCVTxu2fd
4085255760U, // VCVTxu2fq
243272448U, // VDIVD
243272192U, // VDIVS
243272496U, // VDUP16d
245369648U, // VDUP16q
243272464U, // VDUP32d
245369616U, // VDUP32q
247466768U, // VDUP8d
249563920U, // VDUP8q
4088531968U, // VDUPLN16d
4088532032U, // VDUPLN16q
4088663040U, // VDUPLN32d
4088663104U, // VDUPLN32q
4088466432U, // VDUPLN8d
4088466496U, // VDUPLN8q
4088663040U, // VDUPLNfd
4088663104U, // VDUPLNfq
243272464U, // VDUPfd
4088663040U, // VDUPfdf
245369616U, // VDUPfq
4088663104U, // VDUPfqf
4076863760U, // VEORd
4076863824U, // VEORq
4071620608U, // VEXTd16
4071620608U, // VEXTd32
4071620608U, // VEXTd8
4071620608U, // VEXTdf
4071620672U, // VEXTq16
4071620672U, // VEXTq32
4071620672U, // VEXTq8
4071620672U, // VEXTqf
235932432U, // VGETLNi32
235932464U, // VGETLNs16
240126736U, // VGETLNs8
244321072U, // VGETLNu16
248515344U, // VGETLNu8
4060086336U, // VHADDsv16i8
4062183424U, // VHADDsv2i32
4061134848U, // VHADDsv4i16
4062183488U, // VHADDsv4i32
4061134912U, // VHADDsv8i16
4060086272U, // VHADDsv8i8
4076863552U, // VHADDuv16i8
4078960640U, // VHADDuv2i32
4077912064U, // VHADDuv4i16
4078960704U, // VHADDuv4i32
4077912128U, // VHADDuv8i16
4076863488U, // VHADDuv8i8
4060086848U, // VHSUBsv16i8
4062183936U, // VHSUBsv2i32
4061135360U, // VHSUBsv4i16
4062184000U, // VHSUBsv4i32
4061135424U, // VHSUBsv8i16
4060086784U, // VHSUBsv8i8
4076864064U, // VHSUBuv16i8
4078961152U, // VHSUBuv2i32
4077912576U, // VHSUBuv4i16
4078961216U, // VHSUBuv4i32
4077912640U, // VHSUBuv8i16
4076864000U, // VHSUBuv8i8
4095739712U, // VLD1d16
4095738432U, // VLD1d16Q
4095739456U, // VLD1d16T
4095739776U, // VLD1d32
4095738496U, // VLD1d32Q
4095739520U, // VLD1d32T
4095739840U, // VLD1d64
4095739648U, // VLD1d8
4095738368U, // VLD1d8Q
4095739392U, // VLD1d8T
4095739776U, // VLD1df
4095740480U, // VLD1q16
4095740544U, // VLD1q32
4095740608U, // VLD1q64
4095740416U, // VLD1q8
4095740544U, // VLD1qf
4104127744U, // VLD2LNd16
4104128768U, // VLD2LNd32
4104126720U, // VLD2LNd8
4104127776U, // VLD2LNq16a
4104127776U, // VLD2LNq16b
4104128832U, // VLD2LNq32a
4104128832U, // VLD2LNq32b
4095739968U, // VLD2d16
4095740224U, // VLD2d16D
4095740032U, // VLD2d32
4095740288U, // VLD2d32D
4095740608U, // VLD2d64
4095739904U, // VLD2d8
4095740160U, // VLD2d8D
4095738688U, // VLD2q16
4095738752U, // VLD2q32
4095738624U, // VLD2q8
4104128000U, // VLD3LNd16
4104129024U, // VLD3LNd32
4104126976U, // VLD3LNd8
4104128032U, // VLD3LNq16a
4104128032U, // VLD3LNq16b
4104129088U, // VLD3LNq32a
4104129088U, // VLD3LNq32b
4095738944U, // VLD3d16
4095739008U, // VLD3d32
4095739584U, // VLD3d64
4095738880U, // VLD3d8
4095739200U, // VLD3q16a
4095739200U, // VLD3q16b
4095739264U, // VLD3q32a
4095739264U, // VLD3q32b
4095739136U, // VLD3q8a
4095739136U, // VLD3q8b
4104128256U, // VLD4LNd16
4104129280U, // VLD4LNd32
4104127232U, // VLD4LNd8
4104128288U, // VLD4LNq16a
4104128288U, // VLD4LNq16b
4104129344U, // VLD4LNq32a
4104129344U, // VLD4LNq32b
4095737920U, // VLD4d16
4095737984U, // VLD4d32
4095738560U, // VLD4d64
4095737856U, // VLD4d8
4095738176U, // VLD4q16a
4095738176U, // VLD4q16b
4095738240U, // VLD4q32a
4095738240U, // VLD4q32b
4095738112U, // VLD4q8a
4095738112U, // VLD4q8b
202377984U, // VLDMD
202377728U, // VLDMS
219155200U, // VLDRD
210766592U, // VLDRQ
219154944U, // VLDRS
4060090112U, // VMAXfd
4060090112U, // VMAXfd_sfp
4060090176U, // VMAXfq
4060087872U, // VMAXsv16i8
4062184960U, // VMAXsv2i32
4061136384U, // VMAXsv4i16
4062185024U, // VMAXsv4i32
4061136448U, // VMAXsv8i16
4060087808U, // VMAXsv8i8
4076865088U, // VMAXuv16i8
4078962176U, // VMAXuv2i32
4077913600U, // VMAXuv4i16
4078962240U, // VMAXuv4i32
4077913664U, // VMAXuv8i16
4076865024U, // VMAXuv8i8
4062187264U, // VMINfd
4060090112U, // VMINfd_sfp
4062187328U, // VMINfq
4060087888U, // VMINsv16i8
4062184976U, // VMINsv2i32
4061136400U, // VMINsv4i16
4062185040U, // VMINsv4i32
4061136464U, // VMINsv8i16
4060087824U, // VMINsv8i8
4076865104U, // VMINuv16i8
4078962192U, // VMINuv2i32
4077913616U, // VMINuv4i16
4078962256U, // VMINuv4i32
4077913680U, // VMINuv8i16
4076865040U, // VMINuv8i8
234883840U, // VMLAD
4070572608U, // VMLALslsv2i32
4069524032U, // VMLALslsv4i16
4087349824U, // VMLALsluv2i32
4086301248U, // VMLALsluv4i16
4070574080U, // VMLALsv2i64
4069525504U, // VMLALsv4i32
4068476928U, // VMLALsv8i16
4087351296U, // VMLALuv2i64
4086302720U, // VMLALuv4i32
4085254144U, // VMLALuv8i16
234883584U, // VMLAS
4060089616U, // VMLAfd
4060089680U, // VMLAfq
4070572352U, // VMLAslfd
4087349568U, // VMLAslfq
4070572096U, // VMLAslv2i32
4069523520U, // VMLAslv4i16
4087349312U, // VMLAslv4i32
4086300736U, // VMLAslv8i16
4060088640U, // VMLAv16i8
4062185728U, // VMLAv2i32
4061137152U, // VMLAv4i16
4062185792U, // VMLAv4i32
4061137216U, // VMLAv8i16
4060088576U, // VMLAv8i8
234883904U, // VMLSD
4070573632U, // VMLSLslsv2i32
4069525056U, // VMLSLslsv4i16
4087350848U, // VMLSLsluv2i32
4086302272U, // VMLSLsluv4i16
4070574592U, // VMLSLsv2i64
4069526016U, // VMLSLsv4i32
4068477440U, // VMLSLsv8i16
4087351808U, // VMLSLuv2i64
4086303232U, // VMLSLuv4i32
4085254656U, // VMLSLuv8i16
234883648U, // VMLSS
4062186768U, // VMLSfd
4062186832U, // VMLSfq
4070573376U, // VMLSslfd
4087350592U, // VMLSslfq
4070573120U, // VMLSslv2i32
4069524544U, // VMLSslv4i16
4087350336U, // VMLSslv4i32
4086301760U, // VMLSslv8i16
4076865856U, // VMLSv16i8
4078962944U, // VMLSv2i32
4077914368U, // VMLSv4i16
4078963008U, // VMLSv4i32
4077914432U, // VMLSv8i16
4076865792U, // VMLSv8i8
246418240U, // VMOVD
205523728U, // VMOVDRR
246418240U, // VMOVDcc
4062183696U, // VMOVDneon
4070574608U, // VMOVLsv2i64
4069526032U, // VMOVLsv4i32
4069001744U, // VMOVLsv8i16
4087351824U, // VMOVLuv2i64
4086303248U, // VMOVLuv4i32
4085778960U, // VMOVLuv8i16
4089053696U, // VMOVNv2i32
4088791552U, // VMOVNv4i16
4088529408U, // VMOVNv8i8
4062183760U, // VMOVQ
206572304U, // VMOVRRD
206572048U, // VMOVRRS
235932176U, // VMOVRS
246417984U, // VMOVS
234883600U, // VMOVSR
205523472U, // VMOVSRR
246417984U, // VMOVScc
4068478544U, // VMOVv16i8
4068478512U, // VMOVv1i64
4068474896U, // VMOVv2i32
4068478576U, // VMOVv2i64
4068476944U, // VMOVv4i16
4068474960U, // VMOVv4i32
4068477008U, // VMOVv8i16
4068478480U, // VMOVv8i8
250677776U, // VMRS
249629200U, // VMSR
236980992U, // VMULD
4068478464U, // VMULLp
4070574656U, // VMULLslsv2i32
4069526080U, // VMULLslsv4i16
4087351872U, // VMULLsluv2i32
4086303296U, // VMULLsluv4i16
4070575104U, // VMULLsv2i64
4069526528U, // VMULLsv4i32
4068477952U, // VMULLsv8i16
4087352320U, // VMULLuv2i64
4086303744U, // VMULLuv4i32
4085255168U, // VMULLuv8i16
236980736U, // VMULS
4076866832U, // VMULfd
4076866832U, // VMULfd_sfp
4076866896U, // VMULfq
4076865808U, // VMULpd
4076865872U, // VMULpq
4070574400U, // VMULslfd
4087351616U, // VMULslfq
4070574144U, // VMULslv2i32
4069525568U, // VMULslv4i16
4087351360U, // VMULslv4i32
4086302784U, // VMULslv8i16
4060088656U, // VMULv16i8
4062185744U, // VMULv2i32
4061137168U, // VMULv4i16
4062185808U, // VMULv4i32
4061137232U, // VMULv8i16
4060088592U, // VMULv8i8
4088399232U, // VMVNd
4088399296U, // VMVNq
246483776U, // VNEGD
246483776U, // VNEGDcc
246483520U, // VNEGS
246483520U, // VNEGScc
4088989632U, // VNEGf32q
4088989568U, // VNEGfd
4088989568U, // VNEGfd_sfp
4088726400U, // VNEGs16d
4088726464U, // VNEGs16q
4088988544U, // VNEGs32d
4088988608U, // VNEGs32q
4088464256U, // VNEGs8d
4088464320U, // VNEGs8q
235932480U, // VNMLAD
235932224U, // VNMLAS
235932416U, // VNMLSD
235932160U, // VNMLSS
236981056U, // VNMULD
236980800U, // VNMULS
4063232272U, // VORNd
4063232336U, // VORNq
4062183696U, // VORRd
4062183760U, // VORRq
4088399424U, // VPADALsv16i8
4088923648U, // VPADALsv2i32
4088661504U, // VPADALsv4i16
4088923712U, // VPADALsv4i32
4088661568U, // VPADALsv8i16
4088399360U, // VPADALsv8i8
4088399552U, // VPADALuv16i8
4088923776U, // VPADALuv2i32
4088661632U, // VPADALuv4i16
4088923840U, // VPADALuv4i32
4088661696U, // VPADALuv8i16
4088399488U, // VPADALuv8i8
4088398400U, // VPADDLsv16i8
4088922624U, // VPADDLsv2i32
4088660480U, // VPADDLsv4i16
4088922688U, // VPADDLsv4i32
4088660544U, // VPADDLsv8i16
4088398336U, // VPADDLsv8i8
4088398528U, // VPADDLuv16i8
4088922752U, // VPADDLuv2i32
4088660608U, // VPADDLuv4i16
4088922816U, // VPADDLuv4i32
4088660672U, // VPADDLuv8i16
4088398464U, // VPADDLuv8i8
4076866816U, // VPADDf
4061137680U, // VPADDi16
4062186256U, // VPADDi32
4060089104U, // VPADDi8
4076867328U, // VPMAXf
4061137408U, // VPMAXs16
4062185984U, // VPMAXs32
4060088832U, // VPMAXs8
4077914624U, // VPMAXu16
4078963200U, // VPMAXu32
4076866048U, // VPMAXu8
4078964480U, // VPMINf
4061137424U, // VPMINs16
4062186000U, // VPMINs32
4060088848U, // VPMINs8
4077914640U, // VPMINu16
4078963216U, // VPMINu32
4076866064U, // VPMINu8
4088399680U, // VQABSv16i8
4088923904U, // VQABSv2i32
4088661760U, // VQABSv4i16
4088923968U, // VQABSv4i32
4088661824U, // VQABSv8i16
4088399616U, // VQABSv8i8
4060086352U, // VQADDsv16i8
4063232016U, // VQADDsv1i64
4062183440U, // VQADDsv2i32
4063232080U, // VQADDsv2i64
4061134864U, // VQADDsv4i16
4062183504U, // VQADDsv4i32
4061134928U, // VQADDsv8i16
4060086288U, // VQADDsv8i8
4076863568U, // VQADDuv16i8
4080009232U, // VQADDuv1i64
4078960656U, // VQADDuv2i32
4080009296U, // VQADDuv2i64
4077912080U, // VQADDuv4i16
4078960720U, // VQADDuv4i32
4077912144U, // VQADDuv8i16
4076863504U, // VQADDuv8i8
4070572864U, // VQDMLALslv2i32
4069524288U, // VQDMLALslv4i16
4070574336U, // VQDMLALv2i64
4069525760U, // VQDMLALv4i32
4070573888U, // VQDMLSLslv2i32
4069525312U, // VQDMLSLslv4i16
4070574848U, // VQDMLSLv2i64
4069526272U, // VQDMLSLv4i32
4070575168U, // VQDMULHslv2i32
4069526592U, // VQDMULHslv4i16
4087352384U, // VQDMULHslv4i32
4086303808U, // VQDMULHslv8i16
4062186240U, // VQDMULHv2i32
4061137664U, // VQDMULHv4i16
4062186304U, // VQDMULHv4i32
4061137728U, // VQDMULHv8i16
4070574912U, // VQDMULLslv2i32
4069526336U, // VQDMULLslv4i16
4070575360U, // VQDMULLv2i64
4069526784U, // VQDMULLv4i32
4089053760U, // VQMOVNsuv2i32
4088791616U, // VQMOVNsuv4i16
4088529472U, // VQMOVNsuv8i8
4089053824U, // VQMOVNsv2i32
4088791680U, // VQMOVNsv4i16
4088529536U, // VQMOVNsv8i8
4089053888U, // VQMOVNuv2i32
4088791744U, // VQMOVNuv4i16
4088529600U, // VQMOVNuv8i8
4088399808U, // VQNEGv16i8
4088924032U, // VQNEGv2i32
4088661888U, // VQNEGv4i16
4088924096U, // VQNEGv4i32
4088661952U, // VQNEGv8i16
4088399744U, // VQNEGv8i8
4070575424U, // VQRDMULHslv2i32
4069526848U, // VQRDMULHslv4i16
4087352640U, // VQRDMULHslv4i32
4086304064U, // VQRDMULHslv8i16
4078963456U, // VQRDMULHv2i32
4077914880U, // VQRDMULHv4i16
4078963520U, // VQRDMULHv4i32
4077914944U, // VQRDMULHv8i16
4060087632U, // VQRSHLsv16i8
4063233296U, // VQRSHLsv1i64
4062184720U, // VQRSHLsv2i32
4063233360U, // VQRSHLsv2i64
4061136144U, // VQRSHLsv4i16
4062184784U, // VQRSHLsv4i32
4061136208U, // VQRSHLsv8i16
4060087568U, // VQRSHLsv8i8
4076864848U, // VQRSHLuv16i8
4080010512U, // VQRSHLuv1i64
4078961936U, // VQRSHLuv2i32
4080010576U, // VQRSHLuv2i64
4077913360U, // VQRSHLuv4i16
4078962000U, // VQRSHLuv4i32
4077913424U, // VQRSHLuv8i16
4076864784U, // VQRSHLuv8i8
4070574416U, // VQRSHRNsv2i32
4069525840U, // VQRSHRNsv4i16
4069001552U, // VQRSHRNsv8i8
4087351632U, // VQRSHRNuv2i32
4086303056U, // VQRSHRNuv4i16
4085778768U, // VQRSHRNuv8i8
4087351376U, // VQRSHRUNv2i32
4086302800U, // VQRSHRUNv4i16
4085778512U, // VQRSHRUNv8i8
4069001040U, // VQSHLsiv16i8
4068476816U, // VQSHLsiv1i64
4070573840U, // VQSHLsiv2i32
4068476880U, // VQSHLsiv2i64
4069525264U, // VQSHLsiv4i16
4070573904U, // VQSHLsiv4i32
4069525328U, // VQSHLsiv8i16
4069000976U, // VQSHLsiv8i8
4085778000U, // VQSHLsuv16i8
4085253776U, // VQSHLsuv1i64
4087350800U, // VQSHLsuv2i32
4085253840U, // VQSHLsuv2i64
4086302224U, // VQSHLsuv4i16
4087350864U, // VQSHLsuv4i32
4086302288U, // VQSHLsuv8i16
4085777936U, // VQSHLsuv8i8
4060087376U, // VQSHLsv16i8
4063233040U, // VQSHLsv1i64
4062184464U, // VQSHLsv2i32
4063233104U, // VQSHLsv2i64
4061135888U, // VQSHLsv4i16
4062184528U, // VQSHLsv4i32
4061135952U, // VQSHLsv8i16
4060087312U, // VQSHLsv8i8
4085778256U, // VQSHLuiv16i8
4085254032U, // VQSHLuiv1i64
4087351056U, // VQSHLuiv2i32
4085254096U, // VQSHLuiv2i64
4086302480U, // VQSHLuiv4i16
4087351120U, // VQSHLuiv4i32
4086302544U, // VQSHLuiv8i16
4085778192U, // VQSHLuiv8i8
4076864592U, // VQSHLuv16i8
4080010256U, // VQSHLuv1i64
4078961680U, // VQSHLuv2i32
4080010320U, // VQSHLuv2i64
4077913104U, // VQSHLuv4i16
4078961744U, // VQSHLuv4i32
4077913168U, // VQSHLuv8i16
4076864528U, // VQSHLuv8i8
4070574352U, // VQSHRNsv2i32
4069525776U, // VQSHRNsv4i16
4069001488U, // VQSHRNsv8i8
4087351568U, // VQSHRNuv2i32
4086302992U, // VQSHRNuv4i16
4085778704U, // VQSHRNuv8i8
4087351312U, // VQSHRUNv2i32
4086302736U, // VQSHRUNv4i16
4085778448U, // VQSHRUNv8i8
4060086864U, // VQSUBsv16i8
4063232528U, // VQSUBsv1i64
4062183952U, // VQSUBsv2i32
4063232592U, // VQSUBsv2i64
4061135376U, // VQSUBsv4i16
4062184016U, // VQSUBsv4i32
4061135440U, // VQSUBsv8i16
4060086800U, // VQSUBsv8i8
4076864080U, // VQSUBuv16i8
4080009744U, // VQSUBuv1i64
4078961168U, // VQSUBuv2i32
4080009808U, // VQSUBuv2i64
4077912592U, // VQSUBuv4i16
4078961232U, // VQSUBuv4i32
4077912656U, // VQSUBuv8i16
4076864016U, // VQSUBuv8i8
4087350272U, // VRADDHNv2i32
4086301696U, // VRADDHNv4i16
4085253120U, // VRADDHNv8i8
4089119744U, // VRECPEd
4089120000U, // VRECPEfd
4089120064U, // VRECPEfq
4089119808U, // VRECPEq
4060090128U, // VRECPSfd
4060090192U, // VRECPSfq
4088398080U, // VREV16d8
4088398144U, // VREV16q8
4088660096U, // VREV32d16
4088397952U, // VREV32d8
4088660160U, // VREV32q16
4088398016U, // VREV32q8
4088659968U, // VREV64d16
4088922112U, // VREV64d32
4088397824U, // VREV64d8
4088922112U, // VREV64df
4088660032U, // VREV64q16
4088922176U, // VREV64q32
4088397888U, // VREV64q8
4088922176U, // VREV64qf
4060086592U, // VRHADDsv16i8
4062183680U, // VRHADDsv2i32
4061135104U, // VRHADDsv4i16
4062183744U, // VRHADDsv4i32
4061135168U, // VRHADDsv8i16
4060086528U, // VRHADDsv8i8
4076863808U, // VRHADDuv16i8
4078960896U, // VRHADDuv2i32
4077912320U, // VRHADDuv4i16
4078960960U, // VRHADDuv4i32
4077912384U, // VRHADDuv8i16
4076863744U, // VRHADDuv8i8
4060087616U, // VRSHLsv16i8
4063233280U, // VRSHLsv1i64
4062184704U, // VRSHLsv2i32
4063233344U, // VRSHLsv2i64
4061136128U, // VRSHLsv4i16
4062184768U, // VRSHLsv4i32
4061136192U, // VRSHLsv8i16
4060087552U, // VRSHLsv8i8
4076864832U, // VRSHLuv16i8
4080010496U, // VRSHLuv1i64
4078961920U, // VRSHLuv2i32
4080010560U, // VRSHLuv2i64
4077913344U, // VRSHLuv4i16
4078961984U, // VRSHLuv4i32
4077913408U, // VRSHLuv8i16
4076864768U, // VRSHLuv8i8
4070574160U, // VRSHRNv2i32
4069525584U, // VRSHRNv4i16
4069001296U, // VRSHRNv8i8
4068999760U, // VRSHRsv16i8
4068475536U, // VRSHRsv1i64
4070572560U, // VRSHRsv2i32
4068475600U, // VRSHRsv2i64
4069523984U, // VRSHRsv4i16
4070572624U, // VRSHRsv4i32
4069524048U, // VRSHRsv8i16
4068999696U, // VRSHRsv8i8
4085776976U, // VRSHRuv16i8
4085252752U, // VRSHRuv1i64
4087349776U, // VRSHRuv2i32
4085252816U, // VRSHRuv2i64
4086301200U, // VRSHRuv4i16
4087349840U, // VRSHRuv4i32
4086301264U, // VRSHRuv8i16
4085776912U, // VRSHRuv8i8
4089119872U, // VRSQRTEd
4089120128U, // VRSQRTEfd
4089120192U, // VRSQRTEfq
4089119936U, // VRSQRTEq
4062187280U, // VRSQRTSfd
4062187344U, // VRSQRTSfq
4069000016U, // VRSRAsv16i8
4068475792U, // VRSRAsv1i64
4070572816U, // VRSRAsv2i32
4068475856U, // VRSRAsv2i64
4069524240U, // VRSRAsv4i16
4070572880U, // VRSRAsv4i32
4069524304U, // VRSRAsv8i16
4068999952U, // VRSRAsv8i8
4085777232U, // VRSRAuv16i8
4085253008U, // VRSRAuv1i64
4087350032U, // VRSRAuv2i32
4085253072U, // VRSRAuv2i64
4086301456U, // VRSRAuv4i16
4087350096U, // VRSRAuv4i32
4086301520U, // VRSRAuv8i16
4085777168U, // VRSRAuv8i8
4087350784U, // VRSUBHNv2i32
4086302208U, // VRSUBHNv4i16
4085253632U, // VRSUBHNv8i8
234883888U, // VSETLNi16
234883856U, // VSETLNi32
239078160U, // VSETLNi8
4088791808U, // VSHLLi16
4089053952U, // VSHLLi32
4088529664U, // VSHLLi8
4070574608U, // VSHLLsv2i64
4069526032U, // VSHLLsv4i32
4069001744U, // VSHLLsv8i16
4087351824U, // VSHLLuv2i64
4086303248U, // VSHLLuv4i32
4085778960U, // VSHLLuv8i16
4069000528U, // VSHLiv16i8
4068476304U, // VSHLiv1i64
4070573328U, // VSHLiv2i32
4068476368U, // VSHLiv2i64
4069524752U, // VSHLiv4i16
4070573392U, // VSHLiv4i32
4069524816U, // VSHLiv8i16
4069000464U, // VSHLiv8i8
4060087360U, // VSHLsv16i8
4063233024U, // VSHLsv1i64
4062184448U, // VSHLsv2i32
4063233088U, // VSHLsv2i64
4061135872U, // VSHLsv4i16
4062184512U, // VSHLsv4i32
4061135936U, // VSHLsv8i16
4060087296U, // VSHLsv8i8
4076864576U, // VSHLuv16i8
4080010240U, // VSHLuv1i64
4078961664U, // VSHLuv2i32
4080010304U, // VSHLuv2i64
4077913088U, // VSHLuv4i16
4078961728U, // VSHLuv4i32
4077913152U, // VSHLuv8i16
4076864512U, // VSHLuv8i8
4070574096U, // VSHRNv2i32
4069525520U, // VSHRNv4i16
4069001232U, // VSHRNv8i8
4068999248U, // VSHRsv16i8
4068475024U, // VSHRsv1i64
4070572048U, // VSHRsv2i32
4068475088U, // VSHRsv2i64
4069523472U, // VSHRsv4i16
4070572112U, // VSHRsv4i32
4069523536U, // VSHRsv8i16
4068999184U, // VSHRsv8i8
4085776464U, // VSHRuv16i8
4085252240U, // VSHRuv1i64
4087349264U, // VSHRuv2i32
4085252304U, // VSHRuv2i64
4086300688U, // VSHRuv4i16
4087349328U, // VSHRuv4i32
4086300752U, // VSHRuv8i16
4085776400U, // VSHRuv8i8
247073600U, // VSHTOD
247073344U, // VSHTOS
246942656U, // VSITOD
246942400U, // VSITOS
4085777744U, // VSLIv16i8
4085253520U, // VSLIv1i64
4087350544U, // VSLIv2i32
4085253584U, // VSLIv2i64
4086301968U, // VSLIv4i16
4087350608U, // VSLIv4i32
4086302032U, // VSLIv8i16
4085777680U, // VSLIv8i8
247073728U, // VSLTOD
247073472U, // VSLTOS
246483904U, // VSQRTD
246483648U, // VSQRTS
4068999504U, // VSRAsv16i8
4068475280U, // VSRAsv1i64
4070572304U, // VSRAsv2i32
4068475344U, // VSRAsv2i64
4069523728U, // VSRAsv4i16
4070572368U, // VSRAsv4i32
4069523792U, // VSRAsv8i16
4068999440U, // VSRAsv8i8
4085776720U, // VSRAuv16i8
4085252496U, // VSRAuv1i64
4087349520U, // VSRAuv2i32
4085252560U, // VSRAuv2i64
4086300944U, // VSRAuv4i16
4087349584U, // VSRAuv4i32
4086301008U, // VSRAuv8i16
4085776656U, // VSRAuv8i8
4085777488U, // VSRIv16i8
4085253264U, // VSRIv1i64
4087350288U, // VSRIv2i32
4085253328U, // VSRIv2i64
4086301712U, // VSRIv4i16
4087350352U, // VSRIv4i32
4086301776U, // VSRIv8i16
4085777424U, // VSRIv8i8
4093642560U, // VST1d16
4093641280U, // VST1d16Q
4093642304U, // VST1d16T
4093642624U, // VST1d32
4093641344U, // VST1d32Q
4093642368U, // VST1d32T
4093642688U, // VST1d64
4093642496U, // VST1d8
4093641216U, // VST1d8Q
4093642240U, // VST1d8T
4093642624U, // VST1df
4093643328U, // VST1q16
4093643392U, // VST1q32
4093643456U, // VST1q64
4093643264U, // VST1q8
4093643392U, // VST1qf
4102030592U, // VST2LNd16
4102031616U, // VST2LNd32
4102029568U, // VST2LNd8
4102030624U, // VST2LNq16a
4102030624U, // VST2LNq16b
4102031680U, // VST2LNq32a
4102031680U, // VST2LNq32b
4093642816U, // VST2d16
4093643072U, // VST2d16D
4093642880U, // VST2d32
4093643136U, // VST2d32D
4093643456U, // VST2d64
4093642752U, // VST2d8
4093643008U, // VST2d8D
4093641536U, // VST2q16
4093641600U, // VST2q32
4093641472U, // VST2q8
4102030848U, // VST3LNd16
4102031872U, // VST3LNd32
4102029824U, // VST3LNd8
4102030880U, // VST3LNq16a
4102030880U, // VST3LNq16b
4102031936U, // VST3LNq32a
4102031936U, // VST3LNq32b
4093641792U, // VST3d16
4093641856U, // VST3d32
4093642432U, // VST3d64
4093641728U, // VST3d8
4093642048U, // VST3q16a
4093642048U, // VST3q16b
4093642112U, // VST3q32a
4093642112U, // VST3q32b
4093641984U, // VST3q8a
4093641984U, // VST3q8b
4102031104U, // VST4LNd16
4102032128U, // VST4LNd32
4102030080U, // VST4LNd8
4102031136U, // VST4LNq16a
4102031136U, // VST4LNq16b
4102032192U, // VST4LNq32a
4102032192U, // VST4LNq32b
4093640768U, // VST4d16
4093640832U, // VST4d32
4093641408U, // VST4d64
4093640704U, // VST4d8
4093641024U, // VST4q16a
4093641024U, // VST4q16b
4093641088U, // VST4q32a
4093641088U, // VST4q32b
4093640960U, // VST4q8a
4093640960U, // VST4q8b
201329408U, // VSTMD
201329152U, // VSTMS
218106624U, // VSTRD
209718016U, // VSTRQ
218106368U, // VSTRS
238029632U, // VSUBD
4070573568U, // VSUBHNv2i32
4069524992U, // VSUBHNv4i16
4068476416U, // VSUBHNv8i8
4070572544U, // VSUBLsv2i64
4069523968U, // VSUBLsv4i32
4068475392U, // VSUBLsv8i16
4087349760U, // VSUBLuv2i64
4086301184U, // VSUBLuv4i32
4085252608U, // VSUBLuv8i16
238029376U, // VSUBS
4070572800U, // VSUBWsv2i64
4069524224U, // VSUBWsv4i32
4068475648U, // VSUBWsv8i16
4087350016U, // VSUBWuv2i64
4086301440U, // VSUBWuv4i32
4085252864U, // VSUBWuv8i16
4062186752U, // VSUBfd
4062186752U, // VSUBfd_sfp
4062186816U, // VSUBfq
4076865600U, // VSUBv16i8
4080011264U, // VSUBv1i64
4078962688U, // VSUBv2i32
4080011328U, // VSUBv2i64
4077914112U, // VSUBv4i16
4078962752U, // VSUBv4i32
4077914176U, // VSUBv8i16
4076865536U, // VSUBv8i8
4088528896U, // VSWPd
4088528960U, // VSWPq
4088399872U, // VTBL1
4088400128U, // VTBL2
4088400384U, // VTBL3
4088400640U, // VTBL4
4088399936U, // VTBX1
4088400192U, // VTBX2
4088400448U, // VTBX3
4088400704U, // VTBX4
247335744U, // VTOSHD
247335488U, // VTOSHS
247270208U, // VTOSIRD
247269952U, // VTOSIRS
247270336U, // VTOSIZD
247270080U, // VTOSIZS
247335872U, // VTOSLD
247335616U, // VTOSLS
247401280U, // VTOUHD
247401024U, // VTOUHS
247204672U, // VTOUIRD
247204416U, // VTOUIRS
247204800U, // VTOUIZD
247204544U, // VTOUIZS
247401408U, // VTOULD
247401152U, // VTOULS
4088791168U, // VTRNd16
4089053312U, // VTRNd32
4088529024U, // VTRNd8
4088791232U, // VTRNq16
4089053376U, // VTRNq32
4088529088U, // VTRNq8
4060088400U, // VTSTv16i8
4062185488U, // VTSTv2i32
4061136912U, // VTSTv4i16
4062185552U, // VTSTv4i32
4061136976U, // VTSTv8i16
4060088336U, // VTSTv8i8
247139136U, // VUHTOD
247138880U, // VUHTOS
246942528U, // VUITOD
246942272U, // VUITOS
247139264U, // VULTOD
247139008U, // VULTOS
4088791296U, // VUZPd16
4089053440U, // VUZPd32
4088529152U, // VUZPd8
4088791360U, // VUZPq16
4089053504U, // VUZPq32
4088529216U, // VUZPq8
4088791424U, // VZIPd16
4089053568U, // VZIPd32
4088529280U, // VZIPd8
4088791488U, // VZIPq16
4089053632U, // VZIPq32
4088529344U, // VZIPq8
52428802U, // WFE
52428803U, // WFI
52428801U, // YIELD
4048551936U, // t2ADCSri
3947888640U, // t2ADCSrr
3947888640U, // t2ADCSrs
4047503360U, // t2ADCri
3946840064U, // t2ADCrr
3946840064U, // t2ADCrs
4044357632U, // t2ADDSri
3943694336U, // t2ADDSrr
3943694336U, // t2ADDSrs
4044161024U, // t2ADDrSPi
4060938240U, // t2ADDrSPi12
3943497728U, // t2ADDrSPs
4043309056U, // t2ADDri
4060086272U, // t2ADDri12
3942645760U, // t2ADDrr
3942645760U, // t2ADDrs
4026531840U, // t2ANDri
3925868544U, // t2ANDrr
3925868544U, // t2ANDrs
3931045920U, // t2ASRri
4198559744U, // t2ASRrr
4026568704U, // t2B
4084137984U, // t2BFC
4083154944U, // t2BFI
4028628992U, // t2BICri
3927965696U, // t2BICrr
3927965696U, // t2BICrs
3931049728U, // t2BR_JT
4089479168U, // t2BXJ
4026564608U, // t2Bcc
4088430624U, // t2CLREX
4205899904U, // t2CLZ
4044361472U, // t2CMNzri
3943698176U, // t2CMNzrr
3943698176U, // t2CMNzrs
4054847232U, // t2CMPri
3954183936U, // t2CMPrr
3954183936U, // t2CMPrs
4054847232U, // t2CMPzri
3954183936U, // t2CMPzrr
3954183936U, // t2CMPzrs
4087382016U, // t2CPS
4087382256U, // t2DBG
4088430683U, // t2DMBish
4088430682U, // t2DMBishst
4088430679U, // t2DMBnsh
4088430678U, // t2DMBnshst
4088430675U, // t2DMBosh
4088430674U, // t2DMBoshst
4088430686U, // t2DMBst
4088430667U, // t2DSBish
4088430666U, // t2DSBishst
4088430663U, // t2DSBnsh
4088430662U, // t2DSBnshst
4088430659U, // t2DSBosh
4088430658U, // t2DSBoshst
4088430670U, // t2DSBst
4034920448U, // t2EORri
3934257152U, // t2EORrr
3934257152U, // t2EORrs
4088430703U, // t2ISBsy
48896U, // t2IT
4089417567U, // t2Int_MemBarrierV7
4089417551U, // t2Int_SyncBarrierV7
0U, // t2Int_eh_sjlj_setjmp
3893362688U, // t2LDM
3893362688U, // t2LDM_RET
4161801728U, // t2LDRBT
4161800448U, // t2LDRB_POST
4161801472U, // t2LDRB_PRE
4170186752U, // t2LDRBi12
4161801216U, // t2LDRBi8
4162781184U, // t2LDRBpci
4161798144U, // t2LDRBs
3914334208U, // t2LDRDi8
3898540032U, // t2LDRDpci
3897560832U, // t2LDREX
3905949519U, // t2LDREXB
3905945727U, // t2LDREXD
3905949535U, // t2LDREXH
4163898880U, // t2LDRHT
4163897600U, // t2LDRH_POST
4163898624U, // t2LDRH_PRE
4172283904U, // t2LDRHi12
4163898368U, // t2LDRHi8
4164878336U, // t2LDRHpci
4163895296U, // t2LDRHs
4178578944U, // t2LDRSBT
4178577664U, // t2LDRSB_POST
4178578688U, // t2LDRSB_PRE
4186963968U, // t2LDRSBi12
4178578432U, // t2LDRSBi8
4179558400U, // t2LDRSBpci
4178575360U, // t2LDRSBs
4180676096U, // t2LDRSHT
4180674816U, // t2LDRSH_POST
4180675840U, // t2LDRSH_PRE
4189061120U, // t2LDRSHi12
4180675584U, // t2LDRSHi8
4181655552U, // t2LDRSHpci
4180672512U, // t2LDRSHs
4165996032U, // t2LDRT
4165994752U, // t2LDR_POST
4165995776U, // t2LDR_PRE
4174381056U, // t2LDRi12
4165995520U, // t2LDRi8
4166975488U, // t2LDRpci
0U, // t2LDRpci_pic
4165992448U, // t2LDRs
4061069312U, // t2LEApcrel
4061069312U, // t2LEApcrelJT
3931045888U, // t2LSLri
4194365440U, // t2LSLrr
3931045904U, // t2LSRri
4196462592U, // t2LSRrr
4211081216U, // t2MLA
4211081232U, // t2MLS
3931045920U, // t2MOVCCasr
4031709184U, // t2MOVCCi
3931045888U, // t2MOVCClsl
3931045904U, // t2MOVCClsr
3931045888U, // t2MOVCCr
3931045936U, // t2MOVCCror
4072669184U, // t2MOVTi16
4031709184U, // t2MOVi
4064280576U, // t2MOVi16
0U, // t2MOVi32imm
3931045888U, // t2MOVr
3931045936U, // t2MOVrx
3932094560U, // t2MOVsra_flag
3932094544U, // t2MOVsrl_flag
4091576320U, // t2MRS
4092624896U, // t2MRSsys
4085284864U, // t2MSR
4086333440U, // t2MSRsys
4211142656U, // t2MUL
4033806336U, // t2MVNi
3933143040U, // t2MVNr
3933143040U, // t2MVNs
4087382016U, // t2NOP
4032823296U, // t2ORNri
3932160000U, // t2ORNrr
3932160000U, // t2ORNrs
4030726144U, // t2ORRri
3930062848U, // t2ORRrr
3930062848U, // t2ORRrs
3938451456U, // t2PKHBT
3938451488U, // t2PKHTB
4172345344U, // t2PLDWi12
4163959808U, // t2PLDWi8
4164939776U, // t2PLDWpci
4163956736U, // t2PLDWr
4163956736U, // t2PLDWs
4170248192U, // t2PLDi12
4161862656U, // t2PLDi8
4162842624U, // t2PLDpci
4161859584U, // t2PLDr
4161859584U, // t2PLDs
4187025408U, // t2PLIi12
4178639872U, // t2PLIi8
4179619840U, // t2PLIpci
4178636800U, // t2PLIr
4178636800U, // t2PLIs
4202754176U, // t2QADD
4203802640U, // t2QADD16
4202754064U, // t2QADD8
4204851216U, // t2QASX
4202754192U, // t2QDADD
4202754224U, // t2QDSUB
4209045520U, // t2QSAX
4202754208U, // t2QSUB
4207996944U, // t2QSUB16
4206948368U, // t2QSUB8
4203802784U, // t2RBIT
4203802752U, // t2REV
4203802768U, // t2REV16
4203802800U, // t2REVSH
3893362688U, // t2RFEDB
3895459840U, // t2RFEDBW
3918528512U, // t2RFEIA
3920625664U, // t2RFEIAW
3931045936U, // t2RORri
4200656896U, // t2RORrr
4056940544U, // t2RSBSri
3956277248U, // t2RSBSrs
4055891968U, // t2RSBri
3955228672U, // t2RSBrs
4203802624U, // t2SADD16
4202754048U, // t2SADD8
4204851200U, // t2SASX
4050649088U, // t2SBCSri
3949985792U, // t2SBCSrr
3949985792U, // t2SBCSrs
4049600512U, // t2SBCri
3948937216U, // t2SBCrr
3948937216U, // t2SBCrs
4081057792U, // t2SBFX
4220580080U, // t2SDIV
4204851328U, // t2SEL
4087382020U, // t2SEV
4203802656U, // t2SHADD16
4202754080U, // t2SHADD8
4204851232U, // t2SHASX
4209045536U, // t2SHSAX
4207996960U, // t2SHSUB16
4206948384U, // t2SHSUB8
4159733760U, // t2SMC
4212129792U, // t2SMLABB
4212129808U, // t2SMLABT
4213178368U, // t2SMLAD
4213178384U, // t2SMLADX
4223664128U, // t2SMLAL
4223664256U, // t2SMLALBB
4223664272U, // t2SMLALBT
4223664320U, // t2SMLALD
4223664336U, // t2SMLALDX
4223664288U, // t2SMLALTB
4223664304U, // t2SMLALTT
4212129824U, // t2SMLATB
4212129840U, // t2SMLATT
4214226944U, // t2SMLAWB
4214226960U, // t2SMLAWT
4215275520U, // t2SMLSD
4215275536U, // t2SMLSDX
4224712896U, // t2SMLSLD
4224712912U, // t2SMLSLDX
4216324096U, // t2SMMLA
4216324112U, // t2SMMLAR
4217372672U, // t2SMMLS
4217372688U, // t2SMMLSR
4216385536U, // t2SMMUL
4216385552U, // t2SMMULR
4213239808U, // t2SMUAD
4213239824U, // t2SMUADX
4212191232U, // t2SMULBB
4212191248U, // t2SMULBT
4219469824U, // t2SMULL
4212191264U, // t2SMULTB
4212191280U, // t2SMULTT
4214288384U, // t2SMULWB
4214288400U, // t2SMULWT
4215336960U, // t2SMUSD
4215336976U, // t2SMUSDX
3892314112U, // t2SRSDB
3894411264U, // t2SRSDBW
3917479936U, // t2SRSIA
3919577088U, // t2SRSIAW
4078960640U, // t2SSAT16
4078960640U, // t2SSATasr
4076863488U, // t2SSATlsl
4209045504U, // t2SSAX
4207996928U, // t2SSUB16
4206948352U, // t2SSUB8
3892314112U, // t2STM
4160753152U, // t2STRBT
4160751872U, // t2STRB_POST
4160752896U, // t2STRB_PRE
4169138176U, // t2STRBi12
4160752640U, // t2STRBi8
4160749568U, // t2STRBs
3913285632U, // t2STRDi8
3896508416U, // t2STREX
3904900928U, // t2STREXB
3904897136U, // t2STREXD
3904900944U, // t2STREXH
4162850304U, // t2STRHT
4162849024U, // t2STRH_POST
4162850048U, // t2STRH_PRE
4171235328U, // t2STRHi12
4162849792U, // t2STRHi8
4162846720U, // t2STRHs
4164947456U, // t2STRT
4164946176U, // t2STR_POST
4164947200U, // t2STR_PRE
4173332480U, // t2STRi12
4164946944U, // t2STRi8
4164943872U, // t2STRs
4054843392U, // t2SUBSri
3954180096U, // t2SUBSrr
3954180096U, // t2SUBSrs
4054646784U, // t2SUBrSPi
4071424000U, // t2SUBrSPi12
0U, // t2SUBrSPi12_
0U, // t2SUBrSPi_
3953983488U, // t2SUBrSPs
0U, // t2SUBrSPs_
4053794816U, // t2SUBri
4070572032U, // t2SUBri12
3953131520U, // t2SUBrr
3953131520U, // t2SUBrs
4196462720U, // t2SXTAB16rr
4196462720U, // t2SXTAB16rr_rot
4198559872U, // t2SXTABrr
4198559872U, // t2SXTABrr_rot
4194365568U, // t2SXTAHrr
4194365568U, // t2SXTAHrr_rot
4197445760U, // t2SXTB16r
4197445760U, // t2SXTB16r_rot
4199542912U, // t2SXTBr
4199542912U, // t2SXTBr_rot
4195348608U, // t2SXTHr
4195348608U, // t2SXTHr_rot
3906990080U, // t2TBB
3906007040U, // t2TBBgen
3906990096U, // t2TBH
3906007056U, // t2TBHgen
4035972864U, // t2TEQri
3935309568U, // t2TEQrr
3935309568U, // t2TEQrs
4026585088U, // t2TPsoft
4027584256U, // t2TSTri
3926920960U, // t2TSTrr
3926920960U, // t2TSTrs
4203802688U, // t2UADD16
4202754112U, // t2UADD8
4204851264U, // t2UASX
4089446400U, // t2UBFX
4222677232U, // t2UDIV
4203802720U, // t2UHADD16
4202754144U, // t2UHADD8
4204851296U, // t2UHASX
4209045600U, // t2UHSAX
4207997024U, // t2UHSUB16
4206948448U, // t2UHSUB8
4225761376U, // t2UMAAL
4225761280U, // t2UMLAL
4221566976U, // t2UMULL
4203802704U, // t2UQADD16
4202754128U, // t2UQADD8
4204851280U, // t2UQASX
4209045584U, // t2UQSAX
4207997008U, // t2UQSUB16
4206948432U, // t2UQSUB8
4218482688U, // t2USAD8
4218421248U, // t2USADA8
4087349248U, // t2USAT16
4087349248U, // t2USATasr
4085252096U, // t2USATlsl
4209045568U, // t2USAX
4207996992U, // t2USUB16
4206948416U, // t2USUB8
4197511296U, // t2UXTAB16rr
4197511296U, // t2UXTAB16rr_rot
4199608448U, // t2UXTABrr
4199608448U, // t2UXTABrr_rot
4195414144U, // t2UXTAHrr
4195414144U, // t2UXTAHrr_rot
4198494336U, // t2UXTB16r
4198494336U, // t2UXTB16r_rot
4200591488U, // t2UXTBr
4200591488U, // t2UXTBr_rot
4196397184U, // t2UXTHr
4196397184U, // t2UXTHr_rot
4087382018U, // t2WFE
4087382019U, // t2WFI
4087382017U, // t2YIELD
16704U, // tADC
17408U, // tADDhirr
7168U, // tADDi3
12288U, // tADDi8
40960U, // tADDrPCi
17512U, // tADDrSP
43008U, // tADDrSPi
6144U, // tADDrr
45056U, // tADDspi
17541U, // tADDspr
0U, // tADDspr_
0U, // tADJCALLSTACKDOWN
0U, // tADJCALLSTACKUP
16384U, // tAND
0U, // tANDsp
4096U, // tASRri
16640U, // tASRrr
57344U, // tB
17280U, // tBIC
48640U, // tBKPT
4026585088U, // tBL
4026580992U, // tBLXi
4026580992U, // tBLXi_r9
18304U, // tBLXr
18304U, // tBLXr_r9
4026585088U, // tBLr9
18055U, // tBRIND
18055U, // tBR_JTr
0U, // tBX
18288U, // tBX_RET
18176U, // tBX_RET_vararg
0U, // tBXr9
53248U, // tBcc
4026585088U, // tBfar
47360U, // tCBNZ
45312U, // tCBZ
17088U, // tCMNz
17664U, // tCMPhir
10240U, // tCMPi8
17024U, // tCMPr
17664U, // tCMPzhir
10240U, // tCMPzi8
17024U, // tCMPzr
46688U, // tCPS
16448U, // tEOR
0U, // tInt_eh_sjlj_setjmp
51200U, // tLDM
22528U, // tLDR
23552U, // tLDRB
30720U, // tLDRBi
23040U, // tLDRH
34816U, // tLDRHi
22016U, // tLDRSB
24064U, // tLDRSH
38912U, // tLDRcp
26624U, // tLDRi
18432U, // tLDRpci
0U, // tLDRpci_pic
38912U, // tLDRspi
40960U, // tLEApcrel
40960U, // tLEApcrelJT
0U, // tLSLri
16512U, // tLSLrr
2048U, // tLSRri
16576U, // tLSRrr
8192U, // tMOVCCi
17920U, // tMOVCCr
0U, // tMOVCCr_pseudo
0U, // tMOVSr
17920U, // tMOVgpr2gpr
17920U, // tMOVgpr2tgpr
8192U, // tMOVi8
17920U, // tMOVr
17920U, // tMOVtgpr2gpr
17216U, // tMUL
17344U, // tMVN
48896U, // tNOP
17152U, // tORR
17528U, // tPICADD
48128U, // tPOP
48128U, // tPOP_RET
46080U, // tPUSH
47616U, // tREV
47680U, // tREV16
47808U, // tREVSH
16832U, // tROR
16960U, // tRSB
38912U, // tRestore
16768U, // tSBC
46664U, // tSETENDBE
46656U, // tSETENDLE
48960U, // tSEV
49152U, // tSTM
20480U, // tSTR
21504U, // tSTRB
28672U, // tSTRBi
20992U, // tSTRH
32768U, // tSTRHi
24576U, // tSTRi
36864U, // tSTRspi
7680U, // tSUBi3
14336U, // tSUBi8
6656U, // tSUBrr
45184U, // tSUBspi
0U, // tSUBspi_
57088U, // tSVC
45632U, // tSXTB
45568U, // tSXTH
36864U, // tSpill
4026585088U, // tTPsoft
56832U, // tTRAP
16896U, // tTST
45760U, // tUXTB
45696U, // tUXTH
48928U, // tWFE
48944U, // tWFI
48912U, // tYIELD
0U
};
const unsigned opcode = MI.getOpcode();
unsigned Value = InstBits[opcode];
unsigned op = 0;
op = op; // suppress warning
switch (opcode) {
case ARM::ADCSSri:
case ARM::ADCSSrr:
case ARM::ADCSSrs:
case ARM::ADCri:
case ARM::ADCrr:
case ARM::ADCrs:
case ARM::ADDSri:
case ARM::ADDSrr:
case ARM::ADDSrs:
case ARM::ADDri:
case ARM::ADDrr:
case ARM::ADDrs:
case ARM::ADJCALLSTACKDOWN:
case ARM::ADJCALLSTACKUP:
case ARM::ANDri:
case ARM::ANDrr:
case ARM::ANDrs:
case ARM::ATOMIC_CMP_SWAP_I16:
case ARM::ATOMIC_CMP_SWAP_I32:
case ARM::ATOMIC_CMP_SWAP_I8:
case ARM::ATOMIC_LOAD_ADD_I16:
case ARM::ATOMIC_LOAD_ADD_I32:
case ARM::ATOMIC_LOAD_ADD_I8:
case ARM::ATOMIC_LOAD_AND_I16:
case ARM::ATOMIC_LOAD_AND_I32:
case ARM::ATOMIC_LOAD_AND_I8:
case ARM::ATOMIC_LOAD_NAND_I16:
case ARM::ATOMIC_LOAD_NAND_I32:
case ARM::ATOMIC_LOAD_NAND_I8:
case ARM::ATOMIC_LOAD_OR_I16:
case ARM::ATOMIC_LOAD_OR_I32:
case ARM::ATOMIC_LOAD_OR_I8:
case ARM::ATOMIC_LOAD_SUB_I16:
case ARM::ATOMIC_LOAD_SUB_I32:
case ARM::ATOMIC_LOAD_SUB_I8:
case ARM::ATOMIC_LOAD_XOR_I16:
case ARM::ATOMIC_LOAD_XOR_I32:
case ARM::ATOMIC_LOAD_XOR_I8:
case ARM::ATOMIC_SWAP_I16:
case ARM::ATOMIC_SWAP_I32:
case ARM::ATOMIC_SWAP_I8:
case ARM::B:
case ARM::BFC:
case ARM::BFI:
case ARM::BICri:
case ARM::BICrr:
case ARM::BICrs:
case ARM::BKPT:
case ARM::BL:
case ARM::BLX:
case ARM::BLXr9:
case ARM::BL_pred:
case ARM::BLr9:
case ARM::BLr9_pred:
case ARM::BMOVPCRX:
case ARM::BMOVPCRXr9:
case ARM::BRIND:
case ARM::BR_JTadd:
case ARM::BR_JTm:
case ARM::BR_JTr:
case ARM::BX:
case ARM::BXJ:
case ARM::BX_RET:
case ARM::BXr9:
case ARM::Bcc:
case ARM::CDP:
case ARM::CDP2:
case ARM::CLREX:
case ARM::CLZ:
case ARM::CMNzri:
case ARM::CMNzrr:
case ARM::CMNzrs:
case ARM::CMPri:
case ARM::CMPrr:
case ARM::CMPrs:
case ARM::CMPzri:
case ARM::CMPzrr:
case ARM::CMPzrs:
case ARM::CONSTPOOL_ENTRY:
case ARM::CPS:
case ARM::DBG:
case ARM::DMBish:
case ARM::DMBishst:
case ARM::DMBnsh:
case ARM::DMBnshst:
case ARM::DMBosh:
case ARM::DMBoshst:
case ARM::DMBst:
case ARM::DSBish:
case ARM::DSBishst:
case ARM::DSBnsh:
case ARM::DSBnshst:
case ARM::DSBosh:
case ARM::DSBoshst:
case ARM::DSBst:
case ARM::EORri:
case ARM::EORrr:
case ARM::EORrs:
case ARM::FCONSTD:
case ARM::FCONSTS:
case ARM::FMSTAT:
case ARM::ISBsy:
case ARM::Int_MemBarrierV6:
case ARM::Int_MemBarrierV7:
case ARM::Int_SyncBarrierV6:
case ARM::Int_SyncBarrierV7:
case ARM::Int_eh_sjlj_setjmp:
case ARM::LDC2L_OFFSET:
case ARM::LDC2L_OPTION:
case ARM::LDC2L_POST:
case ARM::LDC2L_PRE:
case ARM::LDC2_OFFSET:
case ARM::LDC2_OPTION:
case ARM::LDC2_POST:
case ARM::LDC2_PRE:
case ARM::LDCL_OFFSET:
case ARM::LDCL_OPTION:
case ARM::LDCL_POST:
case ARM::LDCL_PRE:
case ARM::LDC_OFFSET:
case ARM::LDC_OPTION:
case ARM::LDC_POST:
case ARM::LDC_PRE:
case ARM::LDM:
case ARM::LDM_RET:
case ARM::LDR:
case ARM::LDRB:
case ARM::LDRBT:
case ARM::LDRB_POST:
case ARM::LDRB_PRE:
case ARM::LDRD:
case ARM::LDRD_POST:
case ARM::LDRD_PRE:
case ARM::LDREX:
case ARM::LDREXB:
case ARM::LDREXD:
case ARM::LDREXH:
case ARM::LDRH:
case ARM::LDRHT:
case ARM::LDRH_POST:
case ARM::LDRH_PRE:
case ARM::LDRSB:
case ARM::LDRSBT:
case ARM::LDRSB_POST:
case ARM::LDRSB_PRE:
case ARM::LDRSH:
case ARM::LDRSHT:
case ARM::LDRSH_POST:
case ARM::LDRSH_PRE:
case ARM::LDRT:
case ARM::LDR_POST:
case ARM::LDR_PRE:
case ARM::LDRcp:
case ARM::LEApcrel:
case ARM::LEApcrelJT:
case ARM::MCR:
case ARM::MCR2:
case ARM::MCRR:
case ARM::MCRR2:
case ARM::MLA:
case ARM::MLS:
case ARM::MOVCCi:
case ARM::MOVCCr:
case ARM::MOVCCs:
case ARM::MOVPCLR:
case ARM::MOVPCRX:
case ARM::MOVTi16:
case ARM::MOVi:
case ARM::MOVi16:
case ARM::MOVi2pieces:
case ARM::MOVi32imm:
case ARM::MOVr:
case ARM::MOVrx:
case ARM::MOVs:
case ARM::MOVsra_flag:
case ARM::MOVsrl_flag:
case ARM::MRC:
case ARM::MRC2:
case ARM::MRRC:
case ARM::MRRC2:
case ARM::MRS:
case ARM::MRSsys:
case ARM::MSR:
case ARM::MSRi:
case ARM::MSRsys:
case ARM::MSRsysi:
case ARM::MUL:
case ARM::MVNi:
case ARM::MVNr:
case ARM::MVNs:
case ARM::NOP:
case ARM::ORRri:
case ARM::ORRrr:
case ARM::ORRrs:
case ARM::PICADD:
case ARM::PICLDR:
case ARM::PICLDRB:
case ARM::PICLDRH:
case ARM::PICLDRSB:
case ARM::PICLDRSH:
case ARM::PICSTR:
case ARM::PICSTRB:
case ARM::PICSTRH:
case ARM::PKHBT:
case ARM::PKHTB:
case ARM::PLDWi:
case ARM::PLDWr:
case ARM::PLDi:
case ARM::PLDr:
case ARM::PLIi:
case ARM::PLIr:
case ARM::QADD:
case ARM::QADD16:
case ARM::QADD8:
case ARM::QASX:
case ARM::QDADD:
case ARM::QDSUB:
case ARM::QSAX:
case ARM::QSUB:
case ARM::QSUB16:
case ARM::QSUB8:
case ARM::RBIT:
case ARM::REV:
case ARM::REV16:
case ARM::REVSH:
case ARM::RFE:
case ARM::RFEW:
case ARM::RSBSri:
case ARM::RSBSrs:
case ARM::RSBri:
case ARM::RSBrs:
case ARM::RSCSri:
case ARM::RSCSrs:
case ARM::RSCri:
case ARM::RSCrs:
case ARM::SADD16:
case ARM::SADD8:
case ARM::SASX:
case ARM::SBCSSri:
case ARM::SBCSSrr:
case ARM::SBCSSrs:
case ARM::SBCri:
case ARM::SBCrr:
case ARM::SBCrs:
case ARM::SBFX:
case ARM::SEL:
case ARM::SETENDBE:
case ARM::SETENDLE:
case ARM::SEV:
case ARM::SHADD16:
case ARM::SHADD8:
case ARM::SHASX:
case ARM::SHSAX:
case ARM::SHSUB16:
case ARM::SHSUB8:
case ARM::SMC:
case ARM::SMLABB:
case ARM::SMLABT:
case ARM::SMLAD:
case ARM::SMLADX:
case ARM::SMLAL:
case ARM::SMLALBB:
case ARM::SMLALBT:
case ARM::SMLALD:
case ARM::SMLALDX:
case ARM::SMLALTB:
case ARM::SMLALTT:
case ARM::SMLATB:
case ARM::SMLATT:
case ARM::SMLAWB:
case ARM::SMLAWT:
case ARM::SMLSD:
case ARM::SMLSDX:
case ARM::SMLSLD:
case ARM::SMLSLDX:
case ARM::SMMLA:
case ARM::SMMLAR:
case ARM::SMMLS:
case ARM::SMMLSR:
case ARM::SMMUL:
case ARM::SMMULR:
case ARM::SMUAD:
case ARM::SMUADX:
case ARM::SMULBB:
case ARM::SMULBT:
case ARM::SMULL:
case ARM::SMULTB:
case ARM::SMULTT:
case ARM::SMULWB:
case ARM::SMULWT:
case ARM::SMUSD:
case ARM::SMUSDX:
case ARM::SRS:
case ARM::SRSW:
case ARM::SSAT16:
case ARM::SSATasr:
case ARM::SSATlsl:
case ARM::SSAX:
case ARM::SSUB16:
case ARM::SSUB8:
case ARM::STC2L_OFFSET:
case ARM::STC2L_OPTION:
case ARM::STC2L_POST:
case ARM::STC2L_PRE:
case ARM::STC2_OFFSET:
case ARM::STC2_OPTION:
case ARM::STC2_POST:
case ARM::STC2_PRE:
case ARM::STCL_OFFSET:
case ARM::STCL_OPTION:
case ARM::STCL_POST:
case ARM::STCL_PRE:
case ARM::STC_OFFSET:
case ARM::STC_OPTION:
case ARM::STC_POST:
case ARM::STC_PRE:
case ARM::STM:
case ARM::STR:
case ARM::STRB:
case ARM::STRBT:
case ARM::STRB_POST:
case ARM::STRB_PRE:
case ARM::STRD:
case ARM::STRD_POST:
case ARM::STRD_PRE:
case ARM::STREX:
case ARM::STREXB:
case ARM::STREXD:
case ARM::STREXH:
case ARM::STRH:
case ARM::STRHT:
case ARM::STRH_POST:
case ARM::STRH_PRE:
case ARM::STRT:
case ARM::STR_POST:
case ARM::STR_PRE:
case ARM::SUBSri:
case ARM::SUBSrr:
case ARM::SUBSrs:
case ARM::SUBri:
case ARM::SUBrr:
case ARM::SUBrs:
case ARM::SVC:
case ARM::SWP:
case ARM::SWPB:
case ARM::SXTAB16rr:
case ARM::SXTAB16rr_rot:
case ARM::SXTABrr:
case ARM::SXTABrr_rot:
case ARM::SXTAHrr:
case ARM::SXTAHrr_rot:
case ARM::SXTB16r:
case ARM::SXTB16r_rot:
case ARM::SXTBr:
case ARM::SXTBr_rot:
case ARM::SXTHr:
case ARM::SXTHr_rot:
case ARM::TEQri:
case ARM::TEQrr:
case ARM::TEQrs:
case ARM::TPsoft:
case ARM::TRAP:
case ARM::TSTri:
case ARM::TSTrr:
case ARM::TSTrs:
case ARM::UADD16:
case ARM::UADD8:
case ARM::UASX:
case ARM::UBFX:
case ARM::UHADD16:
case ARM::UHADD8:
case ARM::UHASX:
case ARM::UHSAX:
case ARM::UHSUB16:
case ARM::UHSUB8:
case ARM::UMAAL:
case ARM::UMLAL:
case ARM::UMULL:
case ARM::UQADD16:
case ARM::UQADD8:
case ARM::UQASX:
case ARM::UQSAX:
case ARM::UQSUB16:
case ARM::UQSUB8:
case ARM::USAD8:
case ARM::USADA8:
case ARM::USAT16:
case ARM::USATasr:
case ARM::USATlsl:
case ARM::USAX:
case ARM::USUB16:
case ARM::USUB8:
case ARM::UXTAB16rr:
case ARM::UXTAB16rr_rot:
case ARM::UXTABrr:
case ARM::UXTABrr_rot:
case ARM::UXTAHrr:
case ARM::UXTAHrr_rot:
case ARM::UXTB16r:
case ARM::UXTB16r_rot:
case ARM::UXTBr:
case ARM::UXTBr_rot:
case ARM::UXTHr:
case ARM::UXTHr_rot:
case ARM::VABALsv2i64:
case ARM::VABALsv4i32:
case ARM::VABALsv8i16:
case ARM::VABALuv2i64:
case ARM::VABALuv4i32:
case ARM::VABALuv8i16:
case ARM::VABAsv16i8:
case ARM::VABAsv2i32:
case ARM::VABAsv4i16:
case ARM::VABAsv4i32:
case ARM::VABAsv8i16:
case ARM::VABAsv8i8:
case ARM::VABAuv16i8:
case ARM::VABAuv2i32:
case ARM::VABAuv4i16:
case ARM::VABAuv4i32:
case ARM::VABAuv8i16:
case ARM::VABAuv8i8:
case ARM::VABDLsv2i64:
case ARM::VABDLsv4i32:
case ARM::VABDLsv8i16:
case ARM::VABDLuv2i64:
case ARM::VABDLuv4i32:
case ARM::VABDLuv8i16:
case ARM::VABDfd:
case ARM::VABDfq:
case ARM::VABDsv16i8:
case ARM::VABDsv2i32:
case ARM::VABDsv4i16:
case ARM::VABDsv4i32:
case ARM::VABDsv8i16:
case ARM::VABDsv8i8:
case ARM::VABDuv16i8:
case ARM::VABDuv2i32:
case ARM::VABDuv4i16:
case ARM::VABDuv4i32:
case ARM::VABDuv8i16:
case ARM::VABDuv8i8:
case ARM::VABSD:
case ARM::VABSS:
case ARM::VABSfd:
case ARM::VABSfd_sfp:
case ARM::VABSfq:
case ARM::VABSv16i8:
case ARM::VABSv2i32:
case ARM::VABSv4i16:
case ARM::VABSv4i32:
case ARM::VABSv8i16:
case ARM::VABSv8i8:
case ARM::VACGEd:
case ARM::VACGEq:
case ARM::VACGTd:
case ARM::VACGTq:
case ARM::VADDD:
case ARM::VADDHNv2i32:
case ARM::VADDHNv4i16:
case ARM::VADDHNv8i8:
case ARM::VADDLsv2i64:
case ARM::VADDLsv4i32:
case ARM::VADDLsv8i16:
case ARM::VADDLuv2i64:
case ARM::VADDLuv4i32:
case ARM::VADDLuv8i16:
case ARM::VADDS:
case ARM::VADDWsv2i64:
case ARM::VADDWsv4i32:
case ARM::VADDWsv8i16:
case ARM::VADDWuv2i64:
case ARM::VADDWuv4i32:
case ARM::VADDWuv8i16:
case ARM::VADDfd:
case ARM::VADDfd_sfp:
case ARM::VADDfq:
case ARM::VADDv16i8:
case ARM::VADDv1i64:
case ARM::VADDv2i32:
case ARM::VADDv2i64:
case ARM::VADDv4i16:
case ARM::VADDv4i32:
case ARM::VADDv8i16:
case ARM::VADDv8i8:
case ARM::VANDd:
case ARM::VANDq:
case ARM::VBICd:
case ARM::VBICq:
case ARM::VBIFd:
case ARM::VBIFq:
case ARM::VBITd:
case ARM::VBITq:
case ARM::VBSLd:
case ARM::VBSLq:
case ARM::VCEQfd:
case ARM::VCEQfq:
case ARM::VCEQv16i8:
case ARM::VCEQv2i32:
case ARM::VCEQv4i16:
case ARM::VCEQv4i32:
case ARM::VCEQv8i16:
case ARM::VCEQv8i8:
case ARM::VCEQzv16i8:
case ARM::VCEQzv2f32:
case ARM::VCEQzv2i32:
case ARM::VCEQzv4f32:
case ARM::VCEQzv4i16:
case ARM::VCEQzv4i32:
case ARM::VCEQzv8i16:
case ARM::VCEQzv8i8:
case ARM::VCGEfd:
case ARM::VCGEfq:
case ARM::VCGEsv16i8:
case ARM::VCGEsv2i32:
case ARM::VCGEsv4i16:
case ARM::VCGEsv4i32:
case ARM::VCGEsv8i16:
case ARM::VCGEsv8i8:
case ARM::VCGEuv16i8:
case ARM::VCGEuv2i32:
case ARM::VCGEuv4i16:
case ARM::VCGEuv4i32:
case ARM::VCGEuv8i16:
case ARM::VCGEuv8i8:
case ARM::VCGEzv16i8:
case ARM::VCGEzv2f32:
case ARM::VCGEzv2i32:
case ARM::VCGEzv4f32:
case ARM::VCGEzv4i16:
case ARM::VCGEzv4i32:
case ARM::VCGEzv8i16:
case ARM::VCGEzv8i8:
case ARM::VCGTfd:
case ARM::VCGTfq:
case ARM::VCGTsv16i8:
case ARM::VCGTsv2i32:
case ARM::VCGTsv4i16:
case ARM::VCGTsv4i32:
case ARM::VCGTsv8i16:
case ARM::VCGTsv8i8:
case ARM::VCGTuv16i8:
case ARM::VCGTuv2i32:
case ARM::VCGTuv4i16:
case ARM::VCGTuv4i32:
case ARM::VCGTuv8i16:
case ARM::VCGTuv8i8:
case ARM::VCGTzv16i8:
case ARM::VCGTzv2f32:
case ARM::VCGTzv2i32:
case ARM::VCGTzv4f32:
case ARM::VCGTzv4i16:
case ARM::VCGTzv4i32:
case ARM::VCGTzv8i16:
case ARM::VCGTzv8i8:
case ARM::VCLEzv16i8:
case ARM::VCLEzv2f32:
case ARM::VCLEzv2i32:
case ARM::VCLEzv4f32:
case ARM::VCLEzv4i16:
case ARM::VCLEzv4i32:
case ARM::VCLEzv8i16:
case ARM::VCLEzv8i8:
case ARM::VCLSv16i8:
case ARM::VCLSv2i32:
case ARM::VCLSv4i16:
case ARM::VCLSv4i32:
case ARM::VCLSv8i16:
case ARM::VCLSv8i8:
case ARM::VCLTzv16i8:
case ARM::VCLTzv2f32:
case ARM::VCLTzv2i32:
case ARM::VCLTzv4f32:
case ARM::VCLTzv4i16:
case ARM::VCLTzv4i32:
case ARM::VCLTzv8i16:
case ARM::VCLTzv8i8:
case ARM::VCLZv16i8:
case ARM::VCLZv2i32:
case ARM::VCLZv4i16:
case ARM::VCLZv4i32:
case ARM::VCLZv8i16:
case ARM::VCLZv8i8:
case ARM::VCMPD:
case ARM::VCMPED:
case ARM::VCMPES:
case ARM::VCMPEZD:
case ARM::VCMPEZS:
case ARM::VCMPS:
case ARM::VCMPZD:
case ARM::VCMPZS:
case ARM::VCNTd:
case ARM::VCNTq:
case ARM::VCVTBHS:
case ARM::VCVTBSH:
case ARM::VCVTDS:
case ARM::VCVTSD:
case ARM::VCVTTHS:
case ARM::VCVTTSH:
case ARM::VCVTf2sd:
case ARM::VCVTf2sd_sfp:
case ARM::VCVTf2sq:
case ARM::VCVTf2ud:
case ARM::VCVTf2ud_sfp:
case ARM::VCVTf2uq:
case ARM::VCVTf2xsd:
case ARM::VCVTf2xsq:
case ARM::VCVTf2xud:
case ARM::VCVTf2xuq:
case ARM::VCVTs2fd:
case ARM::VCVTs2fd_sfp:
case ARM::VCVTs2fq:
case ARM::VCVTu2fd:
case ARM::VCVTu2fd_sfp:
case ARM::VCVTu2fq:
case ARM::VCVTxs2fd:
case ARM::VCVTxs2fq:
case ARM::VCVTxu2fd:
case ARM::VCVTxu2fq:
case ARM::VDIVD:
case ARM::VDIVS:
case ARM::VDUP16d:
case ARM::VDUP16q:
case ARM::VDUP32d:
case ARM::VDUP32q:
case ARM::VDUP8d:
case ARM::VDUP8q:
case ARM::VDUPLN16d:
case ARM::VDUPLN16q:
case ARM::VDUPLN32d:
case ARM::VDUPLN32q:
case ARM::VDUPLN8d:
case ARM::VDUPLN8q:
case ARM::VDUPLNfd:
case ARM::VDUPLNfq:
case ARM::VDUPfd:
case ARM::VDUPfdf:
case ARM::VDUPfq:
case ARM::VDUPfqf:
case ARM::VEORd:
case ARM::VEORq:
case ARM::VEXTd16:
case ARM::VEXTd32:
case ARM::VEXTd8:
case ARM::VEXTdf:
case ARM::VEXTq16:
case ARM::VEXTq32:
case ARM::VEXTq8:
case ARM::VEXTqf:
case ARM::VGETLNi32:
case ARM::VGETLNs16:
case ARM::VGETLNs8:
case ARM::VGETLNu16:
case ARM::VGETLNu8:
case ARM::VHADDsv16i8:
case ARM::VHADDsv2i32:
case ARM::VHADDsv4i16:
case ARM::VHADDsv4i32:
case ARM::VHADDsv8i16:
case ARM::VHADDsv8i8:
case ARM::VHADDuv16i8:
case ARM::VHADDuv2i32:
case ARM::VHADDuv4i16:
case ARM::VHADDuv4i32:
case ARM::VHADDuv8i16:
case ARM::VHADDuv8i8:
case ARM::VHSUBsv16i8:
case ARM::VHSUBsv2i32:
case ARM::VHSUBsv4i16:
case ARM::VHSUBsv4i32:
case ARM::VHSUBsv8i16:
case ARM::VHSUBsv8i8:
case ARM::VHSUBuv16i8:
case ARM::VHSUBuv2i32:
case ARM::VHSUBuv4i16:
case ARM::VHSUBuv4i32:
case ARM::VHSUBuv8i16:
case ARM::VHSUBuv8i8:
case ARM::VLD1d16:
case ARM::VLD1d16Q:
case ARM::VLD1d16T:
case ARM::VLD1d32:
case ARM::VLD1d32Q:
case ARM::VLD1d32T:
case ARM::VLD1d64:
case ARM::VLD1d8:
case ARM::VLD1d8Q:
case ARM::VLD1d8T:
case ARM::VLD1df:
case ARM::VLD1q16:
case ARM::VLD1q32:
case ARM::VLD1q64:
case ARM::VLD1q8:
case ARM::VLD1qf:
case ARM::VLD2LNd16:
case ARM::VLD2LNd32:
case ARM::VLD2LNd8:
case ARM::VLD2LNq16a:
case ARM::VLD2LNq16b:
case ARM::VLD2LNq32a:
case ARM::VLD2LNq32b:
case ARM::VLD2d16:
case ARM::VLD2d16D:
case ARM::VLD2d32:
case ARM::VLD2d32D:
case ARM::VLD2d64:
case ARM::VLD2d8:
case ARM::VLD2d8D:
case ARM::VLD2q16:
case ARM::VLD2q32:
case ARM::VLD2q8:
case ARM::VLD3LNd16:
case ARM::VLD3LNd32:
case ARM::VLD3LNd8:
case ARM::VLD3LNq16a:
case ARM::VLD3LNq16b:
case ARM::VLD3LNq32a:
case ARM::VLD3LNq32b:
case ARM::VLD3d16:
case ARM::VLD3d32:
case ARM::VLD3d64:
case ARM::VLD3d8:
case ARM::VLD3q16a:
case ARM::VLD3q16b:
case ARM::VLD3q32a:
case ARM::VLD3q32b:
case ARM::VLD3q8a:
case ARM::VLD3q8b:
case ARM::VLD4LNd16:
case ARM::VLD4LNd32:
case ARM::VLD4LNd8:
case ARM::VLD4LNq16a:
case ARM::VLD4LNq16b:
case ARM::VLD4LNq32a:
case ARM::VLD4LNq32b:
case ARM::VLD4d16:
case ARM::VLD4d32:
case ARM::VLD4d64:
case ARM::VLD4d8:
case ARM::VLD4q16a:
case ARM::VLD4q16b:
case ARM::VLD4q32a:
case ARM::VLD4q32b:
case ARM::VLD4q8a:
case ARM::VLD4q8b:
case ARM::VLDMD:
case ARM::VLDMS:
case ARM::VLDRD:
case ARM::VLDRQ:
case ARM::VLDRS:
case ARM::VMAXfd:
case ARM::VMAXfd_sfp:
case ARM::VMAXfq:
case ARM::VMAXsv16i8:
case ARM::VMAXsv2i32:
case ARM::VMAXsv4i16:
case ARM::VMAXsv4i32:
case ARM::VMAXsv8i16:
case ARM::VMAXsv8i8:
case ARM::VMAXuv16i8:
case ARM::VMAXuv2i32:
case ARM::VMAXuv4i16:
case ARM::VMAXuv4i32:
case ARM::VMAXuv8i16:
case ARM::VMAXuv8i8:
case ARM::VMINfd:
case ARM::VMINfd_sfp:
case ARM::VMINfq:
case ARM::VMINsv16i8:
case ARM::VMINsv2i32:
case ARM::VMINsv4i16:
case ARM::VMINsv4i32:
case ARM::VMINsv8i16:
case ARM::VMINsv8i8:
case ARM::VMINuv16i8:
case ARM::VMINuv2i32:
case ARM::VMINuv4i16:
case ARM::VMINuv4i32:
case ARM::VMINuv8i16:
case ARM::VMINuv8i8:
case ARM::VMLAD:
case ARM::VMLALslsv2i32:
case ARM::VMLALslsv4i16:
case ARM::VMLALsluv2i32:
case ARM::VMLALsluv4i16:
case ARM::VMLALsv2i64:
case ARM::VMLALsv4i32:
case ARM::VMLALsv8i16:
case ARM::VMLALuv2i64:
case ARM::VMLALuv4i32:
case ARM::VMLALuv8i16:
case ARM::VMLAS:
case ARM::VMLAfd:
case ARM::VMLAfq:
case ARM::VMLAslfd:
case ARM::VMLAslfq:
case ARM::VMLAslv2i32:
case ARM::VMLAslv4i16:
case ARM::VMLAslv4i32:
case ARM::VMLAslv8i16:
case ARM::VMLAv16i8:
case ARM::VMLAv2i32:
case ARM::VMLAv4i16:
case ARM::VMLAv4i32:
case ARM::VMLAv8i16:
case ARM::VMLAv8i8:
case ARM::VMLSD:
case ARM::VMLSLslsv2i32:
case ARM::VMLSLslsv4i16:
case ARM::VMLSLsluv2i32:
case ARM::VMLSLsluv4i16:
case ARM::VMLSLsv2i64:
case ARM::VMLSLsv4i32:
case ARM::VMLSLsv8i16:
case ARM::VMLSLuv2i64:
case ARM::VMLSLuv4i32:
case ARM::VMLSLuv8i16:
case ARM::VMLSS:
case ARM::VMLSfd:
case ARM::VMLSfq:
case ARM::VMLSslfd:
case ARM::VMLSslfq:
case ARM::VMLSslv2i32:
case ARM::VMLSslv4i16:
case ARM::VMLSslv4i32:
case ARM::VMLSslv8i16:
case ARM::VMLSv16i8:
case ARM::VMLSv2i32:
case ARM::VMLSv4i16:
case ARM::VMLSv4i32:
case ARM::VMLSv8i16:
case ARM::VMLSv8i8:
case ARM::VMOVD:
case ARM::VMOVDRR:
case ARM::VMOVDcc:
case ARM::VMOVDneon:
case ARM::VMOVLsv2i64:
case ARM::VMOVLsv4i32:
case ARM::VMOVLsv8i16:
case ARM::VMOVLuv2i64:
case ARM::VMOVLuv4i32:
case ARM::VMOVLuv8i16:
case ARM::VMOVNv2i32:
case ARM::VMOVNv4i16:
case ARM::VMOVNv8i8:
case ARM::VMOVQ:
case ARM::VMOVRRD:
case ARM::VMOVRRS:
case ARM::VMOVRS:
case ARM::VMOVS:
case ARM::VMOVSR:
case ARM::VMOVSRR:
case ARM::VMOVScc:
case ARM::VMOVv16i8:
case ARM::VMOVv1i64:
case ARM::VMOVv2i32:
case ARM::VMOVv2i64:
case ARM::VMOVv4i16:
case ARM::VMOVv4i32:
case ARM::VMOVv8i16:
case ARM::VMOVv8i8:
case ARM::VMRS:
case ARM::VMSR:
case ARM::VMULD:
case ARM::VMULLp:
case ARM::VMULLslsv2i32:
case ARM::VMULLslsv4i16:
case ARM::VMULLsluv2i32:
case ARM::VMULLsluv4i16:
case ARM::VMULLsv2i64:
case ARM::VMULLsv4i32:
case ARM::VMULLsv8i16:
case ARM::VMULLuv2i64:
case ARM::VMULLuv4i32:
case ARM::VMULLuv8i16:
case ARM::VMULS:
case ARM::VMULfd:
case ARM::VMULfd_sfp:
case ARM::VMULfq:
case ARM::VMULpd:
case ARM::VMULpq:
case ARM::VMULslfd:
case ARM::VMULslfq:
case ARM::VMULslv2i32:
case ARM::VMULslv4i16:
case ARM::VMULslv4i32:
case ARM::VMULslv8i16:
case ARM::VMULv16i8:
case ARM::VMULv2i32:
case ARM::VMULv4i16:
case ARM::VMULv4i32:
case ARM::VMULv8i16:
case ARM::VMULv8i8:
case ARM::VMVNd:
case ARM::VMVNq:
case ARM::VNEGD:
case ARM::VNEGDcc:
case ARM::VNEGS:
case ARM::VNEGScc:
case ARM::VNEGf32q:
case ARM::VNEGfd:
case ARM::VNEGfd_sfp:
case ARM::VNEGs16d:
case ARM::VNEGs16q:
case ARM::VNEGs32d:
case ARM::VNEGs32q:
case ARM::VNEGs8d:
case ARM::VNEGs8q:
case ARM::VNMLAD:
case ARM::VNMLAS:
case ARM::VNMLSD:
case ARM::VNMLSS:
case ARM::VNMULD:
case ARM::VNMULS:
case ARM::VORNd:
case ARM::VORNq:
case ARM::VORRd:
case ARM::VORRq:
case ARM::VPADALsv16i8:
case ARM::VPADALsv2i32:
case ARM::VPADALsv4i16:
case ARM::VPADALsv4i32:
case ARM::VPADALsv8i16:
case ARM::VPADALsv8i8:
case ARM::VPADALuv16i8:
case ARM::VPADALuv2i32:
case ARM::VPADALuv4i16:
case ARM::VPADALuv4i32:
case ARM::VPADALuv8i16:
case ARM::VPADALuv8i8:
case ARM::VPADDLsv16i8:
case ARM::VPADDLsv2i32:
case ARM::VPADDLsv4i16:
case ARM::VPADDLsv4i32:
case ARM::VPADDLsv8i16:
case ARM::VPADDLsv8i8:
case ARM::VPADDLuv16i8:
case ARM::VPADDLuv2i32:
case ARM::VPADDLuv4i16:
case ARM::VPADDLuv4i32:
case ARM::VPADDLuv8i16:
case ARM::VPADDLuv8i8:
case ARM::VPADDf:
case ARM::VPADDi16:
case ARM::VPADDi32:
case ARM::VPADDi8:
case ARM::VPMAXf:
case ARM::VPMAXs16:
case ARM::VPMAXs32:
case ARM::VPMAXs8:
case ARM::VPMAXu16:
case ARM::VPMAXu32:
case ARM::VPMAXu8:
case ARM::VPMINf:
case ARM::VPMINs16:
case ARM::VPMINs32:
case ARM::VPMINs8:
case ARM::VPMINu16:
case ARM::VPMINu32:
case ARM::VPMINu8:
case ARM::VQABSv16i8:
case ARM::VQABSv2i32:
case ARM::VQABSv4i16:
case ARM::VQABSv4i32:
case ARM::VQABSv8i16:
case ARM::VQABSv8i8:
case ARM::VQADDsv16i8:
case ARM::VQADDsv1i64:
case ARM::VQADDsv2i32:
case ARM::VQADDsv2i64:
case ARM::VQADDsv4i16:
case ARM::VQADDsv4i32:
case ARM::VQADDsv8i16:
case ARM::VQADDsv8i8:
case ARM::VQADDuv16i8:
case ARM::VQADDuv1i64:
case ARM::VQADDuv2i32:
case ARM::VQADDuv2i64:
case ARM::VQADDuv4i16:
case ARM::VQADDuv4i32:
case ARM::VQADDuv8i16:
case ARM::VQADDuv8i8:
case ARM::VQDMLALslv2i32:
case ARM::VQDMLALslv4i16:
case ARM::VQDMLALv2i64:
case ARM::VQDMLALv4i32:
case ARM::VQDMLSLslv2i32:
case ARM::VQDMLSLslv4i16:
case ARM::VQDMLSLv2i64:
case ARM::VQDMLSLv4i32:
case ARM::VQDMULHslv2i32:
case ARM::VQDMULHslv4i16:
case ARM::VQDMULHslv4i32:
case ARM::VQDMULHslv8i16:
case ARM::VQDMULHv2i32:
case ARM::VQDMULHv4i16:
case ARM::VQDMULHv4i32:
case ARM::VQDMULHv8i16:
case ARM::VQDMULLslv2i32:
case ARM::VQDMULLslv4i16:
case ARM::VQDMULLv2i64:
case ARM::VQDMULLv4i32:
case ARM::VQMOVNsuv2i32:
case ARM::VQMOVNsuv4i16:
case ARM::VQMOVNsuv8i8:
case ARM::VQMOVNsv2i32:
case ARM::VQMOVNsv4i16:
case ARM::VQMOVNsv8i8:
case ARM::VQMOVNuv2i32:
case ARM::VQMOVNuv4i16:
case ARM::VQMOVNuv8i8:
case ARM::VQNEGv16i8:
case ARM::VQNEGv2i32:
case ARM::VQNEGv4i16:
case ARM::VQNEGv4i32:
case ARM::VQNEGv8i16:
case ARM::VQNEGv8i8:
case ARM::VQRDMULHslv2i32:
case ARM::VQRDMULHslv4i16:
case ARM::VQRDMULHslv4i32:
case ARM::VQRDMULHslv8i16:
case ARM::VQRDMULHv2i32:
case ARM::VQRDMULHv4i16:
case ARM::VQRDMULHv4i32:
case ARM::VQRDMULHv8i16:
case ARM::VQRSHLsv16i8:
case ARM::VQRSHLsv1i64:
case ARM::VQRSHLsv2i32:
case ARM::VQRSHLsv2i64:
case ARM::VQRSHLsv4i16:
case ARM::VQRSHLsv4i32:
case ARM::VQRSHLsv8i16:
case ARM::VQRSHLsv8i8:
case ARM::VQRSHLuv16i8:
case ARM::VQRSHLuv1i64:
case ARM::VQRSHLuv2i32:
case ARM::VQRSHLuv2i64:
case ARM::VQRSHLuv4i16:
case ARM::VQRSHLuv4i32:
case ARM::VQRSHLuv8i16:
case ARM::VQRSHLuv8i8:
case ARM::VQRSHRNsv2i32:
case ARM::VQRSHRNsv4i16:
case ARM::VQRSHRNsv8i8:
case ARM::VQRSHRNuv2i32:
case ARM::VQRSHRNuv4i16:
case ARM::VQRSHRNuv8i8:
case ARM::VQRSHRUNv2i32:
case ARM::VQRSHRUNv4i16:
case ARM::VQRSHRUNv8i8:
case ARM::VQSHLsiv16i8:
case ARM::VQSHLsiv1i64:
case ARM::VQSHLsiv2i32:
case ARM::VQSHLsiv2i64:
case ARM::VQSHLsiv4i16:
case ARM::VQSHLsiv4i32:
case ARM::VQSHLsiv8i16:
case ARM::VQSHLsiv8i8:
case ARM::VQSHLsuv16i8:
case ARM::VQSHLsuv1i64:
case ARM::VQSHLsuv2i32:
case ARM::VQSHLsuv2i64:
case ARM::VQSHLsuv4i16:
case ARM::VQSHLsuv4i32:
case ARM::VQSHLsuv8i16:
case ARM::VQSHLsuv8i8:
case ARM::VQSHLsv16i8:
case ARM::VQSHLsv1i64:
case ARM::VQSHLsv2i32:
case ARM::VQSHLsv2i64:
case ARM::VQSHLsv4i16:
case ARM::VQSHLsv4i32:
case ARM::VQSHLsv8i16:
case ARM::VQSHLsv8i8:
case ARM::VQSHLuiv16i8:
case ARM::VQSHLuiv1i64:
case ARM::VQSHLuiv2i32:
case ARM::VQSHLuiv2i64:
case ARM::VQSHLuiv4i16:
case ARM::VQSHLuiv4i32:
case ARM::VQSHLuiv8i16:
case ARM::VQSHLuiv8i8:
case ARM::VQSHLuv16i8:
case ARM::VQSHLuv1i64:
case ARM::VQSHLuv2i32:
case ARM::VQSHLuv2i64:
case ARM::VQSHLuv4i16:
case ARM::VQSHLuv4i32:
case ARM::VQSHLuv8i16:
case ARM::VQSHLuv8i8:
case ARM::VQSHRNsv2i32:
case ARM::VQSHRNsv4i16:
case ARM::VQSHRNsv8i8:
case ARM::VQSHRNuv2i32:
case ARM::VQSHRNuv4i16:
case ARM::VQSHRNuv8i8:
case ARM::VQSHRUNv2i32:
case ARM::VQSHRUNv4i16:
case ARM::VQSHRUNv8i8:
case ARM::VQSUBsv16i8:
case ARM::VQSUBsv1i64:
case ARM::VQSUBsv2i32:
case ARM::VQSUBsv2i64:
case ARM::VQSUBsv4i16:
case ARM::VQSUBsv4i32:
case ARM::VQSUBsv8i16:
case ARM::VQSUBsv8i8:
case ARM::VQSUBuv16i8:
case ARM::VQSUBuv1i64:
case ARM::VQSUBuv2i32:
case ARM::VQSUBuv2i64:
case ARM::VQSUBuv4i16:
case ARM::VQSUBuv4i32:
case ARM::VQSUBuv8i16:
case ARM::VQSUBuv8i8:
case ARM::VRADDHNv2i32:
case ARM::VRADDHNv4i16:
case ARM::VRADDHNv8i8:
case ARM::VRECPEd:
case ARM::VRECPEfd:
case ARM::VRECPEfq:
case ARM::VRECPEq:
case ARM::VRECPSfd:
case ARM::VRECPSfq:
case ARM::VREV16d8:
case ARM::VREV16q8:
case ARM::VREV32d16:
case ARM::VREV32d8:
case ARM::VREV32q16:
case ARM::VREV32q8:
case ARM::VREV64d16:
case ARM::VREV64d32:
case ARM::VREV64d8:
case ARM::VREV64df:
case ARM::VREV64q16:
case ARM::VREV64q32:
case ARM::VREV64q8:
case ARM::VREV64qf:
case ARM::VRHADDsv16i8:
case ARM::VRHADDsv2i32:
case ARM::VRHADDsv4i16:
case ARM::VRHADDsv4i32:
case ARM::VRHADDsv8i16:
case ARM::VRHADDsv8i8:
case ARM::VRHADDuv16i8:
case ARM::VRHADDuv2i32:
case ARM::VRHADDuv4i16:
case ARM::VRHADDuv4i32:
case ARM::VRHADDuv8i16:
case ARM::VRHADDuv8i8:
case ARM::VRSHLsv16i8:
case ARM::VRSHLsv1i64:
case ARM::VRSHLsv2i32:
case ARM::VRSHLsv2i64:
case ARM::VRSHLsv4i16:
case ARM::VRSHLsv4i32:
case ARM::VRSHLsv8i16:
case ARM::VRSHLsv8i8:
case ARM::VRSHLuv16i8:
case ARM::VRSHLuv1i64:
case ARM::VRSHLuv2i32:
case ARM::VRSHLuv2i64:
case ARM::VRSHLuv4i16:
case ARM::VRSHLuv4i32:
case ARM::VRSHLuv8i16:
case ARM::VRSHLuv8i8:
case ARM::VRSHRNv2i32:
case ARM::VRSHRNv4i16:
case ARM::VRSHRNv8i8:
case ARM::VRSHRsv16i8:
case ARM::VRSHRsv1i64:
case ARM::VRSHRsv2i32:
case ARM::VRSHRsv2i64:
case ARM::VRSHRsv4i16:
case ARM::VRSHRsv4i32:
case ARM::VRSHRsv8i16:
case ARM::VRSHRsv8i8:
case ARM::VRSHRuv16i8:
case ARM::VRSHRuv1i64:
case ARM::VRSHRuv2i32:
case ARM::VRSHRuv2i64:
case ARM::VRSHRuv4i16:
case ARM::VRSHRuv4i32:
case ARM::VRSHRuv8i16:
case ARM::VRSHRuv8i8:
case ARM::VRSQRTEd:
case ARM::VRSQRTEfd:
case ARM::VRSQRTEfq:
case ARM::VRSQRTEq:
case ARM::VRSQRTSfd:
case ARM::VRSQRTSfq:
case ARM::VRSRAsv16i8:
case ARM::VRSRAsv1i64:
case ARM::VRSRAsv2i32:
case ARM::VRSRAsv2i64:
case ARM::VRSRAsv4i16:
case ARM::VRSRAsv4i32:
case ARM::VRSRAsv8i16:
case ARM::VRSRAsv8i8:
case ARM::VRSRAuv16i8:
case ARM::VRSRAuv1i64:
case ARM::VRSRAuv2i32:
case ARM::VRSRAuv2i64:
case ARM::VRSRAuv4i16:
case ARM::VRSRAuv4i32:
case ARM::VRSRAuv8i16:
case ARM::VRSRAuv8i8:
case ARM::VRSUBHNv2i32:
case ARM::VRSUBHNv4i16:
case ARM::VRSUBHNv8i8:
case ARM::VSETLNi16:
case ARM::VSETLNi32:
case ARM::VSETLNi8:
case ARM::VSHLLi16:
case ARM::VSHLLi32:
case ARM::VSHLLi8:
case ARM::VSHLLsv2i64:
case ARM::VSHLLsv4i32:
case ARM::VSHLLsv8i16:
case ARM::VSHLLuv2i64:
case ARM::VSHLLuv4i32:
case ARM::VSHLLuv8i16:
case ARM::VSHLiv16i8:
case ARM::VSHLiv1i64:
case ARM::VSHLiv2i32:
case ARM::VSHLiv2i64:
case ARM::VSHLiv4i16:
case ARM::VSHLiv4i32:
case ARM::VSHLiv8i16:
case ARM::VSHLiv8i8:
case ARM::VSHLsv16i8:
case ARM::VSHLsv1i64:
case ARM::VSHLsv2i32:
case ARM::VSHLsv2i64:
case ARM::VSHLsv4i16:
case ARM::VSHLsv4i32:
case ARM::VSHLsv8i16:
case ARM::VSHLsv8i8:
case ARM::VSHLuv16i8:
case ARM::VSHLuv1i64:
case ARM::VSHLuv2i32:
case ARM::VSHLuv2i64:
case ARM::VSHLuv4i16:
case ARM::VSHLuv4i32:
case ARM::VSHLuv8i16:
case ARM::VSHLuv8i8:
case ARM::VSHRNv2i32:
case ARM::VSHRNv4i16:
case ARM::VSHRNv8i8:
case ARM::VSHRsv16i8:
case ARM::VSHRsv1i64:
case ARM::VSHRsv2i32:
case ARM::VSHRsv2i64:
case ARM::VSHRsv4i16:
case ARM::VSHRsv4i32:
case ARM::VSHRsv8i16:
case ARM::VSHRsv8i8:
case ARM::VSHRuv16i8:
case ARM::VSHRuv1i64:
case ARM::VSHRuv2i32:
case ARM::VSHRuv2i64:
case ARM::VSHRuv4i16:
case ARM::VSHRuv4i32:
case ARM::VSHRuv8i16:
case ARM::VSHRuv8i8:
case ARM::VSHTOD:
case ARM::VSHTOS:
case ARM::VSITOD:
case ARM::VSITOS:
case ARM::VSLIv16i8:
case ARM::VSLIv1i64:
case ARM::VSLIv2i32:
case ARM::VSLIv2i64:
case ARM::VSLIv4i16:
case ARM::VSLIv4i32:
case ARM::VSLIv8i16:
case ARM::VSLIv8i8:
case ARM::VSLTOD:
case ARM::VSLTOS:
case ARM::VSQRTD:
case ARM::VSQRTS:
case ARM::VSRAsv16i8:
case ARM::VSRAsv1i64:
case ARM::VSRAsv2i32:
case ARM::VSRAsv2i64:
case ARM::VSRAsv4i16:
case ARM::VSRAsv4i32:
case ARM::VSRAsv8i16:
case ARM::VSRAsv8i8:
case ARM::VSRAuv16i8:
case ARM::VSRAuv1i64:
case ARM::VSRAuv2i32:
case ARM::VSRAuv2i64:
case ARM::VSRAuv4i16:
case ARM::VSRAuv4i32:
case ARM::VSRAuv8i16:
case ARM::VSRAuv8i8:
case ARM::VSRIv16i8:
case ARM::VSRIv1i64:
case ARM::VSRIv2i32:
case ARM::VSRIv2i64:
case ARM::VSRIv4i16:
case ARM::VSRIv4i32:
case ARM::VSRIv8i16:
case ARM::VSRIv8i8:
case ARM::VST1d16:
case ARM::VST1d16Q:
case ARM::VST1d16T:
case ARM::VST1d32:
case ARM::VST1d32Q:
case ARM::VST1d32T:
case ARM::VST1d64:
case ARM::VST1d8:
case ARM::VST1d8Q:
case ARM::VST1d8T:
case ARM::VST1df:
case ARM::VST1q16:
case ARM::VST1q32:
case ARM::VST1q64:
case ARM::VST1q8:
case ARM::VST1qf:
case ARM::VST2LNd16:
case ARM::VST2LNd32:
case ARM::VST2LNd8:
case ARM::VST2LNq16a:
case ARM::VST2LNq16b:
case ARM::VST2LNq32a:
case ARM::VST2LNq32b:
case ARM::VST2d16:
case ARM::VST2d16D:
case ARM::VST2d32:
case ARM::VST2d32D:
case ARM::VST2d64:
case ARM::VST2d8:
case ARM::VST2d8D:
case ARM::VST2q16:
case ARM::VST2q32:
case ARM::VST2q8:
case ARM::VST3LNd16:
case ARM::VST3LNd32:
case ARM::VST3LNd8:
case ARM::VST3LNq16a:
case ARM::VST3LNq16b:
case ARM::VST3LNq32a:
case ARM::VST3LNq32b:
case ARM::VST3d16:
case ARM::VST3d32:
case ARM::VST3d64:
case ARM::VST3d8:
case ARM::VST3q16a:
case ARM::VST3q16b:
case ARM::VST3q32a:
case ARM::VST3q32b:
case ARM::VST3q8a:
case ARM::VST3q8b:
case ARM::VST4LNd16:
case ARM::VST4LNd32:
case ARM::VST4LNd8:
case ARM::VST4LNq16a:
case ARM::VST4LNq16b:
case ARM::VST4LNq32a:
case ARM::VST4LNq32b:
case ARM::VST4d16:
case ARM::VST4d32:
case ARM::VST4d64:
case ARM::VST4d8:
case ARM::VST4q16a:
case ARM::VST4q16b:
case ARM::VST4q32a:
case ARM::VST4q32b:
case ARM::VST4q8a:
case ARM::VST4q8b:
case ARM::VSTMD:
case ARM::VSTMS:
case ARM::VSTRD:
case ARM::VSTRQ:
case ARM::VSTRS:
case ARM::VSUBD:
case ARM::VSUBHNv2i32:
case ARM::VSUBHNv4i16:
case ARM::VSUBHNv8i8:
case ARM::VSUBLsv2i64:
case ARM::VSUBLsv4i32:
case ARM::VSUBLsv8i16:
case ARM::VSUBLuv2i64:
case ARM::VSUBLuv4i32:
case ARM::VSUBLuv8i16:
case ARM::VSUBS:
case ARM::VSUBWsv2i64:
case ARM::VSUBWsv4i32:
case ARM::VSUBWsv8i16:
case ARM::VSUBWuv2i64:
case ARM::VSUBWuv4i32:
case ARM::VSUBWuv8i16:
case ARM::VSUBfd:
case ARM::VSUBfd_sfp:
case ARM::VSUBfq:
case ARM::VSUBv16i8:
case ARM::VSUBv1i64:
case ARM::VSUBv2i32:
case ARM::VSUBv2i64:
case ARM::VSUBv4i16:
case ARM::VSUBv4i32:
case ARM::VSUBv8i16:
case ARM::VSUBv8i8:
case ARM::VSWPd:
case ARM::VSWPq:
case ARM::VTBL1:
case ARM::VTBL2:
case ARM::VTBL3:
case ARM::VTBL4:
case ARM::VTBX1:
case ARM::VTBX2:
case ARM::VTBX3:
case ARM::VTBX4:
case ARM::VTOSHD:
case ARM::VTOSHS:
case ARM::VTOSIRD:
case ARM::VTOSIRS:
case ARM::VTOSIZD:
case ARM::VTOSIZS:
case ARM::VTOSLD:
case ARM::VTOSLS:
case ARM::VTOUHD:
case ARM::VTOUHS:
case ARM::VTOUIRD:
case ARM::VTOUIRS:
case ARM::VTOUIZD:
case ARM::VTOUIZS:
case ARM::VTOULD:
case ARM::VTOULS:
case ARM::VTRNd16:
case ARM::VTRNd32:
case ARM::VTRNd8:
case ARM::VTRNq16:
case ARM::VTRNq32:
case ARM::VTRNq8:
case ARM::VTSTv16i8:
case ARM::VTSTv2i32:
case ARM::VTSTv4i16:
case ARM::VTSTv4i32:
case ARM::VTSTv8i16:
case ARM::VTSTv8i8:
case ARM::VUHTOD:
case ARM::VUHTOS:
case ARM::VUITOD:
case ARM::VUITOS:
case ARM::VULTOD:
case ARM::VULTOS:
case ARM::VUZPd16:
case ARM::VUZPd32:
case ARM::VUZPd8:
case ARM::VUZPq16:
case ARM::VUZPq32:
case ARM::VUZPq8:
case ARM::VZIPd16:
case ARM::VZIPd32:
case ARM::VZIPd8:
case ARM::VZIPq16:
case ARM::VZIPq32:
case ARM::VZIPq8:
case ARM::WFE:
case ARM::WFI:
case ARM::YIELD:
case ARM::t2ADCSri:
case ARM::t2ADCSrr:
case ARM::t2ADCSrs:
case ARM::t2ADCri:
case ARM::t2ADCrr:
case ARM::t2ADCrs:
case ARM::t2ADDSri:
case ARM::t2ADDSrr:
case ARM::t2ADDSrs:
case ARM::t2ADDrSPi:
case ARM::t2ADDrSPi12:
case ARM::t2ADDrSPs:
case ARM::t2ADDri:
case ARM::t2ADDri12:
case ARM::t2ADDrr:
case ARM::t2ADDrs:
case ARM::t2ANDri:
case ARM::t2ANDrr:
case ARM::t2ANDrs:
case ARM::t2ASRri:
case ARM::t2ASRrr:
case ARM::t2B:
case ARM::t2BFC:
case ARM::t2BFI:
case ARM::t2BICri:
case ARM::t2BICrr:
case ARM::t2BICrs:
case ARM::t2BR_JT:
case ARM::t2BXJ:
case ARM::t2Bcc:
case ARM::t2CLREX:
case ARM::t2CLZ:
case ARM::t2CMNzri:
case ARM::t2CMNzrr:
case ARM::t2CMNzrs:
case ARM::t2CMPri:
case ARM::t2CMPrr:
case ARM::t2CMPrs:
case ARM::t2CMPzri:
case ARM::t2CMPzrr:
case ARM::t2CMPzrs:
case ARM::t2CPS:
case ARM::t2DBG:
case ARM::t2DMBish:
case ARM::t2DMBishst:
case ARM::t2DMBnsh:
case ARM::t2DMBnshst:
case ARM::t2DMBosh:
case ARM::t2DMBoshst:
case ARM::t2DMBst:
case ARM::t2DSBish:
case ARM::t2DSBishst:
case ARM::t2DSBnsh:
case ARM::t2DSBnshst:
case ARM::t2DSBosh:
case ARM::t2DSBoshst:
case ARM::t2DSBst:
case ARM::t2EORri:
case ARM::t2EORrr:
case ARM::t2EORrs:
case ARM::t2ISBsy:
case ARM::t2IT:
case ARM::t2Int_MemBarrierV7:
case ARM::t2Int_SyncBarrierV7:
case ARM::t2Int_eh_sjlj_setjmp:
case ARM::t2LDM:
case ARM::t2LDM_RET:
case ARM::t2LDRBT:
case ARM::t2LDRB_POST:
case ARM::t2LDRB_PRE:
case ARM::t2LDRBi12:
case ARM::t2LDRBi8:
case ARM::t2LDRBpci:
case ARM::t2LDRBs:
case ARM::t2LDRDi8:
case ARM::t2LDRDpci:
case ARM::t2LDREX:
case ARM::t2LDREXB:
case ARM::t2LDREXD:
case ARM::t2LDREXH:
case ARM::t2LDRHT:
case ARM::t2LDRH_POST:
case ARM::t2LDRH_PRE:
case ARM::t2LDRHi12:
case ARM::t2LDRHi8:
case ARM::t2LDRHpci:
case ARM::t2LDRHs:
case ARM::t2LDRSBT:
case ARM::t2LDRSB_POST:
case ARM::t2LDRSB_PRE:
case ARM::t2LDRSBi12:
case ARM::t2LDRSBi8:
case ARM::t2LDRSBpci:
case ARM::t2LDRSBs:
case ARM::t2LDRSHT:
case ARM::t2LDRSH_POST:
case ARM::t2LDRSH_PRE:
case ARM::t2LDRSHi12:
case ARM::t2LDRSHi8:
case ARM::t2LDRSHpci:
case ARM::t2LDRSHs:
case ARM::t2LDRT:
case ARM::t2LDR_POST:
case ARM::t2LDR_PRE:
case ARM::t2LDRi12:
case ARM::t2LDRi8:
case ARM::t2LDRpci:
case ARM::t2LDRpci_pic:
case ARM::t2LDRs:
case ARM::t2LEApcrel:
case ARM::t2LEApcrelJT:
case ARM::t2LSLri:
case ARM::t2LSLrr:
case ARM::t2LSRri:
case ARM::t2LSRrr:
case ARM::t2MLA:
case ARM::t2MLS:
case ARM::t2MOVCCasr:
case ARM::t2MOVCCi:
case ARM::t2MOVCClsl:
case ARM::t2MOVCClsr:
case ARM::t2MOVCCr:
case ARM::t2MOVCCror:
case ARM::t2MOVTi16:
case ARM::t2MOVi:
case ARM::t2MOVi16:
case ARM::t2MOVi32imm:
case ARM::t2MOVr:
case ARM::t2MOVrx:
case ARM::t2MOVsra_flag:
case ARM::t2MOVsrl_flag:
case ARM::t2MRS:
case ARM::t2MRSsys:
case ARM::t2MSR:
case ARM::t2MSRsys:
case ARM::t2MUL:
case ARM::t2MVNi:
case ARM::t2MVNr:
case ARM::t2MVNs:
case ARM::t2NOP:
case ARM::t2ORNri:
case ARM::t2ORNrr:
case ARM::t2ORNrs:
case ARM::t2ORRri:
case ARM::t2ORRrr:
case ARM::t2ORRrs:
case ARM::t2PKHBT:
case ARM::t2PKHTB:
case ARM::t2PLDWi12:
case ARM::t2PLDWi8:
case ARM::t2PLDWpci:
case ARM::t2PLDWr:
case ARM::t2PLDWs:
case ARM::t2PLDi12:
case ARM::t2PLDi8:
case ARM::t2PLDpci:
case ARM::t2PLDr:
case ARM::t2PLDs:
case ARM::t2PLIi12:
case ARM::t2PLIi8:
case ARM::t2PLIpci:
case ARM::t2PLIr:
case ARM::t2PLIs:
case ARM::t2QADD:
case ARM::t2QADD16:
case ARM::t2QADD8:
case ARM::t2QASX:
case ARM::t2QDADD:
case ARM::t2QDSUB:
case ARM::t2QSAX:
case ARM::t2QSUB:
case ARM::t2QSUB16:
case ARM::t2QSUB8:
case ARM::t2RBIT:
case ARM::t2REV:
case ARM::t2REV16:
case ARM::t2REVSH:
case ARM::t2RFEDB:
case ARM::t2RFEDBW:
case ARM::t2RFEIA:
case ARM::t2RFEIAW:
case ARM::t2RORri:
case ARM::t2RORrr:
case ARM::t2RSBSri:
case ARM::t2RSBSrs:
case ARM::t2RSBri:
case ARM::t2RSBrs:
case ARM::t2SADD16:
case ARM::t2SADD8:
case ARM::t2SASX:
case ARM::t2SBCSri:
case ARM::t2SBCSrr:
case ARM::t2SBCSrs:
case ARM::t2SBCri:
case ARM::t2SBCrr:
case ARM::t2SBCrs:
case ARM::t2SBFX:
case ARM::t2SDIV:
case ARM::t2SEL:
case ARM::t2SEV:
case ARM::t2SHADD16:
case ARM::t2SHADD8:
case ARM::t2SHASX:
case ARM::t2SHSAX:
case ARM::t2SHSUB16:
case ARM::t2SHSUB8:
case ARM::t2SMC:
case ARM::t2SMLABB:
case ARM::t2SMLABT:
case ARM::t2SMLAD:
case ARM::t2SMLADX:
case ARM::t2SMLAL:
case ARM::t2SMLALBB:
case ARM::t2SMLALBT:
case ARM::t2SMLALD:
case ARM::t2SMLALDX:
case ARM::t2SMLALTB:
case ARM::t2SMLALTT:
case ARM::t2SMLATB:
case ARM::t2SMLATT:
case ARM::t2SMLAWB:
case ARM::t2SMLAWT:
case ARM::t2SMLSD:
case ARM::t2SMLSDX:
case ARM::t2SMLSLD:
case ARM::t2SMLSLDX:
case ARM::t2SMMLA:
case ARM::t2SMMLAR:
case ARM::t2SMMLS:
case ARM::t2SMMLSR:
case ARM::t2SMMUL:
case ARM::t2SMMULR:
case ARM::t2SMUAD:
case ARM::t2SMUADX:
case ARM::t2SMULBB:
case ARM::t2SMULBT:
case ARM::t2SMULL:
case ARM::t2SMULTB:
case ARM::t2SMULTT:
case ARM::t2SMULWB:
case ARM::t2SMULWT:
case ARM::t2SMUSD:
case ARM::t2SMUSDX:
case ARM::t2SRSDB:
case ARM::t2SRSDBW:
case ARM::t2SRSIA:
case ARM::t2SRSIAW:
case ARM::t2SSAT16:
case ARM::t2SSATasr:
case ARM::t2SSATlsl:
case ARM::t2SSAX:
case ARM::t2SSUB16:
case ARM::t2SSUB8:
case ARM::t2STM:
case ARM::t2STRBT:
case ARM::t2STRB_POST:
case ARM::t2STRB_PRE:
case ARM::t2STRBi12:
case ARM::t2STRBi8:
case ARM::t2STRBs:
case ARM::t2STRDi8:
case ARM::t2STREX:
case ARM::t2STREXB:
case ARM::t2STREXD:
case ARM::t2STREXH:
case ARM::t2STRHT:
case ARM::t2STRH_POST:
case ARM::t2STRH_PRE:
case ARM::t2STRHi12:
case ARM::t2STRHi8:
case ARM::t2STRHs:
case ARM::t2STRT:
case ARM::t2STR_POST:
case ARM::t2STR_PRE:
case ARM::t2STRi12:
case ARM::t2STRi8:
case ARM::t2STRs:
case ARM::t2SUBSri:
case ARM::t2SUBSrr:
case ARM::t2SUBSrs:
case ARM::t2SUBrSPi:
case ARM::t2SUBrSPi12:
case ARM::t2SUBrSPi12_:
case ARM::t2SUBrSPi_:
case ARM::t2SUBrSPs:
case ARM::t2SUBrSPs_:
case ARM::t2SUBri:
case ARM::t2SUBri12:
case ARM::t2SUBrr:
case ARM::t2SUBrs:
case ARM::t2SXTAB16rr:
case ARM::t2SXTAB16rr_rot:
case ARM::t2SXTABrr:
case ARM::t2SXTABrr_rot:
case ARM::t2SXTAHrr:
case ARM::t2SXTAHrr_rot:
case ARM::t2SXTB16r:
case ARM::t2SXTB16r_rot:
case ARM::t2SXTBr:
case ARM::t2SXTBr_rot:
case ARM::t2SXTHr:
case ARM::t2SXTHr_rot:
case ARM::t2TBB:
case ARM::t2TBBgen:
case ARM::t2TBH:
case ARM::t2TBHgen:
case ARM::t2TEQri:
case ARM::t2TEQrr:
case ARM::t2TEQrs:
case ARM::t2TPsoft:
case ARM::t2TSTri:
case ARM::t2TSTrr:
case ARM::t2TSTrs:
case ARM::t2UADD16:
case ARM::t2UADD8:
case ARM::t2UASX:
case ARM::t2UBFX:
case ARM::t2UDIV:
case ARM::t2UHADD16:
case ARM::t2UHADD8:
case ARM::t2UHASX:
case ARM::t2UHSAX:
case ARM::t2UHSUB16:
case ARM::t2UHSUB8:
case ARM::t2UMAAL:
case ARM::t2UMLAL:
case ARM::t2UMULL:
case ARM::t2UQADD16:
case ARM::t2UQADD8:
case ARM::t2UQASX:
case ARM::t2UQSAX:
case ARM::t2UQSUB16:
case ARM::t2UQSUB8:
case ARM::t2USAD8:
case ARM::t2USADA8:
case ARM::t2USAT16:
case ARM::t2USATasr:
case ARM::t2USATlsl:
case ARM::t2USAX:
case ARM::t2USUB16:
case ARM::t2USUB8:
case ARM::t2UXTAB16rr:
case ARM::t2UXTAB16rr_rot:
case ARM::t2UXTABrr:
case ARM::t2UXTABrr_rot:
case ARM::t2UXTAHrr:
case ARM::t2UXTAHrr_rot:
case ARM::t2UXTB16r:
case ARM::t2UXTB16r_rot:
case ARM::t2UXTBr:
case ARM::t2UXTBr_rot:
case ARM::t2UXTHr:
case ARM::t2UXTHr_rot:
case ARM::t2WFE:
case ARM::t2WFI:
case ARM::t2YIELD:
case ARM::tADC:
case ARM::tADDhirr:
case ARM::tADDi3:
case ARM::tADDi8:
case ARM::tADDrPCi:
case ARM::tADDrSP:
case ARM::tADDrSPi:
case ARM::tADDrr:
case ARM::tADDspi:
case ARM::tADDspr:
case ARM::tADDspr_:
case ARM::tADJCALLSTACKDOWN:
case ARM::tADJCALLSTACKUP:
case ARM::tAND:
case ARM::tANDsp:
case ARM::tASRri:
case ARM::tASRrr:
case ARM::tB:
case ARM::tBIC:
case ARM::tBKPT:
case ARM::tBL:
case ARM::tBLXi:
case ARM::tBLXi_r9:
case ARM::tBLXr:
case ARM::tBLXr_r9:
case ARM::tBLr9:
case ARM::tBRIND:
case ARM::tBR_JTr:
case ARM::tBX:
case ARM::tBX_RET:
case ARM::tBX_RET_vararg:
case ARM::tBXr9:
case ARM::tBcc:
case ARM::tBfar:
case ARM::tCBNZ:
case ARM::tCBZ:
case ARM::tCMNz:
case ARM::tCMPhir:
case ARM::tCMPi8:
case ARM::tCMPr:
case ARM::tCMPzhir:
case ARM::tCMPzi8:
case ARM::tCMPzr:
case ARM::tCPS:
case ARM::tEOR:
case ARM::tInt_eh_sjlj_setjmp:
case ARM::tLDM:
case ARM::tLDR:
case ARM::tLDRB:
case ARM::tLDRBi:
case ARM::tLDRH:
case ARM::tLDRHi:
case ARM::tLDRSB:
case ARM::tLDRSH:
case ARM::tLDRcp:
case ARM::tLDRi:
case ARM::tLDRpci:
case ARM::tLDRpci_pic:
case ARM::tLDRspi:
case ARM::tLEApcrel:
case ARM::tLEApcrelJT:
case ARM::tLSLri:
case ARM::tLSLrr:
case ARM::tLSRri:
case ARM::tLSRrr:
case ARM::tMOVCCi:
case ARM::tMOVCCr:
case ARM::tMOVCCr_pseudo:
case ARM::tMOVSr:
case ARM::tMOVgpr2gpr:
case ARM::tMOVgpr2tgpr:
case ARM::tMOVi8:
case ARM::tMOVr:
case ARM::tMOVtgpr2gpr:
case ARM::tMUL:
case ARM::tMVN:
case ARM::tNOP:
case ARM::tORR:
case ARM::tPICADD:
case ARM::tPOP:
case ARM::tPOP_RET:
case ARM::tPUSH:
case ARM::tREV:
case ARM::tREV16:
case ARM::tREVSH:
case ARM::tROR:
case ARM::tRSB:
case ARM::tRestore:
case ARM::tSBC:
case ARM::tSETENDBE:
case ARM::tSETENDLE:
case ARM::tSEV:
case ARM::tSTM:
case ARM::tSTR:
case ARM::tSTRB:
case ARM::tSTRBi:
case ARM::tSTRH:
case ARM::tSTRHi:
case ARM::tSTRi:
case ARM::tSTRspi:
case ARM::tSUBi3:
case ARM::tSUBi8:
case ARM::tSUBrr:
case ARM::tSUBspi:
case ARM::tSUBspi_:
case ARM::tSVC:
case ARM::tSXTB:
case ARM::tSXTH:
case ARM::tSpill:
case ARM::tTPsoft:
case ARM::tTRAP:
case ARM::tTST:
case ARM::tUXTB:
case ARM::tUXTH:
case ARM::tWFE:
case ARM::tWFI:
case ARM::tYIELD: {
break;
}
default:
std::string msg;
raw_string_ostream Msg(msg);
Msg << "Not supported instr: " << MI;
llvm_report_error(Msg.str());
}
return Value;
}