//===- TableGen'erated file -------------------------------------*- C++ -*-===// // // Target Instruction Descriptors // // Automatically generated file, do not edit! // //===----------------------------------------------------------------------===// namespace llvm { static const TargetRegisterClass* Barriers1[] = { &PPC::CARRYRCRegClass, NULL }; static const unsigned ImplicitList1[] = { PPC::CARRY, 0 }; static const unsigned ImplicitList2[] = { PPC::R1, 0 }; static const unsigned ImplicitList3[] = { PPC::CR0, 0 }; static const unsigned ImplicitList4[] = { PPC::CTR, 0 }; static const unsigned ImplicitList5[] = { PPC::CTR8, PPC::RM, 0 }; static const TargetRegisterClass* Barriers2[] = { &PPC::CARRYRCRegClass, &PPC::CTRRC8RegClass, NULL }; static const unsigned ImplicitList6[] = { PPC::X0, PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CARRY, 0 }; static const unsigned ImplicitList7[] = { PPC::CTR, PPC::RM, 0 }; static const TargetRegisterClass* Barriers3[] = { &PPC::CARRYRCRegClass, &PPC::CTRRCRegClass, NULL }; static const unsigned ImplicitList8[] = { PPC::R0, PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CARRY, 0 }; static const unsigned ImplicitList9[] = { PPC::R0, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CARRY, 0 }; static const unsigned ImplicitList10[] = { PPC::RM, 0 }; static const unsigned ImplicitList11[] = { PPC::LR, PPC::RM, 0 }; static const unsigned ImplicitList12[] = { PPC::X1, 0 }; static const unsigned ImplicitList13[] = { PPC::CTR8, 0 }; static const unsigned ImplicitList14[] = { PPC::LR, 0 }; static const unsigned ImplicitList15[] = { PPC::LR8, 0 }; static const TargetRegisterClass* Barriers4[] = { &PPC::CTRRCRegClass, NULL }; static const TargetRegisterClass* Barriers5[] = { &PPC::CTRRC8RegClass, NULL }; static const unsigned ImplicitList16[] = { PPC::CR6, 0 }; static const TargetOperandInfo OperandInfo2[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo3[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo4[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo5[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo6[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo7[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo8[] = { { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo9[] = { { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo10[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo11[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo12[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::GPRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo13[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::G8RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo14[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { PPC::CRRCRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo15[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { PPC::CRRCRegClassID, 0|(1<<TOI::Predicate), 0 }, }; static const TargetOperandInfo OperandInfo16[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo17[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo18[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo19[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo20[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo21[] = { { PPC::CRBITRCRegClassID, 0, 0 }, { PPC::CRBITRCRegClassID, 0, 0 }, { PPC::CRBITRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo22[] = { { PPC::CRBITRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo23[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, }; static const TargetOperandInfo OperandInfo24[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo25[] = { { 0, 0, 0 }, { 0, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo26[] = { { 0, 0, 0 }, { 0, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo27[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, }; static const TargetOperandInfo OperandInfo28[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, }; static const TargetOperandInfo OperandInfo29[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo30[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo31[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo32[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo33[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo34[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo35[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo36[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo37[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo38[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo39[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo40[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo41[] = { { 0, 0, 0 }, { 0, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo42[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, }; static const TargetOperandInfo OperandInfo43[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, }; static const TargetOperandInfo OperandInfo44[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo45[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo46[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, }; static const TargetOperandInfo OperandInfo47[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, }; static const TargetOperandInfo OperandInfo48[] = { { PPC::G8RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo49[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo50[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, }; static const TargetOperandInfo OperandInfo51[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo52[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, }; static const TargetOperandInfo OperandInfo53[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, }; static const TargetOperandInfo OperandInfo54[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo55[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, }; static const TargetOperandInfo OperandInfo56[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo57[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo58[] = { { PPC::VRRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, }; static const TargetOperandInfo OperandInfo59[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo60[] = { { PPC::GPRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo61[] = { { PPC::F8RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo62[] = { { PPC::VRRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo63[] = { { 0, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo64[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo65[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo66[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo67[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo68[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo69[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo70[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo71[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo72[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo73[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo74[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo75[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo76[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo77[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo78[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo79[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo80[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo81[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::F8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo82[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::F4RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo83[] = { { PPC::CTRRCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo84[] = { { PPC::CTRRC8RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo85[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo86[] = { { PPC::VRRCRegClassID, 0, 0 }, { 0, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo87[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo88[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo89[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo90[] = { { PPC::VRRCRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetInstrDesc PPCInsts[] = { { 0, 0, 0, 52, "PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #0 = PHI { 1, 0, 0, 52, "INLINEASM", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #1 = INLINEASM { 2, 1, 0, 52, "DBG_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo8 }, // Inst #2 = DBG_LABEL { 3, 1, 0, 52, "EH_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo8 }, // Inst #3 = EH_LABEL { 4, 1, 0, 52, "GC_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo8 }, // Inst #4 = GC_LABEL { 5, 0, 0, 52, "KILL", 0|(1<<TID::Variadic), 0, NULL, NULL, NULL, 0 }, // Inst #5 = KILL { 6, 3, 1, 52, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo20 }, // Inst #6 = EXTRACT_SUBREG { 7, 4, 1, 52, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo41 }, // Inst #7 = INSERT_SUBREG { 8, 1, 1, 52, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo8 }, // Inst #8 = IMPLICIT_DEF { 9, 4, 1, 52, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #9 = SUBREG_TO_REG { 10, 3, 1, 52, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo20 }, // Inst #10 = COPY_TO_REGCLASS { 11, 0, 0, 52, "DBG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DBG_VALUE { 12, 3, 1, 14, "ADD4", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #12 = ADD4 { 13, 3, 1, 14, "ADD8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #13 = ADD8 { 14, 3, 1, 14, "ADDC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #14 = ADDC { 15, 3, 1, 14, "ADDC8", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #15 = ADDC8 { 16, 3, 1, 14, "ADDE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #16 = ADDE { 17, 3, 1, 14, "ADDE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #17 = ADDE8 { 18, 3, 1, 14, "ADDI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #18 = ADDI { 19, 3, 1, 14, "ADDI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #19 = ADDI8 { 20, 3, 1, 14, "ADDIC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #20 = ADDIC { 21, 3, 1, 14, "ADDIC8", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #21 = ADDIC8 { 22, 3, 1, 14, "ADDICo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #22 = ADDICo { 23, 3, 1, 14, "ADDIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #23 = ADDIS { 24, 3, 1, 14, "ADDIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #24 = ADDIS8 { 25, 2, 1, 14, "ADDME", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #25 = ADDME { 26, 2, 1, 14, "ADDME8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #26 = ADDME8 { 27, 2, 1, 14, "ADDZE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #27 = ADDZE { 28, 2, 1, 14, "ADDZE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #28 = ADDZE8 { 29, 1, 0, 52, "ADJCALLSTACKDOWN", 0, 0, ImplicitList2, ImplicitList2, NULL, OperandInfo8 }, // Inst #29 = ADJCALLSTACKDOWN { 30, 2, 0, 52, "ADJCALLSTACKUP", 0, 0, ImplicitList2, ImplicitList2, NULL, OperandInfo9 }, // Inst #30 = ADJCALLSTACKUP { 31, 3, 1, 14, "AND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #31 = AND { 32, 3, 1, 14, "AND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #32 = AND8 { 33, 3, 1, 14, "ANDC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #33 = ANDC { 34, 3, 1, 14, "ANDC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #34 = ANDC8 { 35, 3, 1, 14, "ANDISo", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo4 }, // Inst #35 = ANDISo { 36, 3, 1, 14, "ANDISo8", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo5 }, // Inst #36 = ANDISo8 { 37, 3, 1, 14, "ANDIo", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo4 }, // Inst #37 = ANDIo { 38, 3, 1, 14, "ANDIo8", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo5 }, // Inst #38 = ANDIo8 { 39, 5, 1, 52, "ATOMIC_CMP_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo10 }, // Inst #39 = ATOMIC_CMP_SWAP_I16 { 40, 5, 1, 52, "ATOMIC_CMP_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo10 }, // Inst #40 = ATOMIC_CMP_SWAP_I32 { 41, 5, 1, 52, "ATOMIC_CMP_SWAP_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo11 }, // Inst #41 = ATOMIC_CMP_SWAP_I64 { 42, 5, 1, 52, "ATOMIC_CMP_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo10 }, // Inst #42 = ATOMIC_CMP_SWAP_I8 { 43, 4, 1, 52, "ATOMIC_LOAD_ADD_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #43 = ATOMIC_LOAD_ADD_I16 { 44, 4, 1, 52, "ATOMIC_LOAD_ADD_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #44 = ATOMIC_LOAD_ADD_I32 { 45, 4, 1, 52, "ATOMIC_LOAD_ADD_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #45 = ATOMIC_LOAD_ADD_I64 { 46, 4, 1, 52, "ATOMIC_LOAD_ADD_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #46 = ATOMIC_LOAD_ADD_I8 { 47, 4, 1, 52, "ATOMIC_LOAD_AND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #47 = ATOMIC_LOAD_AND_I16 { 48, 4, 1, 52, "ATOMIC_LOAD_AND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #48 = ATOMIC_LOAD_AND_I32 { 49, 4, 1, 52, "ATOMIC_LOAD_AND_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #49 = ATOMIC_LOAD_AND_I64 { 50, 4, 1, 52, "ATOMIC_LOAD_AND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #50 = ATOMIC_LOAD_AND_I8 { 51, 4, 1, 52, "ATOMIC_LOAD_NAND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #51 = ATOMIC_LOAD_NAND_I16 { 52, 4, 1, 52, "ATOMIC_LOAD_NAND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #52 = ATOMIC_LOAD_NAND_I32 { 53, 4, 1, 52, "ATOMIC_LOAD_NAND_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #53 = ATOMIC_LOAD_NAND_I64 { 54, 4, 1, 52, "ATOMIC_LOAD_NAND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #54 = ATOMIC_LOAD_NAND_I8 { 55, 4, 1, 52, "ATOMIC_LOAD_OR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #55 = ATOMIC_LOAD_OR_I16 { 56, 4, 1, 52, "ATOMIC_LOAD_OR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #56 = ATOMIC_LOAD_OR_I32 { 57, 4, 1, 52, "ATOMIC_LOAD_OR_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #57 = ATOMIC_LOAD_OR_I64 { 58, 4, 1, 52, "ATOMIC_LOAD_OR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #58 = ATOMIC_LOAD_OR_I8 { 59, 4, 1, 52, "ATOMIC_LOAD_SUB_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #59 = ATOMIC_LOAD_SUB_I16 { 60, 4, 1, 52, "ATOMIC_LOAD_SUB_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #60 = ATOMIC_LOAD_SUB_I32 { 61, 4, 1, 52, "ATOMIC_LOAD_SUB_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #61 = ATOMIC_LOAD_SUB_I64 { 62, 4, 1, 52, "ATOMIC_LOAD_SUB_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #62 = ATOMIC_LOAD_SUB_I8 { 63, 4, 1, 52, "ATOMIC_LOAD_XOR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #63 = ATOMIC_LOAD_XOR_I16 { 64, 4, 1, 52, "ATOMIC_LOAD_XOR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #64 = ATOMIC_LOAD_XOR_I32 { 65, 4, 1, 52, "ATOMIC_LOAD_XOR_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #65 = ATOMIC_LOAD_XOR_I64 { 66, 4, 1, 52, "ATOMIC_LOAD_XOR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #66 = ATOMIC_LOAD_XOR_I8 { 67, 4, 1, 52, "ATOMIC_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #67 = ATOMIC_SWAP_I16 { 68, 4, 1, 52, "ATOMIC_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #68 = ATOMIC_SWAP_I32 { 69, 4, 1, 52, "ATOMIC_SWAP_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #69 = ATOMIC_SWAP_I64 { 70, 4, 1, 52, "ATOMIC_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #70 = ATOMIC_SWAP_I8 { 71, 1, 0, 0, "B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(7<<3), NULL, NULL, NULL, OperandInfo8 }, // Inst #71 = B { 72, 3, 0, 0, "BCC", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, NULL, NULL, OperandInfo14 }, // Inst #72 = BCC { 73, 0, 0, 0, "BCTR", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList4, NULL, NULL, 0 }, // Inst #73 = BCTR { 74, 0, 0, 0, "BCTRL8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList5, ImplicitList6, Barriers2, 0 }, // Inst #74 = BCTRL8_Darwin { 75, 0, 0, 0, "BCTRL8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList5, ImplicitList6, Barriers2, 0 }, // Inst #75 = BCTRL8_ELF { 76, 0, 0, 0, "BCTRL_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList7, ImplicitList8, Barriers3, 0 }, // Inst #76 = BCTRL_Darwin { 77, 0, 0, 0, "BCTRL_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList7, ImplicitList9, Barriers3, 0 }, // Inst #77 = BCTRL_SVR4 { 78, 1, 0, 0, "BL8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #78 = BL8_Darwin { 79, 1, 0, 0, "BL8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #79 = BL8_ELF { 80, 1, 0, 0, "BLA8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #80 = BLA8_Darwin { 81, 1, 0, 0, "BLA8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #81 = BLA8_ELF { 82, 1, 0, 0, "BLA_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList8, Barriers3, OperandInfo8 }, // Inst #82 = BLA_Darwin { 83, 1, 0, 0, "BLA_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList9, Barriers3, OperandInfo8 }, // Inst #83 = BLA_SVR4 { 84, 2, 0, 0, "BLR", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(7<<3), ImplicitList11, NULL, NULL, OperandInfo15 }, // Inst #84 = BLR { 85, 1, 0, 0, "BL_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList8, Barriers3, OperandInfo8 }, // Inst #85 = BL_Darwin { 86, 1, 0, 0, "BL_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList9, Barriers3, OperandInfo8 }, // Inst #86 = BL_SVR4 { 87, 3, 1, 11, "CMPD", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo16 }, // Inst #87 = CMPD { 88, 3, 1, 11, "CMPDI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo17 }, // Inst #88 = CMPDI { 89, 3, 1, 11, "CMPLD", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo16 }, // Inst #89 = CMPLD { 90, 3, 1, 11, "CMPLDI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo17 }, // Inst #90 = CMPLDI { 91, 3, 1, 11, "CMPLW", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo18 }, // Inst #91 = CMPLW { 92, 3, 1, 11, "CMPLWI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo19 }, // Inst #92 = CMPLWI { 93, 3, 1, 11, "CMPW", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo18 }, // Inst #93 = CMPW { 94, 3, 1, 11, "CMPWI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo19 }, // Inst #94 = CMPWI { 95, 2, 1, 14, "CNTLZD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #95 = CNTLZD { 96, 2, 1, 14, "CNTLZW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #96 = CNTLZW { 97, 3, 1, 1, "CREQV", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo21 }, // Inst #97 = CREQV { 98, 3, 1, 1, "CROR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo21 }, // Inst #98 = CROR { 99, 1, 1, 1, "CRSET", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo22 }, // Inst #99 = CRSET { 100, 2, 0, 30, "DCBA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #100 = DCBA { 101, 2, 0, 30, "DCBF", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #101 = DCBF { 102, 2, 0, 30, "DCBI", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #102 = DCBI { 103, 2, 0, 30, "DCBST", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #103 = DCBST { 104, 2, 0, 30, "DCBT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #104 = DCBT { 105, 2, 0, 30, "DCBTST", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #105 = DCBTST { 106, 2, 0, 30, "DCBZ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #106 = DCBZ { 107, 2, 0, 30, "DCBZL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #107 = DCBZL { 108, 3, 1, 12, "DIVD", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #108 = DIVD { 109, 3, 1, 12, "DIVDU", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #109 = DIVDU { 110, 3, 1, 13, "DIVW", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #110 = DIVW { 111, 3, 1, 13, "DIVWU", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #111 = DIVWU { 112, 4, 0, 33, "DSS", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #112 = DSS { 113, 4, 0, 33, "DSSALL", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #113 = DSSALL { 114, 4, 0, 33, "DST", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #114 = DST { 115, 4, 0, 33, "DST64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #115 = DST64 { 116, 4, 0, 33, "DSTST", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #116 = DSTST { 117, 4, 0, 33, "DSTST64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #117 = DSTST64 { 118, 4, 0, 33, "DSTSTT", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #118 = DSTSTT { 119, 4, 0, 33, "DSTSTT64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #119 = DSTSTT64 { 120, 4, 0, 33, "DSTT", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #120 = DSTT { 121, 4, 0, 33, "DSTT64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #121 = DSTT64 { 122, 4, 1, 52, "DYNALLOC", 0, 0, ImplicitList2, ImplicitList2, NULL, OperandInfo27 }, // Inst #122 = DYNALLOC { 123, 4, 1, 52, "DYNALLOC8", 0, 0, ImplicitList12, ImplicitList12, NULL, OperandInfo28 }, // Inst #123 = DYNALLOC8 { 124, 3, 1, 14, "EQV", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #124 = EQV { 125, 3, 1, 14, "EQV8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #125 = EQV8 { 126, 2, 1, 14, "EXTSB", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #126 = EXTSB { 127, 2, 1, 14, "EXTSB8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #127 = EXTSB8 { 128, 2, 1, 14, "EXTSH", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #128 = EXTSH { 129, 2, 1, 14, "EXTSH8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #129 = EXTSH8 { 130, 2, 1, 14, "EXTSW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #130 = EXTSW { 131, 2, 1, 14, "EXTSW_32", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #131 = EXTSW_32 { 132, 2, 1, 14, "EXTSW_32_64", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo29 }, // Inst #132 = EXTSW_32_64 { 133, 2, 1, 8, "FABSD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #133 = FABSD { 134, 2, 1, 8, "FABSS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #134 = FABSS { 135, 3, 1, 8, "FADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #135 = FADD { 136, 3, 1, 8, "FADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #136 = FADDS { 137, 3, 1, 8, "FADDrtz", 0, 0|(1<<1)|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #137 = FADDrtz { 138, 2, 1, 8, "FCFID", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #138 = FCFID { 139, 3, 1, 4, "FCMPUD", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<3), NULL, NULL, NULL, OperandInfo34 }, // Inst #139 = FCMPUD { 140, 3, 1, 4, "FCMPUS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<3), NULL, NULL, NULL, OperandInfo35 }, // Inst #140 = FCMPUS { 141, 2, 1, 8, "FCTIDZ", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #141 = FCTIDZ { 142, 2, 1, 8, "FCTIWZ", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #142 = FCTIWZ { 143, 3, 1, 5, "FDIV", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #143 = FDIV { 144, 3, 1, 6, "FDIVS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #144 = FDIVS { 145, 4, 1, 7, "FMADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #145 = FMADD { 146, 4, 1, 8, "FMADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #146 = FMADDS { 147, 2, 1, 8, "FMR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo31 }, // Inst #147 = FMR { 148, 2, 1, 8, "FMRSD", 0, 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #148 = FMRSD { 149, 4, 1, 7, "FMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #149 = FMSUB { 150, 4, 1, 8, "FMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #150 = FMSUBS { 151, 3, 1, 7, "FMUL", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #151 = FMUL { 152, 3, 1, 8, "FMULS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #152 = FMULS { 153, 2, 1, 8, "FNABSD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #153 = FNABSD { 154, 2, 1, 8, "FNABSS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #154 = FNABSS { 155, 2, 1, 8, "FNEGD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #155 = FNEGD { 156, 2, 1, 8, "FNEGS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #156 = FNEGS { 157, 4, 1, 7, "FNMADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #157 = FNMADD { 158, 4, 1, 8, "FNMADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #158 = FNMADDS { 159, 4, 1, 7, "FNMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #159 = FNMSUB { 160, 4, 1, 8, "FNMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #160 = FNMSUBS { 161, 2, 1, 8, "FRSP", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo39 }, // Inst #161 = FRSP { 162, 4, 1, 8, "FSELD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo36 }, // Inst #162 = FSELD { 163, 4, 1, 8, "FSELS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo40 }, // Inst #163 = FSELS { 164, 2, 1, 10, "FSQRT", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #164 = FSQRT { 165, 2, 1, 10, "FSQRTS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo31 }, // Inst #165 = FSQRTS { 166, 3, 1, 8, "FSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #166 = FSUB { 167, 3, 1, 8, "FSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #167 = FSUBS { 168, 3, 1, 14, "LA", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #168 = LA { 169, 3, 1, 33, "LBZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #169 = LBZ { 170, 3, 1, 33, "LBZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #170 = LBZ8 { 171, 4, 2, 33, "LBZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #171 = LBZU { 172, 4, 2, 33, "LBZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #172 = LBZU8 { 173, 3, 1, 33, "LBZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #173 = LBZX { 174, 3, 1, 33, "LBZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #174 = LBZX8 { 175, 3, 1, 35, "LD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #175 = LD { 176, 3, 1, 36, "LDARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo47 }, // Inst #176 = LDARX { 177, 4, 2, 35, "LDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #177 = LDU { 178, 3, 1, 35, "LDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #178 = LDX { 179, 1, 0, 35, "LDinto_toc", 0|(1<<TID::FoldableAsLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo48 }, // Inst #179 = LDinto_toc { 180, 3, 1, 35, "LDtoc", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo49 }, // Inst #180 = LDtoc { 181, 0, 0, 35, "LDtoc_restore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, 0 }, // Inst #181 = LDtoc_restore { 182, 3, 1, 37, "LFD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #182 = LFD { 183, 4, 2, 37, "LFDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 }, // Inst #183 = LFDU { 184, 3, 1, 38, "LFDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #184 = LFDX { 185, 3, 1, 38, "LFS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #185 = LFS { 186, 4, 2, 38, "LFSU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo54 }, // Inst #186 = LFSU { 187, 3, 1, 38, "LFSX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #187 = LFSX { 188, 3, 1, 39, "LHA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #188 = LHA { 189, 3, 1, 39, "LHA8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #189 = LHA8 { 190, 4, 2, 33, "LHAU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #190 = LHAU { 191, 4, 2, 33, "LHAU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #191 = LHAU8 { 192, 3, 1, 39, "LHAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #192 = LHAX { 193, 3, 1, 39, "LHAX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #193 = LHAX8 { 194, 3, 1, 33, "LHBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #194 = LHBRX { 195, 3, 1, 33, "LHZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #195 = LHZ { 196, 3, 1, 33, "LHZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #196 = LHZ8 { 197, 4, 2, 33, "LHZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #197 = LHZU { 198, 4, 2, 33, "LHZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #198 = LHZU8 { 199, 3, 1, 33, "LHZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #199 = LHZX { 200, 3, 1, 33, "LHZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #200 = LHZX8 { 201, 2, 1, 14, "LI", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #201 = LI { 202, 2, 1, 14, "LI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #202 = LI8 { 203, 2, 1, 14, "LIS", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #203 = LIS { 204, 2, 1, 14, "LIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #204 = LIS8 { 205, 3, 1, 33, "LVEBX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #205 = LVEBX { 206, 3, 1, 33, "LVEHX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #206 = LVEHX { 207, 3, 1, 33, "LVEWX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #207 = LVEWX { 208, 3, 1, 33, "LVSL", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #208 = LVSL { 209, 3, 1, 33, "LVSR", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #209 = LVSR { 210, 3, 1, 33, "LVX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #210 = LVX { 211, 3, 1, 33, "LVXL", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #211 = LVXL { 212, 3, 1, 42, "LWA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #212 = LWA { 213, 3, 1, 43, "LWARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo46 }, // Inst #213 = LWARX { 214, 3, 1, 39, "LWAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #214 = LWAX { 215, 3, 1, 33, "LWBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #215 = LWBRX { 216, 3, 1, 33, "LWZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #216 = LWZ { 217, 3, 1, 33, "LWZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #217 = LWZ8 { 218, 4, 2, 33, "LWZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #218 = LWZU { 219, 4, 2, 33, "LWZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #219 = LWZU8 { 220, 3, 1, 33, "LWZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #220 = LWZX { 221, 3, 1, 33, "LWZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #221 = LWZX8 { 222, 2, 1, 2, "MCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo59 }, // Inst #222 = MCRF { 223, 1, 1, 54, "MFCR", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #223 = MFCR { 224, 1, 1, 56, "MFCTR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList4, NULL, NULL, OperandInfo60 }, // Inst #224 = MFCTR { 225, 1, 1, 56, "MFCTR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList13, NULL, NULL, OperandInfo48 }, // Inst #225 = MFCTR8 { 226, 1, 1, 15, "MFFS", 0, 0|(1<<1)|(3<<3), ImplicitList10, NULL, NULL, OperandInfo61 }, // Inst #226 = MFFS { 227, 1, 1, 56, "MFLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList14, NULL, NULL, OperandInfo60 }, // Inst #227 = MFLR { 228, 1, 1, 56, "MFLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList15, NULL, NULL, OperandInfo48 }, // Inst #228 = MFLR8 { 229, 2, 1, 54, "MFOCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #229 = MFOCRF { 230, 1, 1, 14, "MFVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #230 = MFVRSAVE { 231, 1, 1, 33, "MFVSCR", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #231 = MFVSCR { 232, 2, 0, 3, "MTCRF", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo63 }, // Inst #232 = MTCRF { 233, 1, 0, 60, "MTCTR", 0, 0|1|(1<<3), NULL, ImplicitList4, Barriers4, OperandInfo60 }, // Inst #233 = MTCTR { 234, 1, 0, 60, "MTCTR8", 0, 0|1|(1<<3), NULL, ImplicitList13, Barriers5, OperandInfo48 }, // Inst #234 = MTCTR8 { 235, 1, 0, 17, "MTFSB0", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #235 = MTFSB0 { 236, 1, 0, 17, "MTFSB1", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #236 = MTFSB1 { 237, 4, 1, 17, "MTFSF", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo64 }, // Inst #237 = MTFSF { 238, 1, 0, 60, "MTLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList14, NULL, OperandInfo60 }, // Inst #238 = MTLR { 239, 1, 0, 60, "MTLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList15, NULL, OperandInfo48 }, // Inst #239 = MTLR8 { 240, 1, 0, 14, "MTVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<1)|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #240 = MTVRSAVE { 241, 1, 0, 33, "MTVSCR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #241 = MTVSCR { 242, 3, 1, 20, "MULHD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #242 = MULHD { 243, 3, 1, 21, "MULHDU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #243 = MULHDU { 244, 3, 1, 20, "MULHW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #244 = MULHW { 245, 3, 1, 21, "MULHWU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #245 = MULHWU { 246, 3, 1, 19, "MULLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #246 = MULLD { 247, 3, 1, 22, "MULLI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #247 = MULLI { 248, 3, 1, 20, "MULLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #248 = MULLW { 249, 1, 0, 52, "MovePCtoLR", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList14, NULL, OperandInfo8 }, // Inst #249 = MovePCtoLR { 250, 1, 0, 52, "MovePCtoLR8", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList15, NULL, OperandInfo8 }, // Inst #250 = MovePCtoLR8 { 251, 3, 1, 14, "NAND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #251 = NAND { 252, 3, 1, 14, "NAND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #252 = NAND8 { 253, 2, 1, 14, "NEG", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #253 = NEG { 254, 2, 1, 14, "NEG8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #254 = NEG8 { 255, 0, 0, 14, "NOP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, 0 }, // Inst #255 = NOP { 256, 3, 1, 14, "NOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #256 = NOR { 257, 3, 1, 14, "NOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #257 = NOR8 { 258, 3, 1, 14, "OR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #258 = OR { 259, 3, 1, 14, "OR4To8", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo65 }, // Inst #259 = OR4To8 { 260, 3, 1, 14, "OR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #260 = OR8 { 261, 3, 1, 14, "OR8To4", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo66 }, // Inst #261 = OR8To4 { 262, 3, 1, 14, "ORC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #262 = ORC { 263, 3, 1, 14, "ORC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #263 = ORC8 { 264, 3, 1, 14, "ORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #264 = ORI { 265, 3, 1, 14, "ORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #265 = ORI8 { 266, 3, 1, 14, "ORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #266 = ORIS { 267, 3, 1, 14, "ORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #267 = ORIS8 { 268, 4, 1, 25, "RLDCL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo67 }, // Inst #268 = RLDCL { 269, 4, 1, 25, "RLDICL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #269 = RLDICL { 270, 4, 1, 25, "RLDICR", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #270 = RLDICR { 271, 5, 1, 25, "RLDIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo69 }, // Inst #271 = RLDIMI { 272, 6, 1, 24, "RLWIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo70 }, // Inst #272 = RLWIMI { 273, 5, 1, 14, "RLWINM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo71 }, // Inst #273 = RLWINM { 274, 5, 1, 14, "RLWINMo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, ImplicitList3, NULL, OperandInfo71 }, // Inst #274 = RLWINMo { 275, 5, 1, 14, "RLWNM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo72 }, // Inst #275 = RLWNM { 276, 5, 1, 52, "SELECT_CC_F4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo73 }, // Inst #276 = SELECT_CC_F4 { 277, 5, 1, 52, "SELECT_CC_F8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo74 }, // Inst #277 = SELECT_CC_F8 { 278, 5, 1, 52, "SELECT_CC_I4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo75 }, // Inst #278 = SELECT_CC_I4 { 279, 5, 1, 52, "SELECT_CC_I8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo76 }, // Inst #279 = SELECT_CC_I8 { 280, 5, 1, 52, "SELECT_CC_VRRC", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo77 }, // Inst #280 = SELECT_CC_VRRC { 281, 3, 1, 25, "SLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #281 = SLD { 282, 3, 1, 14, "SLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #282 = SLW { 283, 3, 0, 52, "SPILL_CR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo42 }, // Inst #283 = SPILL_CR { 284, 3, 1, 25, "SRAD", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo78 }, // Inst #284 = SRAD { 285, 3, 1, 25, "SRADI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #285 = SRADI { 286, 3, 1, 26, "SRAW", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #286 = SRAW { 287, 3, 1, 26, "SRAWI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #287 = SRAWI { 288, 3, 1, 25, "SRD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #288 = SRD { 289, 3, 1, 14, "SRW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #289 = SRW { 290, 3, 0, 33, "STB", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #290 = STB { 291, 3, 0, 33, "STB8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #291 = STB8 { 292, 4, 1, 33, "STBU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #292 = STBU { 293, 4, 1, 33, "STBU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #293 = STBU8 { 294, 3, 0, 33, "STBX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #294 = STBX { 295, 3, 0, 33, "STBX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #295 = STBX8 { 296, 3, 0, 46, "STD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #296 = STD { 297, 3, 0, 47, "STDCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo47 }, // Inst #297 = STDCX { 298, 4, 1, 46, "STDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #298 = STDU { 299, 3, 0, 46, "STDUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #299 = STDUX { 300, 3, 0, 46, "STDX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #300 = STDX { 301, 3, 0, 46, "STDX_32", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #301 = STDX_32 { 302, 3, 0, 46, "STD_32", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #302 = STD_32 { 303, 3, 0, 51, "STFD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #303 = STFD { 304, 4, 1, 33, "STFDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo81 }, // Inst #304 = STFDU { 305, 3, 0, 51, "STFDX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #305 = STFDX { 306, 3, 0, 51, "STFIWX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #306 = STFIWX { 307, 3, 0, 51, "STFS", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #307 = STFS { 308, 4, 1, 33, "STFSU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo82 }, // Inst #308 = STFSU { 309, 3, 0, 51, "STFSX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #309 = STFSX { 310, 3, 0, 33, "STH", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #310 = STH { 311, 3, 0, 33, "STH8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #311 = STH8 { 312, 3, 0, 33, "STHBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #312 = STHBRX { 313, 4, 1, 33, "STHU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #313 = STHU { 314, 4, 1, 33, "STHU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #314 = STHU8 { 315, 3, 0, 33, "STHX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #315 = STHX { 316, 3, 0, 33, "STHX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #316 = STHX8 { 317, 3, 0, 33, "STVEBX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #317 = STVEBX { 318, 3, 0, 33, "STVEHX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #318 = STVEHX { 319, 3, 0, 33, "STVEWX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #319 = STVEWX { 320, 3, 0, 33, "STVX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #320 = STVX { 321, 3, 0, 33, "STVXL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #321 = STVXL { 322, 3, 0, 33, "STW", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #322 = STW { 323, 3, 0, 33, "STW8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #323 = STW8 { 324, 3, 0, 33, "STWBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #324 = STWBRX { 325, 3, 0, 49, "STWCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo46 }, // Inst #325 = STWCX { 326, 4, 1, 33, "STWU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #326 = STWU { 327, 3, 0, 33, "STWUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #327 = STWUX { 328, 3, 0, 33, "STWX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #328 = STWX { 329, 3, 0, 33, "STWX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #329 = STWX8 { 330, 3, 1, 14, "SUBF", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #330 = SUBF { 331, 3, 1, 14, "SUBF8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #331 = SUBF8 { 332, 3, 1, 14, "SUBFC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #332 = SUBFC { 333, 3, 1, 14, "SUBFC8", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #333 = SUBFC8 { 334, 3, 1, 14, "SUBFE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #334 = SUBFE { 335, 3, 1, 14, "SUBFE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #335 = SUBFE8 { 336, 3, 1, 14, "SUBFIC", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #336 = SUBFIC { 337, 3, 1, 14, "SUBFIC8", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #337 = SUBFIC8 { 338, 2, 1, 14, "SUBFME", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #338 = SUBFME { 339, 2, 1, 14, "SUBFME8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #339 = SUBFME8 { 340, 2, 1, 14, "SUBFZE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #340 = SUBFZE { 341, 2, 1, 14, "SUBFZE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #341 = SUBFZE8 { 342, 0, 0, 50, "SYNC", 0|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #342 = SYNC { 343, 1, 0, 0, "TAILB", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #343 = TAILB { 344, 1, 0, 0, "TAILB8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #344 = TAILB8 { 345, 1, 0, 0, "TAILBA", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #345 = TAILBA { 346, 1, 0, 0, "TAILBA8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #346 = TAILBA8 { 347, 0, 0, 0, "TAILBCTR", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #347 = TAILBCTR { 348, 0, 0, 0, "TAILBCTR8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #348 = TAILBCTR8 { 349, 2, 0, 52, "TCRETURNai", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #349 = TCRETURNai { 350, 2, 0, 52, "TCRETURNai8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #350 = TCRETURNai8 { 351, 2, 0, 52, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #351 = TCRETURNdi { 352, 2, 0, 52, "TCRETURNdi8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #352 = TCRETURNdi8 { 353, 2, 0, 52, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo83 }, // Inst #353 = TCRETURNri { 354, 2, 0, 52, "TCRETURNri8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo84 }, // Inst #354 = TCRETURNri8 { 355, 0, 0, 33, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #355 = TRAP { 356, 2, 1, 52, "UPDATE_VRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo6 }, // Inst #356 = UPDATE_VRSAVE { 357, 3, 1, 67, "VADDCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #357 = VADDCUW { 358, 3, 1, 67, "VADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #358 = VADDFP { 359, 3, 1, 67, "VADDSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #359 = VADDSBS { 360, 3, 1, 67, "VADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #360 = VADDSHS { 361, 3, 1, 67, "VADDSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #361 = VADDSWS { 362, 3, 1, 70, "VADDUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #362 = VADDUBM { 363, 3, 1, 67, "VADDUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #363 = VADDUBS { 364, 3, 1, 70, "VADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #364 = VADDUHM { 365, 3, 1, 67, "VADDUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #365 = VADDUHS { 366, 3, 1, 70, "VADDUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #366 = VADDUWM { 367, 3, 1, 67, "VADDUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #367 = VADDUWS { 368, 3, 1, 67, "VAND", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #368 = VAND { 369, 3, 1, 67, "VANDC", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #369 = VANDC { 370, 3, 1, 67, "VAVGSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #370 = VAVGSB { 371, 3, 1, 67, "VAVGSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #371 = VAVGSH { 372, 3, 1, 67, "VAVGSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #372 = VAVGSW { 373, 3, 1, 67, "VAVGUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #373 = VAVGUB { 374, 3, 1, 67, "VAVGUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #374 = VAVGUH { 375, 3, 1, 67, "VAVGUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #375 = VAVGUW { 376, 3, 1, 67, "VCFSX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #376 = VCFSX { 377, 3, 1, 67, "VCFUX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #377 = VCFUX { 378, 3, 1, 68, "VCMPBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #378 = VCMPBFP { 379, 3, 1, 68, "VCMPBFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #379 = VCMPBFPo { 380, 3, 1, 68, "VCMPEQFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #380 = VCMPEQFP { 381, 3, 1, 68, "VCMPEQFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #381 = VCMPEQFPo { 382, 3, 1, 68, "VCMPEQUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #382 = VCMPEQUB { 383, 3, 1, 68, "VCMPEQUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #383 = VCMPEQUBo { 384, 3, 1, 68, "VCMPEQUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #384 = VCMPEQUH { 385, 3, 1, 68, "VCMPEQUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #385 = VCMPEQUHo { 386, 3, 1, 68, "VCMPEQUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #386 = VCMPEQUW { 387, 3, 1, 68, "VCMPEQUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #387 = VCMPEQUWo { 388, 3, 1, 68, "VCMPGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #388 = VCMPGEFP { 389, 3, 1, 68, "VCMPGEFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #389 = VCMPGEFPo { 390, 3, 1, 68, "VCMPGTFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #390 = VCMPGTFP { 391, 3, 1, 68, "VCMPGTFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #391 = VCMPGTFPo { 392, 3, 1, 68, "VCMPGTSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #392 = VCMPGTSB { 393, 3, 1, 68, "VCMPGTSBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #393 = VCMPGTSBo { 394, 3, 1, 68, "VCMPGTSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #394 = VCMPGTSH { 395, 3, 1, 68, "VCMPGTSHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #395 = VCMPGTSHo { 396, 3, 1, 68, "VCMPGTSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #396 = VCMPGTSW { 397, 3, 1, 68, "VCMPGTSWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #397 = VCMPGTSWo { 398, 3, 1, 68, "VCMPGTUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #398 = VCMPGTUB { 399, 3, 1, 68, "VCMPGTUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #399 = VCMPGTUBo { 400, 3, 1, 68, "VCMPGTUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #400 = VCMPGTUH { 401, 3, 1, 68, "VCMPGTUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #401 = VCMPGTUHo { 402, 3, 1, 68, "VCMPGTUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #402 = VCMPGTUW { 403, 3, 1, 68, "VCMPGTUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #403 = VCMPGTUWo { 404, 3, 1, 67, "VCTSXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #404 = VCTSXS { 405, 3, 1, 67, "VCTUXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #405 = VCTUXS { 406, 2, 1, 67, "VEXPTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #406 = VEXPTEFP { 407, 2, 1, 67, "VLOGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #407 = VLOGEFP { 408, 4, 1, 67, "VMADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #408 = VMADDFP { 409, 3, 1, 67, "VMAXFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #409 = VMAXFP { 410, 3, 1, 67, "VMAXSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #410 = VMAXSB { 411, 3, 1, 67, "VMAXSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #411 = VMAXSH { 412, 3, 1, 67, "VMAXSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #412 = VMAXSW { 413, 3, 1, 67, "VMAXUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #413 = VMAXUB { 414, 3, 1, 67, "VMAXUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #414 = VMAXUH { 415, 3, 1, 67, "VMAXUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #415 = VMAXUW { 416, 4, 1, 67, "VMHADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #416 = VMHADDSHS { 417, 4, 1, 67, "VMHRADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #417 = VMHRADDSHS { 418, 3, 1, 67, "VMINFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #418 = VMINFP { 419, 3, 1, 67, "VMINSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #419 = VMINSB { 420, 3, 1, 67, "VMINSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #420 = VMINSH { 421, 3, 1, 67, "VMINSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #421 = VMINSW { 422, 3, 1, 67, "VMINUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #422 = VMINUB { 423, 3, 1, 67, "VMINUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #423 = VMINUH { 424, 3, 1, 67, "VMINUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #424 = VMINUW { 425, 4, 1, 67, "VMLADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #425 = VMLADDUHM { 426, 3, 1, 67, "VMRGHB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #426 = VMRGHB { 427, 3, 1, 67, "VMRGHH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #427 = VMRGHH { 428, 3, 1, 67, "VMRGHW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #428 = VMRGHW { 429, 3, 1, 67, "VMRGLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #429 = VMRGLB { 430, 3, 1, 67, "VMRGLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #430 = VMRGLH { 431, 3, 1, 67, "VMRGLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #431 = VMRGLW { 432, 4, 1, 67, "VMSUMMBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #432 = VMSUMMBM { 433, 4, 1, 67, "VMSUMSHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #433 = VMSUMSHM { 434, 4, 1, 67, "VMSUMSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #434 = VMSUMSHS { 435, 4, 1, 67, "VMSUMUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #435 = VMSUMUBM { 436, 4, 1, 67, "VMSUMUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #436 = VMSUMUHM { 437, 4, 1, 67, "VMSUMUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #437 = VMSUMUHS { 438, 3, 1, 67, "VMULESB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #438 = VMULESB { 439, 3, 1, 67, "VMULESH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #439 = VMULESH { 440, 3, 1, 67, "VMULEUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #440 = VMULEUB { 441, 3, 1, 67, "VMULEUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #441 = VMULEUH { 442, 3, 1, 67, "VMULOSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #442 = VMULOSB { 443, 3, 1, 67, "VMULOSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #443 = VMULOSH { 444, 3, 1, 67, "VMULOUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #444 = VMULOUB { 445, 3, 1, 67, "VMULOUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #445 = VMULOUH { 446, 4, 1, 67, "VNMSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #446 = VNMSUBFP { 447, 3, 1, 67, "VNOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #447 = VNOR { 448, 3, 1, 67, "VOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #448 = VOR { 449, 4, 1, 67, "VPERM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #449 = VPERM { 450, 3, 1, 67, "VPKPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #450 = VPKPX { 451, 3, 1, 67, "VPKSHSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #451 = VPKSHSS { 452, 3, 1, 67, "VPKSHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #452 = VPKSHUS { 453, 3, 1, 67, "VPKSWSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #453 = VPKSWSS { 454, 3, 1, 67, "VPKSWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #454 = VPKSWUS { 455, 3, 1, 67, "VPKUHUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #455 = VPKUHUM { 456, 3, 1, 67, "VPKUHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #456 = VPKUHUS { 457, 3, 1, 67, "VPKUWUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #457 = VPKUWUM { 458, 3, 1, 67, "VPKUWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #458 = VPKUWUS { 459, 2, 1, 67, "VREFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #459 = VREFP { 460, 2, 1, 67, "VRFIM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #460 = VRFIM { 461, 2, 1, 67, "VRFIN", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #461 = VRFIN { 462, 2, 1, 67, "VRFIP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #462 = VRFIP { 463, 2, 1, 67, "VRFIZ", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #463 = VRFIZ { 464, 3, 1, 67, "VRLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #464 = VRLB { 465, 3, 1, 67, "VRLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #465 = VRLH { 466, 3, 1, 67, "VRLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #466 = VRLW { 467, 2, 1, 67, "VRSQRTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #467 = VRSQRTEFP { 468, 4, 1, 67, "VSEL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #468 = VSEL { 469, 3, 1, 67, "VSL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #469 = VSL { 470, 3, 1, 67, "VSLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #470 = VSLB { 471, 4, 1, 67, "VSLDOI", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo89 }, // Inst #471 = VSLDOI { 472, 3, 1, 67, "VSLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #472 = VSLH { 473, 3, 1, 67, "VSLO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #473 = VSLO { 474, 3, 1, 67, "VSLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #474 = VSLW { 475, 3, 1, 71, "VSPLTB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #475 = VSPLTB { 476, 3, 1, 71, "VSPLTH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #476 = VSPLTH { 477, 2, 1, 71, "VSPLTISB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #477 = VSPLTISB { 478, 2, 1, 71, "VSPLTISH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #478 = VSPLTISH { 479, 2, 1, 71, "VSPLTISW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #479 = VSPLTISW { 480, 3, 1, 71, "VSPLTW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #480 = VSPLTW { 481, 3, 1, 67, "VSR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #481 = VSR { 482, 3, 1, 67, "VSRAB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #482 = VSRAB { 483, 3, 1, 67, "VSRAH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #483 = VSRAH { 484, 3, 1, 67, "VSRAW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #484 = VSRAW { 485, 3, 1, 67, "VSRB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #485 = VSRB { 486, 3, 1, 67, "VSRH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #486 = VSRH { 487, 3, 1, 67, "VSRO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #487 = VSRO { 488, 3, 1, 67, "VSRW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #488 = VSRW { 489, 3, 1, 67, "VSUBCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #489 = VSUBCUW { 490, 3, 1, 70, "VSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #490 = VSUBFP { 491, 3, 1, 67, "VSUBSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #491 = VSUBSBS { 492, 3, 1, 67, "VSUBSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #492 = VSUBSHS { 493, 3, 1, 67, "VSUBSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #493 = VSUBSWS { 494, 3, 1, 70, "VSUBUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #494 = VSUBUBM { 495, 3, 1, 67, "VSUBUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #495 = VSUBUBS { 496, 3, 1, 70, "VSUBUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #496 = VSUBUHM { 497, 3, 1, 67, "VSUBUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #497 = VSUBUHS { 498, 3, 1, 70, "VSUBUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #498 = VSUBUWM { 499, 3, 1, 67, "VSUBUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #499 = VSUBUWS { 500, 3, 1, 67, "VSUM2SWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #500 = VSUM2SWS { 501, 3, 1, 67, "VSUM4SBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #501 = VSUM4SBS { 502, 3, 1, 67, "VSUM4SHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #502 = VSUM4SHS { 503, 3, 1, 67, "VSUM4UBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #503 = VSUM4UBS { 504, 3, 1, 67, "VSUMSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #504 = VSUMSWS { 505, 2, 1, 67, "VUPKHPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #505 = VUPKHPX { 506, 2, 1, 67, "VUPKHSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #506 = VUPKHSB { 507, 2, 1, 67, "VUPKHSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #507 = VUPKHSH { 508, 2, 1, 67, "VUPKLPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #508 = VUPKLPX { 509, 2, 1, 67, "VUPKLSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #509 = VUPKLSB { 510, 2, 1, 67, "VUPKLSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #510 = VUPKLSH { 511, 3, 1, 67, "VXOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #511 = VXOR { 512, 1, 1, 67, "V_SET0", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo62 }, // Inst #512 = V_SET0 { 513, 3, 1, 14, "XOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #513 = XOR { 514, 3, 1, 14, "XOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #514 = XOR8 { 515, 3, 1, 14, "XORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #515 = XORI { 516, 3, 1, 14, "XORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #516 = XORI8 { 517, 3, 1, 14, "XORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #517 = XORIS { 518, 3, 1, 14, "XORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #518 = XORIS8 }; } // End llvm namespace