//===- TableGen'erated file -------------------------------------*- C++ -*-===// // // Target Instruction Descriptors // // Automatically generated file, do not edit! // //===----------------------------------------------------------------------===// namespace llvm { static const unsigned ImplicitList1[] = { X86::EFLAGS, 0 }; static const TargetRegisterClass* Barriers1[] = { &X86::CCRRegClass, NULL }; static const unsigned ImplicitList2[] = { X86::ESP, 0 }; static const unsigned ImplicitList3[] = { X86::ESP, X86::EFLAGS, 0 }; static const unsigned ImplicitList4[] = { X86::RSP, 0 }; static const unsigned ImplicitList5[] = { X86::RSP, X86::EFLAGS, 0 }; static const unsigned ImplicitList6[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0 }; static const TargetRegisterClass* Barriers2[] = { &X86::CCRRegClass, &X86::GR32_ABCDRegClass, &X86::GR32_ADRegClass, NULL }; static const unsigned ImplicitList7[] = { X86::EFLAGS, X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0 }; static const unsigned ImplicitList8[] = { X86::XMM0, 0 }; static const TargetRegisterClass* Barriers3[] = { &X86::CCRRegClass, &X86::FR32RegClass, &X86::FR64RegClass, &X86::GR32_ADRegClass, &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, &X86::VR128RegClass, &X86::VR64RegClass, NULL }; static const unsigned ImplicitList9[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, 0 }; static const TargetRegisterClass* Barriers4[] = { &X86::CCRRegClass, &X86::FR32RegClass, &X86::FR64RegClass, &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, &X86::VR128RegClass, &X86::VR64RegClass, NULL }; static const unsigned ImplicitList10[] = { X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::ST1, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, 0 }; static const unsigned ImplicitList11[] = { X86::AL, 0 }; static const unsigned ImplicitList12[] = { X86::AX, 0 }; static const unsigned ImplicitList13[] = { X86::EAX, 0 }; static const TargetRegisterClass* Barriers5[] = { &X86::GR32_ADRegClass, NULL }; static const unsigned ImplicitList14[] = { X86::EAX, X86::EDX, 0 }; static const unsigned ImplicitList15[] = { X86::RAX, 0 }; static const unsigned ImplicitList16[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, 0 }; static const unsigned ImplicitList17[] = { X86::RAX, X86::RDX, X86::EFLAGS, 0 }; static const TargetRegisterClass* Barriers6[] = { &X86::CCRRegClass, &X86::GR32_ADRegClass, NULL }; static const unsigned ImplicitList18[] = { X86::EAX, X86::EDX, X86::EFLAGS, 0 }; static const unsigned ImplicitList19[] = { X86::RAX, X86::RDX, 0 }; static const unsigned ImplicitList20[] = { X86::AX, X86::DX, 0 }; static const unsigned ImplicitList21[] = { X86::AX, X86::DX, X86::EFLAGS, 0 }; static const unsigned ImplicitList22[] = { X86::AL, X86::EFLAGS, X86::AX, 0 }; static const TargetRegisterClass* Barriers7[] = { &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, NULL }; static const unsigned ImplicitList23[] = { X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 0 }; static const unsigned ImplicitList24[] = { X86::ST0, 0 }; static const unsigned ImplicitList25[] = { X86::ST1, 0 }; static const unsigned ImplicitList26[] = { X86::DX, 0 }; static const unsigned ImplicitList27[] = { X86::ECX, 0 }; static const unsigned ImplicitList28[] = { X86::AH, 0 }; static const unsigned ImplicitList29[] = { X86::AX, X86::EFLAGS, 0 }; static const unsigned ImplicitList30[] = { X86::EAX, X86::EFLAGS, 0 }; static const unsigned ImplicitList31[] = { X86::RAX, X86::EFLAGS, 0 }; static const unsigned ImplicitList32[] = { X86::AL, X86::EFLAGS, 0 }; static const unsigned ImplicitList33[] = { X86::EBP, X86::ESP, 0 }; static const unsigned ImplicitList34[] = { X86::RBP, X86::RSP, 0 }; static const unsigned ImplicitList35[] = { X86::EDI, 0 }; static const unsigned ImplicitList36[] = { X86::RDI, 0 }; static const unsigned ImplicitList37[] = { X86::EDI, X86::ESI, X86::EFLAGS, 0 }; static const unsigned ImplicitList38[] = { X86::EDI, X86::ESI, 0 }; static const unsigned ImplicitList39[] = { X86::DX, X86::AX, 0 }; static const unsigned ImplicitList40[] = { X86::DX, X86::EAX, 0 }; static const unsigned ImplicitList41[] = { X86::DX, X86::AL, 0 }; static const unsigned ImplicitList42[] = { X86::ECX, X86::EFLAGS, 0 }; static const unsigned ImplicitList43[] = { X86::XMM0, X86::EFLAGS, 0 }; static const unsigned ImplicitList44[] = { X86::CL, 0 }; static const unsigned ImplicitList45[] = { X86::RAX, X86::RCX, X86::RDX, 0 }; static const unsigned ImplicitList46[] = { X86::ECX, X86::EDI, X86::ESI, 0 }; static const unsigned ImplicitList47[] = { X86::RCX, X86::RDI, X86::RSI, 0 }; static const unsigned ImplicitList48[] = { X86::AL, X86::ECX, X86::EDI, 0 }; static const unsigned ImplicitList49[] = { X86::ECX, X86::EDI, 0 }; static const unsigned ImplicitList50[] = { X86::EAX, X86::ECX, X86::EDI, 0 }; static const unsigned ImplicitList51[] = { X86::RAX, X86::RCX, X86::RDI, 0 }; static const unsigned ImplicitList52[] = { X86::RCX, X86::RDI, 0 }; static const unsigned ImplicitList53[] = { X86::AX, X86::ECX, X86::EDI, 0 }; static const unsigned ImplicitList54[] = { X86::AL, X86::EDI, X86::EFLAGS, 0 }; static const unsigned ImplicitList55[] = { X86::EAX, X86::EDI, X86::EFLAGS, 0 }; static const unsigned ImplicitList56[] = { X86::AX, X86::EDI, X86::EFLAGS, 0 }; static const TargetRegisterClass* Barriers8[] = { &X86::CCRRegClass, &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, &X86::VR64RegClass, NULL }; static const unsigned ImplicitList57[] = { X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::ST1, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::EFLAGS, 0 }; static const TargetOperandInfo OperandInfo2[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo3[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo4[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo5[] = { { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo6[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo7[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo8[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo9[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo10[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo11[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo12[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo13[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo14[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo15[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo16[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo17[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo18[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo19[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo20[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo21[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo22[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo23[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR8RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo24[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo25[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR128RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo26[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo27[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo28[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo29[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo30[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo31[] = { { X86::RSTRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo32[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo33[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo34[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo35[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo36[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo37[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo38[] = { { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo39[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo40[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo41[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo42[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo43[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo44[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo45[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo46[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo47[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo48[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo49[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo50[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo51[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo52[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo53[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo54[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo55[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo56[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo57[] = { { X86::GR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo58[] = { { X86::GR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo59[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo60[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo61[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP80RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo62[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo63[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo64[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo65[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo66[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo67[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo68[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo69[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo70[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo71[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo72[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo73[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo74[] = { { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo75[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo76[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo77[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo78[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR8RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo79[] = { { X86::GR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo80[] = { { X86::FR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo81[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo82[] = { { X86::FR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo83[] = { { X86::FR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo84[] = { { X86::FR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo85[] = { { X86::FR32RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo86[] = { { X86::FR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo87[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo88[] = { { X86::GR64RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo89[] = { { X86::GR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo90[] = { { X86::GR32RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo91[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo92[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, }; static const TargetOperandInfo OperandInfo93[] = { { X86::GR16RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo94[] = { { X86::GR8RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo95[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo96[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo97[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo98[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo99[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo100[] = { { X86::RFP32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo101[] = { { X86::RFP64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo102[] = { { X86::RFP80RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo103[] = { { X86::FR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo104[] = { { X86::FR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo105[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo106[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo107[] = { { X86::RFP32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo108[] = { { X86::RFP64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo109[] = { { X86::RFP80RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo110[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo111[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo112[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo113[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo114[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo115[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo116[] = { { 0, 0, 0 }, { 0, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo117[] = { { X86::VR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo118[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo119[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo120[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo121[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo122[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo123[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo124[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo125[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo126[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo127[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo128[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo129[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo130[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo131[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo132[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo133[] = { { X86::VR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo134[] = { { X86::VR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo135[] = { { X86::FR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo136[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo137[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo138[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo139[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo140[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo141[] = { { X86::VR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo142[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo143[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo144[] = { { X86::VR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo145[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo146[] = { { X86::GR16RegClassID, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo147[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo148[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo149[] = { { X86::CONTROL_REG_32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo150[] = { { X86::DEBUG_REGRegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo151[] = { { X86::GR32RegClassID, 0, 0 }, { X86::CONTROL_REG_32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo152[] = { { X86::GR32RegClassID, 0, 0 }, { X86::DEBUG_REGRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo153[] = { { X86::CONTROL_REG_64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo154[] = { { X86::DEBUG_REGRegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo155[] = { { X86::GR64RegClassID, 0, 0 }, { X86::CONTROL_REG_64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo156[] = { { X86::GR64RegClassID, 0, 0 }, { X86::DEBUG_REGRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo157[] = { { X86::GR64RegClassID, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo158[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo159[] = { { X86::VR128RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo160[] = { { X86::GR64_NOREXRegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOREX_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR8_NOREXRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo161[] = { { X86::GR8_NOREXRegClassID, 0, 0 }, { X86::GR64_NOREXRegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOREX_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo162[] = { { X86::GR8_NOREXRegClassID, 0, 0 }, { X86::GR8_NOREXRegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo163[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo164[] = { { X86::VR128RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo165[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo166[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo167[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo168[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo169[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo170[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo171[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo172[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo173[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo174[] = { { X86::GR32_NOREXRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo175[] = { { X86::GR32_NOREXRegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo176[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo177[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo178[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo179[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo180[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo181[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, }; static const TargetOperandInfo OperandInfo182[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo183[] = { { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo184[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo185[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo186[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo187[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo188[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo189[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo190[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo191[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo192[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo193[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo194[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo195[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo196[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo197[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo198[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo199[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, }; static const TargetOperandInfo OperandInfo200[] = { { X86::VR128RegClassID, 0, 0 }, }; static const TargetInstrDesc X86Insts[] = { { 0, 0, 0, 0, "PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #0 = PHI { 1, 0, 0, 0, "INLINEASM", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #1 = INLINEASM { 2, 1, 0, 0, "DBG_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo5 }, // Inst #2 = DBG_LABEL { 3, 1, 0, 0, "EH_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo5 }, // Inst #3 = EH_LABEL { 4, 1, 0, 0, "GC_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo5 }, // Inst #4 = GC_LABEL { 5, 0, 0, 0, "KILL", 0|(1<<TID::Variadic), 0, NULL, NULL, NULL, 0 }, // Inst #5 = KILL { 6, 3, 1, 0, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo76 }, // Inst #6 = EXTRACT_SUBREG { 7, 4, 1, 0, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo116 }, // Inst #7 = INSERT_SUBREG { 8, 1, 1, 0, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo5 }, // Inst #8 = IMPLICIT_DEF { 9, 4, 1, 0, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo196 }, // Inst #9 = SUBREG_TO_REG { 10, 3, 1, 0, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo76 }, // Inst #10 = COPY_TO_REGCLASS { 11, 0, 0, 0, "DBG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DBG_VALUE { 12, 0, 0, 0, "ABS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(225<<24), NULL, NULL, NULL, 0 }, // Inst #12 = ABS_F { 13, 2, 1, 0, "ABS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #13 = ABS_Fp32 { 14, 2, 1, 0, "ABS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #14 = ABS_Fp64 { 15, 2, 1, 0, "ABS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #15 = ABS_Fp80 { 16, 1, 0, 0, "ADC16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #16 = ADC16i16 { 17, 6, 0, 0, "ADC16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #17 = ADC16mi { 18, 6, 0, 0, "ADC16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #18 = ADC16mi8 { 19, 6, 0, 0, "ADC16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #19 = ADC16mr { 20, 3, 1, 0, "ADC16ri", 0, 0|18|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #20 = ADC16ri { 21, 3, 1, 0, "ADC16ri8", 0, 0|18|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #21 = ADC16ri8 { 22, 7, 1, 0, "ADC16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #22 = ADC16rm { 23, 3, 1, 0, "ADC16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #23 = ADC16rr { 24, 3, 1, 0, "ADC16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #24 = ADC16rr_REV { 25, 1, 0, 0, "ADC32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #25 = ADC32i32 { 26, 6, 0, 0, "ADC32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #26 = ADC32mi { 27, 6, 0, 0, "ADC32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #27 = ADC32mi8 { 28, 6, 0, 0, "ADC32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #28 = ADC32mr { 29, 3, 1, 0, "ADC32ri", 0, 0|18|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #29 = ADC32ri { 30, 3, 1, 0, "ADC32ri8", 0, 0|18|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #30 = ADC32ri8 { 31, 7, 1, 0, "ADC32rm", 0|(1<<TID::MayLoad), 0|6|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #31 = ADC32rm { 32, 3, 1, 0, "ADC32rr", 0|(1<<TID::Commutable), 0|3|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #32 = ADC32rr { 33, 3, 1, 0, "ADC32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #33 = ADC32rr_REV { 34, 1, 0, 0, "ADC64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #34 = ADC64i32 { 35, 6, 0, 0, "ADC64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #35 = ADC64mi32 { 36, 6, 0, 0, "ADC64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #36 = ADC64mi8 { 37, 6, 0, 0, "ADC64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #37 = ADC64mr { 38, 3, 1, 0, "ADC64ri32", 0, 0|18|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #38 = ADC64ri32 { 39, 3, 1, 0, "ADC64ri8", 0, 0|18|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #39 = ADC64ri8 { 40, 7, 1, 0, "ADC64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #40 = ADC64rm { 41, 3, 1, 0, "ADC64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #41 = ADC64rr { 42, 3, 1, 0, "ADC64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #42 = ADC64rr_REV { 43, 1, 0, 0, "ADC8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(20<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #43 = ADC8i8 { 44, 6, 0, 0, "ADC8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #44 = ADC8mi { 45, 6, 0, 0, "ADC8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(16<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #45 = ADC8mr { 46, 3, 1, 0, "ADC8ri", 0, 0|18|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #46 = ADC8ri { 47, 7, 1, 0, "ADC8rm", 0|(1<<TID::MayLoad), 0|6|(18<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #47 = ADC8rm { 48, 3, 1, 0, "ADC8rr", 0|(1<<TID::Commutable), 0|3|(16<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #48 = ADC8rr { 49, 3, 1, 0, "ADC8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(18<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #49 = ADC8rr_REV { 50, 1, 0, 0, "ADD16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #50 = ADD16i16 { 51, 6, 0, 0, "ADD16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #51 = ADD16mi { 52, 6, 0, 0, "ADD16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #52 = ADD16mi8 { 53, 6, 0, 0, "ADD16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #53 = ADD16mr { 54, 3, 1, 0, "ADD16mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #54 = ADD16mrmrr { 55, 3, 1, 0, "ADD16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #55 = ADD16ri { 56, 3, 1, 0, "ADD16ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #56 = ADD16ri8 { 57, 7, 1, 0, "ADD16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #57 = ADD16rm { 58, 3, 1, 0, "ADD16rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<6)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #58 = ADD16rr { 59, 1, 0, 0, "ADD32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #59 = ADD32i32 { 60, 6, 0, 0, "ADD32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #60 = ADD32mi { 61, 6, 0, 0, "ADD32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #61 = ADD32mi8 { 62, 6, 0, 0, "ADD32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #62 = ADD32mr { 63, 3, 1, 0, "ADD32mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #63 = ADD32mrmrr { 64, 3, 1, 0, "ADD32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #64 = ADD32ri { 65, 3, 1, 0, "ADD32ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #65 = ADD32ri8 { 66, 7, 1, 0, "ADD32rm", 0|(1<<TID::MayLoad), 0|6|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #66 = ADD32rm { 67, 3, 1, 0, "ADD32rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #67 = ADD32rr { 68, 1, 0, 0, "ADD64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #68 = ADD64i32 { 69, 6, 0, 0, "ADD64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #69 = ADD64mi32 { 70, 6, 0, 0, "ADD64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #70 = ADD64mi8 { 71, 6, 0, 0, "ADD64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #71 = ADD64mr { 72, 3, 1, 0, "ADD64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #72 = ADD64mrmrr { 73, 3, 1, 0, "ADD64ri32", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #73 = ADD64ri32 { 74, 3, 1, 0, "ADD64ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #74 = ADD64ri8 { 75, 7, 1, 0, "ADD64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #75 = ADD64rm { 76, 3, 1, 0, "ADD64rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<12)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #76 = ADD64rr { 77, 1, 0, 0, "ADD8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(4<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #77 = ADD8i8 { 78, 6, 0, 0, "ADD8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #78 = ADD8mi { 79, 6, 0, 0, "ADD8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4, NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #79 = ADD8mr { 80, 3, 1, 0, "ADD8mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(2<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #80 = ADD8mrmrr { 81, 3, 1, 0, "ADD8ri", 0, 0|16|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #81 = ADD8ri { 82, 7, 1, 0, "ADD8rm", 0|(1<<TID::MayLoad), 0|6|(2<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #82 = ADD8rm { 83, 3, 1, 0, "ADD8rr", 0|(1<<TID::Commutable), 0|3, NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #83 = ADD8rr { 84, 7, 1, 0, "ADDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #84 = ADDPDrm { 85, 3, 1, 0, "ADDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #85 = ADDPDrr { 86, 7, 1, 0, "ADDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #86 = ADDPSrm { 87, 3, 1, 0, "ADDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #87 = ADDPSrr { 88, 7, 1, 0, "ADDSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #88 = ADDSDrm { 89, 7, 1, 0, "ADDSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #89 = ADDSDrm_Int { 90, 3, 1, 0, "ADDSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #90 = ADDSDrr { 91, 3, 1, 0, "ADDSDrr_Int", 0, 0|5|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #91 = ADDSDrr_Int { 92, 7, 1, 0, "ADDSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #92 = ADDSSrm { 93, 7, 1, 0, "ADDSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #93 = ADDSSrm_Int { 94, 3, 1, 0, "ADDSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #94 = ADDSSrr { 95, 3, 1, 0, "ADDSSrr_Int", 0, 0|5|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #95 = ADDSSrr_Int { 96, 7, 1, 0, "ADDSUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(208<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #96 = ADDSUBPDrm { 97, 3, 1, 0, "ADDSUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(208<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #97 = ADDSUBPDrr { 98, 7, 1, 0, "ADDSUBPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(208<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #98 = ADDSUBPSrm { 99, 3, 1, 0, "ADDSUBPSrr", 0, 0|5|(11<<8)|(208<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #99 = ADDSUBPSrr { 100, 5, 0, 0, "ADD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #100 = ADD_F32m { 101, 5, 0, 0, "ADD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #101 = ADD_F64m { 102, 5, 0, 0, "ADD_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #102 = ADD_FI16m { 103, 5, 0, 0, "ADD_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #103 = ADD_FI32m { 104, 1, 0, 0, "ADD_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #104 = ADD_FPrST0 { 105, 1, 0, 0, "ADD_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #105 = ADD_FST0r { 106, 3, 1, 0, "ADD_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #106 = ADD_Fp32 { 107, 7, 1, 0, "ADD_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #107 = ADD_Fp32m { 108, 3, 1, 0, "ADD_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #108 = ADD_Fp64 { 109, 7, 1, 0, "ADD_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #109 = ADD_Fp64m { 110, 7, 1, 0, "ADD_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #110 = ADD_Fp64m32 { 111, 3, 1, 0, "ADD_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #111 = ADD_Fp80 { 112, 7, 1, 0, "ADD_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #112 = ADD_Fp80m32 { 113, 7, 1, 0, "ADD_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #113 = ADD_Fp80m64 { 114, 7, 1, 0, "ADD_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #114 = ADD_FpI16m32 { 115, 7, 1, 0, "ADD_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #115 = ADD_FpI16m64 { 116, 7, 1, 0, "ADD_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #116 = ADD_FpI16m80 { 117, 7, 1, 0, "ADD_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #117 = ADD_FpI32m32 { 118, 7, 1, 0, "ADD_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #118 = ADD_FpI32m64 { 119, 7, 1, 0, "ADD_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #119 = ADD_FpI32m80 { 120, 1, 0, 0, "ADD_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #120 = ADD_FrST0 { 121, 1, 0, 0, "ADJCALLSTACKDOWN32", 0, 0, ImplicitList2, ImplicitList3, Barriers1, OperandInfo5 }, // Inst #121 = ADJCALLSTACKDOWN32 { 122, 1, 0, 0, "ADJCALLSTACKDOWN64", 0, 0, ImplicitList4, ImplicitList5, Barriers1, OperandInfo5 }, // Inst #122 = ADJCALLSTACKDOWN64 { 123, 2, 0, 0, "ADJCALLSTACKUP32", 0, 0, ImplicitList2, ImplicitList3, Barriers1, OperandInfo38 }, // Inst #123 = ADJCALLSTACKUP32 { 124, 2, 0, 0, "ADJCALLSTACKUP64", 0, 0, ImplicitList4, ImplicitList5, Barriers1, OperandInfo38 }, // Inst #124 = ADJCALLSTACKUP64 { 125, 1, 0, 0, "AND16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #125 = AND16i16 { 126, 6, 0, 0, "AND16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #126 = AND16mi { 127, 6, 0, 0, "AND16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #127 = AND16mi8 { 128, 6, 0, 0, "AND16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #128 = AND16mr { 129, 3, 1, 0, "AND16ri", 0, 0|20|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #129 = AND16ri { 130, 3, 1, 0, "AND16ri8", 0, 0|20|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #130 = AND16ri8 { 131, 7, 1, 0, "AND16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #131 = AND16rm { 132, 3, 1, 0, "AND16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #132 = AND16rr { 133, 3, 1, 0, "AND16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #133 = AND16rr_REV { 134, 1, 0, 0, "AND32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #134 = AND32i32 { 135, 6, 0, 0, "AND32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #135 = AND32mi { 136, 6, 0, 0, "AND32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #136 = AND32mi8 { 137, 6, 0, 0, "AND32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #137 = AND32mr { 138, 3, 1, 0, "AND32ri", 0, 0|20|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #138 = AND32ri { 139, 3, 1, 0, "AND32ri8", 0, 0|20|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #139 = AND32ri8 { 140, 7, 1, 0, "AND32rm", 0|(1<<TID::MayLoad), 0|6|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #140 = AND32rm { 141, 3, 1, 0, "AND32rr", 0|(1<<TID::Commutable), 0|3|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #141 = AND32rr { 142, 3, 1, 0, "AND32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #142 = AND32rr_REV { 143, 1, 0, 0, "AND64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #143 = AND64i32 { 144, 6, 0, 0, "AND64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #144 = AND64mi32 { 145, 6, 0, 0, "AND64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #145 = AND64mi8 { 146, 6, 0, 0, "AND64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #146 = AND64mr { 147, 3, 1, 0, "AND64ri32", 0, 0|20|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #147 = AND64ri32 { 148, 3, 1, 0, "AND64ri8", 0, 0|20|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #148 = AND64ri8 { 149, 7, 1, 0, "AND64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #149 = AND64rm { 150, 3, 1, 0, "AND64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #150 = AND64rr { 151, 3, 1, 0, "AND64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #151 = AND64rr_REV { 152, 1, 0, 0, "AND8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(36<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #152 = AND8i8 { 153, 6, 0, 0, "AND8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #153 = AND8mi { 154, 6, 0, 0, "AND8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(32<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #154 = AND8mr { 155, 3, 1, 0, "AND8ri", 0, 0|20|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #155 = AND8ri { 156, 7, 1, 0, "AND8rm", 0|(1<<TID::MayLoad), 0|6|(34<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #156 = AND8rm { 157, 3, 1, 0, "AND8rr", 0|(1<<TID::Commutable), 0|3|(32<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #157 = AND8rr { 158, 3, 1, 0, "AND8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(34<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #158 = AND8rr_REV { 159, 7, 1, 0, "ANDNPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #159 = ANDNPDrm { 160, 3, 1, 0, "ANDNPDrr", 0, 0|5|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #160 = ANDNPDrr { 161, 7, 1, 0, "ANDNPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #161 = ANDNPSrm { 162, 3, 1, 0, "ANDNPSrr", 0, 0|5|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #162 = ANDNPSrr { 163, 7, 1, 0, "ANDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #163 = ANDPDrm { 164, 3, 1, 0, "ANDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #164 = ANDPDrr { 165, 7, 1, 0, "ANDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #165 = ANDPSrm { 166, 3, 1, 0, "ANDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #166 = ANDPSrr { 167, 9, 2, 0, "ATOMADD6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #167 = ATOMADD6432 { 168, 7, 1, 0, "ATOMAND16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #168 = ATOMAND16 { 169, 7, 1, 0, "ATOMAND32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #169 = ATOMAND32 { 170, 7, 1, 0, "ATOMAND64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #170 = ATOMAND64 { 171, 9, 2, 0, "ATOMAND6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #171 = ATOMAND6432 { 172, 7, 1, 0, "ATOMAND8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #172 = ATOMAND8 { 173, 7, 1, 0, "ATOMMAX16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #173 = ATOMMAX16 { 174, 7, 1, 0, "ATOMMAX32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #174 = ATOMMAX32 { 175, 7, 1, 0, "ATOMMAX64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #175 = ATOMMAX64 { 176, 7, 1, 0, "ATOMMIN16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #176 = ATOMMIN16 { 177, 7, 1, 0, "ATOMMIN32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #177 = ATOMMIN32 { 178, 7, 1, 0, "ATOMMIN64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #178 = ATOMMIN64 { 179, 7, 1, 0, "ATOMNAND16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #179 = ATOMNAND16 { 180, 7, 1, 0, "ATOMNAND32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #180 = ATOMNAND32 { 181, 7, 1, 0, "ATOMNAND64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #181 = ATOMNAND64 { 182, 9, 2, 0, "ATOMNAND6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #182 = ATOMNAND6432 { 183, 7, 1, 0, "ATOMNAND8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #183 = ATOMNAND8 { 184, 7, 1, 0, "ATOMOR16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #184 = ATOMOR16 { 185, 7, 1, 0, "ATOMOR32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #185 = ATOMOR32 { 186, 7, 1, 0, "ATOMOR64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #186 = ATOMOR64 { 187, 9, 2, 0, "ATOMOR6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #187 = ATOMOR6432 { 188, 7, 1, 0, "ATOMOR8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #188 = ATOMOR8 { 189, 9, 2, 0, "ATOMSUB6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #189 = ATOMSUB6432 { 190, 9, 2, 0, "ATOMSWAP6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #190 = ATOMSWAP6432 { 191, 7, 1, 0, "ATOMUMAX16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #191 = ATOMUMAX16 { 192, 7, 1, 0, "ATOMUMAX32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #192 = ATOMUMAX32 { 193, 7, 1, 0, "ATOMUMAX64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #193 = ATOMUMAX64 { 194, 7, 1, 0, "ATOMUMIN16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #194 = ATOMUMIN16 { 195, 7, 1, 0, "ATOMUMIN32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #195 = ATOMUMIN32 { 196, 7, 1, 0, "ATOMUMIN64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #196 = ATOMUMIN64 { 197, 7, 1, 0, "ATOMXOR16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #197 = ATOMXOR16 { 198, 7, 1, 0, "ATOMXOR32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #198 = ATOMXOR32 { 199, 7, 1, 0, "ATOMXOR64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #199 = ATOMXOR64 { 200, 9, 2, 0, "ATOMXOR6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #200 = ATOMXOR6432 { 201, 7, 1, 0, "ATOMXOR8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #201 = ATOMXOR8 { 202, 8, 1, 0, "BLENDPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(13<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #202 = BLENDPDrmi { 203, 4, 1, 0, "BLENDPDrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(13<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #203 = BLENDPDrri { 204, 8, 1, 0, "BLENDPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(12<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #204 = BLENDPSrmi { 205, 4, 1, 0, "BLENDPSrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(12<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #205 = BLENDPSrri { 206, 7, 1, 0, "BLENDVPDrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(21<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #206 = BLENDVPDrm0 { 207, 3, 1, 0, "BLENDVPDrr0", 0, 0|5|(1<<6)|(13<<8)|(21<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #207 = BLENDVPDrr0 { 208, 7, 1, 0, "BLENDVPSrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(20<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #208 = BLENDVPSrm0 { 209, 3, 1, 0, "BLENDVPSrr0", 0, 0|5|(1<<6)|(13<<8)|(20<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #209 = BLENDVPSrr0 { 210, 6, 1, 0, "BSF16rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #210 = BSF16rm { 211, 2, 1, 0, "BSF16rr", 0, 0|5|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #211 = BSF16rr { 212, 6, 1, 0, "BSF32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #212 = BSF32rm { 213, 2, 1, 0, "BSF32rr", 0, 0|5|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #213 = BSF32rr { 214, 6, 1, 0, "BSF64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #214 = BSF64rm { 215, 2, 1, 0, "BSF64rr", 0, 0|5|(1<<8)|(1<<12)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #215 = BSF64rr { 216, 6, 1, 0, "BSR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #216 = BSR16rm { 217, 2, 1, 0, "BSR16rr", 0, 0|5|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #217 = BSR16rr { 218, 6, 1, 0, "BSR32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #218 = BSR32rm { 219, 2, 1, 0, "BSR32rr", 0, 0|5|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #219 = BSR32rr { 220, 6, 1, 0, "BSR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #220 = BSR64rm { 221, 2, 1, 0, "BSR64rr", 0, 0|5|(1<<8)|(1<<12)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #221 = BSR64rr { 222, 2, 1, 0, "BSWAP32r", 0, 0|2|(1<<8)|(200<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #222 = BSWAP32r { 223, 2, 1, 0, "BSWAP64r", 0, 0|2|(1<<8)|(1<<12)|(200<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #223 = BSWAP64r { 224, 6, 0, 0, "BT16mi8", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #224 = BT16mi8 { 225, 6, 0, 0, "BT16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #225 = BT16mr { 226, 2, 0, 0, "BT16ri8", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #226 = BT16ri8 { 227, 2, 0, 0, "BT16rr", 0, 0|3|(1<<6)|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #227 = BT16rr { 228, 6, 0, 0, "BT32mi8", 0|(1<<TID::MayLoad), 0|28|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #228 = BT32mi8 { 229, 6, 0, 0, "BT32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #229 = BT32mr { 230, 2, 0, 0, "BT32ri8", 0, 0|20|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #230 = BT32ri8 { 231, 2, 0, 0, "BT32rr", 0, 0|3|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #231 = BT32rr { 232, 6, 0, 0, "BT64mi8", 0|(1<<TID::MayLoad), 0|28|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #232 = BT64mi8 { 233, 6, 0, 0, "BT64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #233 = BT64mr { 234, 2, 0, 0, "BT64ri8", 0, 0|20|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #234 = BT64ri8 { 235, 2, 0, 0, "BT64rr", 0, 0|3|(1<<8)|(1<<12)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #235 = BT64rr { 236, 6, 0, 0, "BTC16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #236 = BTC16mi8 { 237, 6, 0, 0, "BTC16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #237 = BTC16mr { 238, 2, 0, 0, "BTC16ri8", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #238 = BTC16ri8 { 239, 2, 0, 0, "BTC16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #239 = BTC16rr { 240, 6, 0, 0, "BTC32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #240 = BTC32mi8 { 241, 6, 0, 0, "BTC32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #241 = BTC32mr { 242, 2, 0, 0, "BTC32ri8", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #242 = BTC32ri8 { 243, 2, 0, 0, "BTC32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #243 = BTC32rr { 244, 6, 0, 0, "BTC64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #244 = BTC64mi8 { 245, 6, 0, 0, "BTC64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #245 = BTC64mr { 246, 2, 0, 0, "BTC64ri8", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #246 = BTC64ri8 { 247, 2, 0, 0, "BTC64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #247 = BTC64rr { 248, 6, 0, 0, "BTR16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #248 = BTR16mi8 { 249, 6, 0, 0, "BTR16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #249 = BTR16mr { 250, 2, 0, 0, "BTR16ri8", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #250 = BTR16ri8 { 251, 2, 0, 0, "BTR16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #251 = BTR16rr { 252, 6, 0, 0, "BTR32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #252 = BTR32mi8 { 253, 6, 0, 0, "BTR32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #253 = BTR32mr { 254, 2, 0, 0, "BTR32ri8", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #254 = BTR32ri8 { 255, 2, 0, 0, "BTR32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #255 = BTR32rr { 256, 6, 0, 0, "BTR64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #256 = BTR64mi8 { 257, 6, 0, 0, "BTR64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #257 = BTR64mr { 258, 2, 0, 0, "BTR64ri8", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #258 = BTR64ri8 { 259, 2, 0, 0, "BTR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #259 = BTR64rr { 260, 6, 0, 0, "BTS16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #260 = BTS16mi8 { 261, 6, 0, 0, "BTS16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #261 = BTS16mr { 262, 2, 0, 0, "BTS16ri8", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #262 = BTS16ri8 { 263, 2, 0, 0, "BTS16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #263 = BTS16rr { 264, 6, 0, 0, "BTS32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #264 = BTS32mi8 { 265, 6, 0, 0, "BTS32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #265 = BTS32mr { 266, 2, 0, 0, "BTS32ri8", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #266 = BTS32ri8 { 267, 2, 0, 0, "BTS32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #267 = BTS32rr { 268, 6, 0, 0, "BTS64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #268 = BTS64mi8 { 269, 6, 0, 0, "BTS64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #269 = BTS64mr { 270, 2, 0, 0, "BTS64ri8", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #270 = BTS64ri8 { 271, 2, 0, 0, "BTS64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #271 = BTS64rr { 272, 5, 0, 0, "CALL32m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #272 = CALL32m { 273, 1, 0, 0, "CALL32r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo57 }, // Inst #273 = CALL32r { 274, 5, 0, 0, "CALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo30 }, // Inst #274 = CALL64m { 275, 1, 0, 0, "CALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(232<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo5 }, // Inst #275 = CALL64pcrel32 { 276, 1, 0, 0, "CALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo58 }, // Inst #276 = CALL64r { 277, 1, 0, 0, "CALLpcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(5<<13)|(232<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo5 }, // Inst #277 = CALLpcrel32 { 278, 0, 0, 0, "CBW", 0, 0|1|(1<<6)|(152<<24), ImplicitList11, ImplicitList12, NULL, 0 }, // Inst #278 = CBW { 279, 0, 0, 0, "CDQ", 0, 0|1|(153<<24), ImplicitList13, ImplicitList14, Barriers5, 0 }, // Inst #279 = CDQ { 280, 0, 0, 0, "CDQE", 0, 0|1|(1<<12)|(152<<24), ImplicitList13, ImplicitList15, NULL, 0 }, // Inst #280 = CDQE { 281, 0, 0, 0, "CHS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(224<<24), NULL, NULL, NULL, 0 }, // Inst #281 = CHS_F { 282, 2, 1, 0, "CHS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #282 = CHS_Fp32 { 283, 2, 1, 0, "CHS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #283 = CHS_Fp64 { 284, 2, 1, 0, "CHS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #284 = CHS_Fp80 { 285, 0, 0, 0, "CLC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(248<<24), NULL, NULL, NULL, 0 }, // Inst #285 = CLC { 286, 0, 0, 0, "CLD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(252<<24), NULL, NULL, NULL, 0 }, // Inst #286 = CLD { 287, 5, 0, 0, "CLFLUSH", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #287 = CLFLUSH { 288, 0, 0, 0, "CLI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(250<<24), NULL, NULL, NULL, 0 }, // Inst #288 = CLI { 289, 0, 0, 0, "CLTS", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(6<<24), NULL, NULL, NULL, 0 }, // Inst #289 = CLTS { 290, 0, 0, 0, "CMC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(245<<24), NULL, NULL, NULL, 0 }, // Inst #290 = CMC { 291, 7, 1, 0, "CMOVA16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #291 = CMOVA16rm { 292, 3, 1, 0, "CMOVA16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #292 = CMOVA16rr { 293, 7, 1, 0, "CMOVA32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #293 = CMOVA32rm { 294, 3, 1, 0, "CMOVA32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #294 = CMOVA32rr { 295, 7, 1, 0, "CMOVA64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #295 = CMOVA64rm { 296, 3, 1, 0, "CMOVA64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #296 = CMOVA64rr { 297, 7, 1, 0, "CMOVAE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #297 = CMOVAE16rm { 298, 3, 1, 0, "CMOVAE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #298 = CMOVAE16rr { 299, 7, 1, 0, "CMOVAE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #299 = CMOVAE32rm { 300, 3, 1, 0, "CMOVAE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #300 = CMOVAE32rr { 301, 7, 1, 0, "CMOVAE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #301 = CMOVAE64rm { 302, 3, 1, 0, "CMOVAE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #302 = CMOVAE64rr { 303, 7, 1, 0, "CMOVB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #303 = CMOVB16rm { 304, 3, 1, 0, "CMOVB16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #304 = CMOVB16rr { 305, 7, 1, 0, "CMOVB32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #305 = CMOVB32rm { 306, 3, 1, 0, "CMOVB32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #306 = CMOVB32rr { 307, 7, 1, 0, "CMOVB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #307 = CMOVB64rm { 308, 3, 1, 0, "CMOVB64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #308 = CMOVB64rr { 309, 7, 1, 0, "CMOVBE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #309 = CMOVBE16rm { 310, 3, 1, 0, "CMOVBE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #310 = CMOVBE16rr { 311, 7, 1, 0, "CMOVBE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #311 = CMOVBE32rm { 312, 3, 1, 0, "CMOVBE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #312 = CMOVBE32rr { 313, 7, 1, 0, "CMOVBE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #313 = CMOVBE64rm { 314, 3, 1, 0, "CMOVBE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #314 = CMOVBE64rr { 315, 1, 1, 0, "CMOVBE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #315 = CMOVBE_F { 316, 3, 1, 0, "CMOVBE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #316 = CMOVBE_Fp32 { 317, 3, 1, 0, "CMOVBE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #317 = CMOVBE_Fp64 { 318, 3, 1, 0, "CMOVBE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #318 = CMOVBE_Fp80 { 319, 1, 1, 0, "CMOVB_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #319 = CMOVB_F { 320, 3, 1, 0, "CMOVB_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #320 = CMOVB_Fp32 { 321, 3, 1, 0, "CMOVB_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #321 = CMOVB_Fp64 { 322, 3, 1, 0, "CMOVB_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #322 = CMOVB_Fp80 { 323, 7, 1, 0, "CMOVE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #323 = CMOVE16rm { 324, 3, 1, 0, "CMOVE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #324 = CMOVE16rr { 325, 7, 1, 0, "CMOVE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #325 = CMOVE32rm { 326, 3, 1, 0, "CMOVE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #326 = CMOVE32rr { 327, 7, 1, 0, "CMOVE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #327 = CMOVE64rm { 328, 3, 1, 0, "CMOVE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #328 = CMOVE64rr { 329, 1, 1, 0, "CMOVE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #329 = CMOVE_F { 330, 3, 1, 0, "CMOVE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #330 = CMOVE_Fp32 { 331, 3, 1, 0, "CMOVE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #331 = CMOVE_Fp64 { 332, 3, 1, 0, "CMOVE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #332 = CMOVE_Fp80 { 333, 7, 1, 0, "CMOVG16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #333 = CMOVG16rm { 334, 3, 1, 0, "CMOVG16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #334 = CMOVG16rr { 335, 7, 1, 0, "CMOVG32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #335 = CMOVG32rm { 336, 3, 1, 0, "CMOVG32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #336 = CMOVG32rr { 337, 7, 1, 0, "CMOVG64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #337 = CMOVG64rm { 338, 3, 1, 0, "CMOVG64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #338 = CMOVG64rr { 339, 7, 1, 0, "CMOVGE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #339 = CMOVGE16rm { 340, 3, 1, 0, "CMOVGE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #340 = CMOVGE16rr { 341, 7, 1, 0, "CMOVGE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #341 = CMOVGE32rm { 342, 3, 1, 0, "CMOVGE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #342 = CMOVGE32rr { 343, 7, 1, 0, "CMOVGE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #343 = CMOVGE64rm { 344, 3, 1, 0, "CMOVGE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #344 = CMOVGE64rr { 345, 7, 1, 0, "CMOVL16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #345 = CMOVL16rm { 346, 3, 1, 0, "CMOVL16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #346 = CMOVL16rr { 347, 7, 1, 0, "CMOVL32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #347 = CMOVL32rm { 348, 3, 1, 0, "CMOVL32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #348 = CMOVL32rr { 349, 7, 1, 0, "CMOVL64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #349 = CMOVL64rm { 350, 3, 1, 0, "CMOVL64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #350 = CMOVL64rr { 351, 7, 1, 0, "CMOVLE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #351 = CMOVLE16rm { 352, 3, 1, 0, "CMOVLE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #352 = CMOVLE16rr { 353, 7, 1, 0, "CMOVLE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #353 = CMOVLE32rm { 354, 3, 1, 0, "CMOVLE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #354 = CMOVLE32rr { 355, 7, 1, 0, "CMOVLE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #355 = CMOVLE64rm { 356, 3, 1, 0, "CMOVLE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #356 = CMOVLE64rr { 357, 1, 1, 0, "CMOVNBE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #357 = CMOVNBE_F { 358, 3, 1, 0, "CMOVNBE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #358 = CMOVNBE_Fp32 { 359, 3, 1, 0, "CMOVNBE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #359 = CMOVNBE_Fp64 { 360, 3, 1, 0, "CMOVNBE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #360 = CMOVNBE_Fp80 { 361, 1, 1, 0, "CMOVNB_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #361 = CMOVNB_F { 362, 3, 1, 0, "CMOVNB_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #362 = CMOVNB_Fp32 { 363, 3, 1, 0, "CMOVNB_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #363 = CMOVNB_Fp64 { 364, 3, 1, 0, "CMOVNB_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #364 = CMOVNB_Fp80 { 365, 7, 1, 0, "CMOVNE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #365 = CMOVNE16rm { 366, 3, 1, 0, "CMOVNE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #366 = CMOVNE16rr { 367, 7, 1, 0, "CMOVNE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #367 = CMOVNE32rm { 368, 3, 1, 0, "CMOVNE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #368 = CMOVNE32rr { 369, 7, 1, 0, "CMOVNE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #369 = CMOVNE64rm { 370, 3, 1, 0, "CMOVNE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #370 = CMOVNE64rr { 371, 1, 1, 0, "CMOVNE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #371 = CMOVNE_F { 372, 3, 1, 0, "CMOVNE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #372 = CMOVNE_Fp32 { 373, 3, 1, 0, "CMOVNE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #373 = CMOVNE_Fp64 { 374, 3, 1, 0, "CMOVNE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #374 = CMOVNE_Fp80 { 375, 7, 1, 0, "CMOVNO16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #375 = CMOVNO16rm { 376, 3, 1, 0, "CMOVNO16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #376 = CMOVNO16rr { 377, 7, 1, 0, "CMOVNO32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #377 = CMOVNO32rm { 378, 3, 1, 0, "CMOVNO32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #378 = CMOVNO32rr { 379, 7, 1, 0, "CMOVNO64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #379 = CMOVNO64rm { 380, 3, 1, 0, "CMOVNO64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #380 = CMOVNO64rr { 381, 7, 1, 0, "CMOVNP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #381 = CMOVNP16rm { 382, 3, 1, 0, "CMOVNP16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #382 = CMOVNP16rr { 383, 7, 1, 0, "CMOVNP32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #383 = CMOVNP32rm { 384, 3, 1, 0, "CMOVNP32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #384 = CMOVNP32rr { 385, 7, 1, 0, "CMOVNP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #385 = CMOVNP64rm { 386, 3, 1, 0, "CMOVNP64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #386 = CMOVNP64rr { 387, 1, 1, 0, "CMOVNP_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #387 = CMOVNP_F { 388, 3, 1, 0, "CMOVNP_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #388 = CMOVNP_Fp32 { 389, 3, 1, 0, "CMOVNP_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #389 = CMOVNP_Fp64 { 390, 3, 1, 0, "CMOVNP_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #390 = CMOVNP_Fp80 { 391, 7, 1, 0, "CMOVNS16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #391 = CMOVNS16rm { 392, 3, 1, 0, "CMOVNS16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #392 = CMOVNS16rr { 393, 7, 1, 0, "CMOVNS32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #393 = CMOVNS32rm { 394, 3, 1, 0, "CMOVNS32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #394 = CMOVNS32rr { 395, 7, 1, 0, "CMOVNS64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #395 = CMOVNS64rm { 396, 3, 1, 0, "CMOVNS64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #396 = CMOVNS64rr { 397, 7, 1, 0, "CMOVO16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #397 = CMOVO16rm { 398, 3, 1, 0, "CMOVO16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #398 = CMOVO16rr { 399, 7, 1, 0, "CMOVO32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #399 = CMOVO32rm { 400, 3, 1, 0, "CMOVO32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #400 = CMOVO32rr { 401, 7, 1, 0, "CMOVO64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #401 = CMOVO64rm { 402, 3, 1, 0, "CMOVO64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #402 = CMOVO64rr { 403, 7, 1, 0, "CMOVP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #403 = CMOVP16rm { 404, 3, 1, 0, "CMOVP16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #404 = CMOVP16rr { 405, 7, 1, 0, "CMOVP32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #405 = CMOVP32rm { 406, 3, 1, 0, "CMOVP32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #406 = CMOVP32rr { 407, 7, 1, 0, "CMOVP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #407 = CMOVP64rm { 408, 3, 1, 0, "CMOVP64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #408 = CMOVP64rr { 409, 1, 1, 0, "CMOVP_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #409 = CMOVP_F { 410, 3, 1, 0, "CMOVP_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #410 = CMOVP_Fp32 { 411, 3, 1, 0, "CMOVP_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #411 = CMOVP_Fp64 { 412, 3, 1, 0, "CMOVP_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #412 = CMOVP_Fp80 { 413, 7, 1, 0, "CMOVS16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #413 = CMOVS16rm { 414, 3, 1, 0, "CMOVS16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #414 = CMOVS16rr { 415, 7, 1, 0, "CMOVS32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #415 = CMOVS32rm { 416, 3, 1, 0, "CMOVS32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #416 = CMOVS32rr { 417, 7, 1, 0, "CMOVS64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #417 = CMOVS64rm { 418, 3, 1, 0, "CMOVS64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #418 = CMOVS64rr { 419, 4, 1, 0, "CMOV_FR32", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo62 }, // Inst #419 = CMOV_FR32 { 420, 4, 1, 0, "CMOV_FR64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo63 }, // Inst #420 = CMOV_FR64 { 421, 4, 1, 0, "CMOV_GR8", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, ImplicitList1, Barriers1, OperandInfo64 }, // Inst #421 = CMOV_GR8 { 422, 4, 1, 0, "CMOV_V1I64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo65 }, // Inst #422 = CMOV_V1I64 { 423, 4, 1, 0, "CMOV_V2F64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #423 = CMOV_V2F64 { 424, 4, 1, 0, "CMOV_V2I64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #424 = CMOV_V2I64 { 425, 4, 1, 0, "CMOV_V4F32", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #425 = CMOV_V4F32 { 426, 1, 0, 0, "CMP16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #426 = CMP16i16 { 427, 6, 0, 0, "CMP16mi", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #427 = CMP16mi { 428, 6, 0, 0, "CMP16mi8", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #428 = CMP16mi8 { 429, 6, 0, 0, "CMP16mr", 0|(1<<TID::MayLoad), 0|4|(1<<6)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #429 = CMP16mr { 430, 2, 0, 0, "CMP16mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #430 = CMP16mrmrr { 431, 2, 0, 0, "CMP16ri", 0, 0|23|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #431 = CMP16ri { 432, 2, 0, 0, "CMP16ri8", 0, 0|23|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #432 = CMP16ri8 { 433, 6, 0, 0, "CMP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #433 = CMP16rm { 434, 2, 0, 0, "CMP16rr", 0, 0|3|(1<<6)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #434 = CMP16rr { 435, 1, 0, 0, "CMP32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #435 = CMP32i32 { 436, 6, 0, 0, "CMP32mi", 0|(1<<TID::MayLoad), 0|31|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #436 = CMP32mi { 437, 6, 0, 0, "CMP32mi8", 0|(1<<TID::MayLoad), 0|31|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #437 = CMP32mi8 { 438, 6, 0, 0, "CMP32mr", 0|(1<<TID::MayLoad), 0|4|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #438 = CMP32mr { 439, 2, 0, 0, "CMP32mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #439 = CMP32mrmrr { 440, 2, 0, 0, "CMP32ri", 0, 0|23|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #440 = CMP32ri { 441, 2, 0, 0, "CMP32ri8", 0, 0|23|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #441 = CMP32ri8 { 442, 6, 0, 0, "CMP32rm", 0|(1<<TID::MayLoad), 0|6|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #442 = CMP32rm { 443, 2, 0, 0, "CMP32rr", 0, 0|3|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #443 = CMP32rr { 444, 1, 0, 0, "CMP64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #444 = CMP64i32 { 445, 6, 0, 0, "CMP64mi32", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #445 = CMP64mi32 { 446, 6, 0, 0, "CMP64mi8", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #446 = CMP64mi8 { 447, 6, 0, 0, "CMP64mr", 0|(1<<TID::MayLoad), 0|4|(1<<12)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #447 = CMP64mr { 448, 2, 0, 0, "CMP64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #448 = CMP64mrmrr { 449, 2, 0, 0, "CMP64ri32", 0, 0|23|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #449 = CMP64ri32 { 450, 2, 0, 0, "CMP64ri8", 0, 0|23|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #450 = CMP64ri8 { 451, 6, 0, 0, "CMP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #451 = CMP64rm { 452, 2, 0, 0, "CMP64rr", 0, 0|3|(1<<12)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #452 = CMP64rr { 453, 1, 0, 0, "CMP8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(60<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #453 = CMP8i8 { 454, 6, 0, 0, "CMP8mi", 0|(1<<TID::MayLoad), 0|31|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #454 = CMP8mi { 455, 6, 0, 0, "CMP8mr", 0|(1<<TID::MayLoad), 0|4|(56<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #455 = CMP8mr { 456, 2, 0, 0, "CMP8mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(58<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #456 = CMP8mrmrr { 457, 2, 0, 0, "CMP8ri", 0, 0|23|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #457 = CMP8ri { 458, 6, 0, 0, "CMP8rm", 0|(1<<TID::MayLoad), 0|6|(58<<24), NULL, ImplicitList1, Barriers1, OperandInfo69 }, // Inst #458 = CMP8rm { 459, 2, 0, 0, "CMP8rr", 0, 0|3|(56<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #459 = CMP8rr { 460, 8, 1, 0, "CMPPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #460 = CMPPDrmi { 461, 4, 1, 0, "CMPPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #461 = CMPPDrri { 462, 8, 1, 0, "CMPPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #462 = CMPPSrmi { 463, 4, 1, 0, "CMPPSrri", 0, 0|5|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #463 = CMPPSrri { 464, 0, 0, 0, "CMPS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(167<<24), NULL, NULL, NULL, 0 }, // Inst #464 = CMPS16 { 465, 0, 0, 0, "CMPS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(167<<24), NULL, NULL, NULL, 0 }, // Inst #465 = CMPS32 { 466, 0, 0, 0, "CMPS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(167<<24), NULL, NULL, NULL, 0 }, // Inst #466 = CMPS64 { 467, 0, 0, 0, "CMPS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(166<<24), NULL, NULL, NULL, 0 }, // Inst #467 = CMPS8 { 468, 8, 1, 0, "CMPSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo70 }, // Inst #468 = CMPSDrm { 469, 4, 1, 0, "CMPSDrr", 0, 0|5|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo71 }, // Inst #469 = CMPSDrr { 470, 8, 1, 0, "CMPSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo72 }, // Inst #470 = CMPSSrm { 471, 4, 1, 0, "CMPSSrr", 0, 0|5|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #471 = CMPSSrr { 472, 5, 0, 0, "CMPXCHG16B", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(1<<12)|(199<<24), ImplicitList16, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #472 = CMPXCHG16B { 473, 6, 0, 0, "CMPXCHG16rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #473 = CMPXCHG16rm { 474, 2, 1, 0, "CMPXCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #474 = CMPXCHG16rr { 475, 6, 0, 0, "CMPXCHG32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #475 = CMPXCHG32rm { 476, 2, 1, 0, "CMPXCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #476 = CMPXCHG32rr { 477, 6, 0, 0, "CMPXCHG64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(177<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #477 = CMPXCHG64rm { 478, 2, 1, 0, "CMPXCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(177<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #478 = CMPXCHG64rr { 479, 5, 0, 0, "CMPXCHG8B", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(199<<24), ImplicitList6, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #479 = CMPXCHG8B { 480, 6, 0, 0, "CMPXCHG8rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(176<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #480 = CMPXCHG8rm { 481, 2, 1, 0, "CMPXCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(176<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #481 = CMPXCHG8rr { 482, 6, 0, 0, "COMISDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(47<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #482 = COMISDrm { 483, 2, 0, 0, "COMISDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(47<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #483 = COMISDrr { 484, 6, 0, 0, "COMISSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #484 = COMISSrm { 485, 2, 0, 0, "COMISSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #485 = COMISSrr { 486, 1, 0, 0, "COMP_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #486 = COMP_FST0r { 487, 1, 0, 0, "COM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #487 = COM_FIPr { 488, 1, 0, 0, "COM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #488 = COM_FIr { 489, 1, 0, 0, "COM_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #489 = COM_FST0r { 490, 0, 0, 0, "COS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(255<<24), NULL, NULL, NULL, 0 }, // Inst #490 = COS_F { 491, 2, 1, 0, "COS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #491 = COS_Fp32 { 492, 2, 1, 0, "COS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #492 = COS_Fp64 { 493, 2, 1, 0, "COS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #493 = COS_Fp80 { 494, 0, 0, 0, "CPUID", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(162<<24), NULL, NULL, NULL, 0 }, // Inst #494 = CPUID { 495, 0, 0, 0, "CQO", 0, 0|1|(1<<12)|(153<<24), ImplicitList15, ImplicitList19, NULL, 0 }, // Inst #495 = CQO { 496, 7, 1, 0, "CRC32m16", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #496 = CRC32m16 { 497, 7, 1, 0, "CRC32m32", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #497 = CRC32m32 { 498, 7, 1, 0, "CRC32m8", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(240<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #498 = CRC32m8 { 499, 3, 1, 0, "CRC32r16", 0, 0|5|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo77 }, // Inst #499 = CRC32r16 { 500, 3, 1, 0, "CRC32r32", 0, 0|5|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #500 = CRC32r32 { 501, 3, 1, 0, "CRC32r8", 0, 0|5|(1<<6)|(15<<8)|(240<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #501 = CRC32r8 { 502, 7, 1, 0, "CRC64m64", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(1<<12)|(240<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #502 = CRC64m64 { 503, 3, 1, 0, "CRC64r64", 0, 0|5|(1<<6)|(15<<8)|(1<<12)|(240<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #503 = CRC64r64 { 504, 0, 0, 0, "CS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(46<<24), NULL, NULL, NULL, 0 }, // Inst #504 = CS_PREFIX { 505, 6, 1, 0, "CVTDQ2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #505 = CVTDQ2PDrm { 506, 2, 1, 0, "CVTDQ2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #506 = CVTDQ2PDrr { 507, 6, 1, 0, "CVTDQ2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #507 = CVTDQ2PSrm { 508, 2, 1, 0, "CVTDQ2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #508 = CVTDQ2PSrr { 509, 6, 1, 0, "CVTPD2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #509 = CVTPD2DQrm { 510, 2, 1, 0, "CVTPD2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #510 = CVTPD2DQrr { 511, 6, 1, 0, "CVTPD2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #511 = CVTPD2PSrm { 512, 2, 1, 0, "CVTPD2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #512 = CVTPD2PSrr { 513, 6, 1, 0, "CVTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #513 = CVTPS2DQrm { 514, 2, 1, 0, "CVTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #514 = CVTPS2DQrr { 515, 6, 1, 0, "CVTPS2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #515 = CVTPS2PDrm { 516, 2, 1, 0, "CVTPS2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #516 = CVTPS2PDrr { 517, 6, 1, 0, "CVTSD2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #517 = CVTSD2SI64rm { 518, 2, 1, 0, "CVTSD2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #518 = CVTSD2SI64rr { 519, 6, 1, 0, "CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #519 = CVTSD2SSrm { 520, 2, 1, 0, "CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo81 }, // Inst #520 = CVTSD2SSrr { 521, 6, 1, 0, "CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #521 = CVTSI2SD64rm { 522, 2, 1, 0, "CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #522 = CVTSI2SD64rr { 523, 6, 1, 0, "CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #523 = CVTSI2SDrm { 524, 2, 1, 0, "CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo84 }, // Inst #524 = CVTSI2SDrr { 525, 6, 1, 0, "CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #525 = CVTSI2SS64rm { 526, 2, 1, 0, "CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo85 }, // Inst #526 = CVTSI2SS64rr { 527, 6, 1, 0, "CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #527 = CVTSI2SSrm { 528, 2, 1, 0, "CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #528 = CVTSI2SSrr { 529, 6, 1, 0, "CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #529 = CVTSS2SDrm { 530, 2, 1, 0, "CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo87 }, // Inst #530 = CVTSS2SDrr { 531, 6, 1, 0, "CVTSS2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #531 = CVTSS2SI64rm { 532, 2, 1, 0, "CVTSS2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo88 }, // Inst #532 = CVTSS2SI64rr { 533, 6, 1, 0, "CVTSS2SIrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #533 = CVTSS2SIrm { 534, 2, 1, 0, "CVTSS2SIrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #534 = CVTSS2SIrr { 535, 6, 1, 0, "CVTTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #535 = CVTTPS2DQrm { 536, 2, 1, 0, "CVTTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #536 = CVTTPS2DQrr { 537, 6, 1, 0, "CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #537 = CVTTSD2SI64rm { 538, 2, 1, 0, "CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #538 = CVTTSD2SI64rr { 539, 6, 1, 0, "CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #539 = CVTTSD2SIrm { 540, 2, 1, 0, "CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo90 }, // Inst #540 = CVTTSD2SIrr { 541, 6, 1, 0, "CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #541 = CVTTSS2SI64rm { 542, 2, 1, 0, "CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo88 }, // Inst #542 = CVTTSS2SI64rr { 543, 6, 1, 0, "CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #543 = CVTTSS2SIrm { 544, 2, 1, 0, "CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #544 = CVTTSS2SIrr { 545, 0, 0, 0, "CWD", 0, 0|1|(1<<6)|(153<<24), ImplicitList12, ImplicitList20, NULL, 0 }, // Inst #545 = CWD { 546, 0, 0, 0, "CWDE", 0, 0|1|(152<<24), ImplicitList12, ImplicitList13, NULL, 0 }, // Inst #546 = CWDE { 547, 5, 0, 0, "DEC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #547 = DEC16m { 548, 2, 1, 0, "DEC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #548 = DEC16r { 549, 5, 0, 0, "DEC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #549 = DEC32m { 550, 2, 1, 0, "DEC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #550 = DEC32r { 551, 5, 0, 0, "DEC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #551 = DEC64_16m { 552, 2, 1, 0, "DEC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #552 = DEC64_16r { 553, 5, 0, 0, "DEC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #553 = DEC64_32m { 554, 2, 1, 0, "DEC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #554 = DEC64_32r { 555, 5, 0, 0, "DEC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #555 = DEC64m { 556, 2, 1, 0, "DEC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #556 = DEC64r { 557, 5, 0, 0, "DEC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #557 = DEC8m { 558, 2, 1, 0, "DEC8r", 0, 0|17|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #558 = DEC8r { 559, 5, 0, 0, "DIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #559 = DIV16m { 560, 1, 0, 0, "DIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #560 = DIV16r { 561, 5, 0, 0, "DIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #561 = DIV32m { 562, 1, 0, 0, "DIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #562 = DIV32r { 563, 5, 0, 0, "DIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #563 = DIV64m { 564, 1, 0, 0, "DIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #564 = DIV64r { 565, 5, 0, 0, "DIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #565 = DIV8m { 566, 1, 0, 0, "DIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #566 = DIV8r { 567, 7, 1, 0, "DIVPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #567 = DIVPDrm { 568, 3, 1, 0, "DIVPDrr", 0, 0|5|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #568 = DIVPDrr { 569, 7, 1, 0, "DIVPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #569 = DIVPSrm { 570, 3, 1, 0, "DIVPSrr", 0, 0|5|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #570 = DIVPSrr { 571, 5, 0, 0, "DIVR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #571 = DIVR_F32m { 572, 5, 0, 0, "DIVR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #572 = DIVR_F64m { 573, 5, 0, 0, "DIVR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #573 = DIVR_FI16m { 574, 5, 0, 0, "DIVR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #574 = DIVR_FI32m { 575, 1, 0, 0, "DIVR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #575 = DIVR_FPrST0 { 576, 1, 0, 0, "DIVR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #576 = DIVR_FST0r { 577, 7, 1, 0, "DIVR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #577 = DIVR_Fp32m { 578, 7, 1, 0, "DIVR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #578 = DIVR_Fp64m { 579, 7, 1, 0, "DIVR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #579 = DIVR_Fp64m32 { 580, 7, 1, 0, "DIVR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #580 = DIVR_Fp80m32 { 581, 7, 1, 0, "DIVR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #581 = DIVR_Fp80m64 { 582, 7, 1, 0, "DIVR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #582 = DIVR_FpI16m32 { 583, 7, 1, 0, "DIVR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #583 = DIVR_FpI16m64 { 584, 7, 1, 0, "DIVR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #584 = DIVR_FpI16m80 { 585, 7, 1, 0, "DIVR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #585 = DIVR_FpI32m32 { 586, 7, 1, 0, "DIVR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #586 = DIVR_FpI32m64 { 587, 7, 1, 0, "DIVR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #587 = DIVR_FpI32m80 { 588, 1, 0, 0, "DIVR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #588 = DIVR_FrST0 { 589, 7, 1, 0, "DIVSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #589 = DIVSDrm { 590, 7, 1, 0, "DIVSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #590 = DIVSDrm_Int { 591, 3, 1, 0, "DIVSDrr", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #591 = DIVSDrr { 592, 3, 1, 0, "DIVSDrr_Int", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #592 = DIVSDrr_Int { 593, 7, 1, 0, "DIVSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #593 = DIVSSrm { 594, 7, 1, 0, "DIVSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #594 = DIVSSrm_Int { 595, 3, 1, 0, "DIVSSrr", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #595 = DIVSSrr { 596, 3, 1, 0, "DIVSSrr_Int", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #596 = DIVSSrr_Int { 597, 5, 0, 0, "DIV_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #597 = DIV_F32m { 598, 5, 0, 0, "DIV_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #598 = DIV_F64m { 599, 5, 0, 0, "DIV_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #599 = DIV_FI16m { 600, 5, 0, 0, "DIV_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #600 = DIV_FI32m { 601, 1, 0, 0, "DIV_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #601 = DIV_FPrST0 { 602, 1, 0, 0, "DIV_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #602 = DIV_FST0r { 603, 3, 1, 0, "DIV_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #603 = DIV_Fp32 { 604, 7, 1, 0, "DIV_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #604 = DIV_Fp32m { 605, 3, 1, 0, "DIV_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #605 = DIV_Fp64 { 606, 7, 1, 0, "DIV_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #606 = DIV_Fp64m { 607, 7, 1, 0, "DIV_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #607 = DIV_Fp64m32 { 608, 3, 1, 0, "DIV_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #608 = DIV_Fp80 { 609, 7, 1, 0, "DIV_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #609 = DIV_Fp80m32 { 610, 7, 1, 0, "DIV_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #610 = DIV_Fp80m64 { 611, 7, 1, 0, "DIV_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #611 = DIV_FpI16m32 { 612, 7, 1, 0, "DIV_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #612 = DIV_FpI16m64 { 613, 7, 1, 0, "DIV_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #613 = DIV_FpI16m80 { 614, 7, 1, 0, "DIV_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #614 = DIV_FpI32m32 { 615, 7, 1, 0, "DIV_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #615 = DIV_FpI32m64 { 616, 7, 1, 0, "DIV_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #616 = DIV_FpI32m80 { 617, 1, 0, 0, "DIV_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #617 = DIV_FrST0 { 618, 8, 1, 0, "DPPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #618 = DPPDrmi { 619, 4, 1, 0, "DPPDrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #619 = DPPDrri { 620, 8, 1, 0, "DPPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #620 = DPPSrmi { 621, 4, 1, 0, "DPPSrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #621 = DPPSrri { 622, 0, 0, 0, "DS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(62<<24), NULL, NULL, NULL, 0 }, // Inst #622 = DS_PREFIX { 623, 1, 0, 0, "EH_RETURN", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #623 = EH_RETURN { 624, 1, 0, 0, "EH_RETURN64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #624 = EH_RETURN64 { 625, 2, 0, 0, "ENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(200<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #625 = ENTER { 626, 0, 0, 0, "ES_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(38<<24), NULL, NULL, NULL, 0 }, // Inst #626 = ES_PREFIX { 627, 7, 0, 0, "EXTRACTPSmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #627 = EXTRACTPSmr { 628, 3, 1, 0, "EXTRACTPSrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #628 = EXTRACTPSrr { 629, 0, 0, 0, "F2XM1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(240<<24), NULL, NULL, NULL, 0 }, // Inst #629 = F2XM1 { 630, 2, 0, 0, "FARCALL16i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo38 }, // Inst #630 = FARCALL16i { 631, 5, 0, 0, "FARCALL16m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #631 = FARCALL16m { 632, 2, 0, 0, "FARCALL32i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo38 }, // Inst #632 = FARCALL32i { 633, 5, 0, 0, "FARCALL32m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #633 = FARCALL32m { 634, 5, 0, 0, "FARCALL64", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo30 }, // Inst #634 = FARCALL64 { 635, 2, 0, 0, "FARJMP16i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(234<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #635 = FARJMP16i { 636, 5, 0, 0, "FARJMP16m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #636 = FARJMP16m { 637, 2, 0, 0, "FARJMP32i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(234<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #637 = FARJMP32i { 638, 5, 0, 0, "FARJMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #638 = FARJMP32m { 639, 5, 0, 0, "FARJMP64", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #639 = FARJMP64 { 640, 5, 0, 0, "FBLDm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #640 = FBLDm { 641, 5, 1, 0, "FBSTPm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #641 = FBSTPm { 642, 5, 0, 0, "FCOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #642 = FCOM32m { 643, 5, 0, 0, "FCOM64m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #643 = FCOM64m { 644, 5, 0, 0, "FCOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #644 = FCOMP32m { 645, 5, 0, 0, "FCOMP64m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #645 = FCOMP64m { 646, 0, 0, 0, "FCOMPP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(9<<8)|(217<<24), NULL, NULL, NULL, 0 }, // Inst #646 = FCOMPP { 647, 0, 0, 0, "FDECSTP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(246<<24), NULL, NULL, NULL, 0 }, // Inst #647 = FDECSTP { 648, 1, 0, 0, "FFREE", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #648 = FFREE { 649, 5, 0, 0, "FICOM16m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #649 = FICOM16m { 650, 5, 0, 0, "FICOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #650 = FICOM32m { 651, 5, 0, 0, "FICOMP16m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #651 = FICOMP16m { 652, 5, 0, 0, "FICOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #652 = FICOMP32m { 653, 0, 0, 0, "FINCSTP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(247<<24), NULL, NULL, NULL, 0 }, // Inst #653 = FINCSTP { 654, 5, 0, 0, "FLDCW16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #654 = FLDCW16m { 655, 5, 0, 0, "FLDENVm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #655 = FLDENVm { 656, 0, 0, 0, "FLDL2E", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(234<<24), NULL, NULL, NULL, 0 }, // Inst #656 = FLDL2E { 657, 0, 0, 0, "FLDL2T", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(233<<24), NULL, NULL, NULL, 0 }, // Inst #657 = FLDL2T { 658, 0, 0, 0, "FLDLG2", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(236<<24), NULL, NULL, NULL, 0 }, // Inst #658 = FLDLG2 { 659, 0, 0, 0, "FLDLN2", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(237<<24), NULL, NULL, NULL, 0 }, // Inst #659 = FLDLN2 { 660, 0, 0, 0, "FLDPI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(235<<24), NULL, NULL, NULL, 0 }, // Inst #660 = FLDPI { 661, 0, 0, 0, "FNCLEX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(6<<8)|(226<<24), NULL, NULL, NULL, 0 }, // Inst #661 = FNCLEX { 662, 0, 0, 0, "FNINIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(6<<8)|(227<<24), NULL, NULL, NULL, 0 }, // Inst #662 = FNINIT { 663, 0, 0, 0, "FNOP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(208<<24), NULL, NULL, NULL, 0 }, // Inst #663 = FNOP { 664, 5, 0, 0, "FNSTCW16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #664 = FNSTCW16m { 665, 0, 0, 0, "FNSTSW8r", 0|(1<<TID::UnmodeledSideEffects), 0|1|(10<<8)|(224<<24), NULL, ImplicitList12, NULL, 0 }, // Inst #665 = FNSTSW8r { 666, 5, 1, 0, "FNSTSWm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #666 = FNSTSWm { 667, 6, 0, 0, "FP32_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #667 = FP32_TO_INT16_IN_MEM { 668, 6, 0, 0, "FP32_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #668 = FP32_TO_INT32_IN_MEM { 669, 6, 0, 0, "FP32_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #669 = FP32_TO_INT64_IN_MEM { 670, 6, 0, 0, "FP64_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #670 = FP64_TO_INT16_IN_MEM { 671, 6, 0, 0, "FP64_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #671 = FP64_TO_INT32_IN_MEM { 672, 6, 0, 0, "FP64_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #672 = FP64_TO_INT64_IN_MEM { 673, 6, 0, 0, "FP80_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #673 = FP80_TO_INT16_IN_MEM { 674, 6, 0, 0, "FP80_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #674 = FP80_TO_INT32_IN_MEM { 675, 6, 0, 0, "FP80_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #675 = FP80_TO_INT64_IN_MEM { 676, 0, 0, 0, "FPATAN", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(243<<24), NULL, NULL, NULL, 0 }, // Inst #676 = FPATAN { 677, 0, 0, 0, "FPREM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(248<<24), NULL, NULL, NULL, 0 }, // Inst #677 = FPREM { 678, 0, 0, 0, "FPREM1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(245<<24), NULL, NULL, NULL, 0 }, // Inst #678 = FPREM1 { 679, 0, 0, 0, "FPTAN", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(242<<24), NULL, NULL, NULL, 0 }, // Inst #679 = FPTAN { 680, 0, 0, 0, "FP_REG_KILL", 0|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0, NULL, ImplicitList23, Barriers7, 0 }, // Inst #680 = FP_REG_KILL { 681, 0, 0, 0, "FRNDINT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(252<<24), NULL, NULL, NULL, 0 }, // Inst #681 = FRNDINT { 682, 5, 1, 0, "FRSTORm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #682 = FRSTORm { 683, 5, 1, 0, "FSAVEm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #683 = FSAVEm { 684, 0, 0, 0, "FSCALE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(253<<24), NULL, NULL, NULL, 0 }, // Inst #684 = FSCALE { 685, 0, 0, 0, "FSINCOS", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(251<<24), NULL, NULL, NULL, 0 }, // Inst #685 = FSINCOS { 686, 5, 1, 0, "FSTENVm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #686 = FSTENVm { 687, 6, 1, 0, "FS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #687 = FS_MOV32rm { 688, 0, 0, 0, "FS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(100<<24), NULL, NULL, NULL, 0 }, // Inst #688 = FS_PREFIX { 689, 0, 0, 0, "FXAM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(229<<24), NULL, NULL, NULL, 0 }, // Inst #689 = FXAM { 690, 5, 0, 0, "FXRSTOR", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #690 = FXRSTOR { 691, 5, 1, 0, "FXSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #691 = FXSAVE { 692, 0, 0, 0, "FXTRACT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(244<<24), NULL, NULL, NULL, 0 }, // Inst #692 = FXTRACT { 693, 0, 0, 0, "FYL2X", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(241<<24), NULL, NULL, NULL, 0 }, // Inst #693 = FYL2X { 694, 0, 0, 0, "FYL2XP1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(249<<24), NULL, NULL, NULL, 0 }, // Inst #694 = FYL2XP1 { 695, 1, 1, 0, "FpGET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #695 = FpGET_ST0_32 { 696, 1, 1, 0, "FpGET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #696 = FpGET_ST0_64 { 697, 1, 1, 0, "FpGET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #697 = FpGET_ST0_80 { 698, 1, 1, 0, "FpGET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #698 = FpGET_ST1_32 { 699, 1, 1, 0, "FpGET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #699 = FpGET_ST1_64 { 700, 1, 1, 0, "FpGET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #700 = FpGET_ST1_80 { 701, 1, 0, 0, "FpSET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo100 }, // Inst #701 = FpSET_ST0_32 { 702, 1, 0, 0, "FpSET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo101 }, // Inst #702 = FpSET_ST0_64 { 703, 1, 0, 0, "FpSET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo102 }, // Inst #703 = FpSET_ST0_80 { 704, 1, 0, 0, "FpSET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList25, NULL, OperandInfo100 }, // Inst #704 = FpSET_ST1_32 { 705, 1, 0, 0, "FpSET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList25, NULL, OperandInfo101 }, // Inst #705 = FpSET_ST1_64 { 706, 1, 0, 0, "FpSET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList25, NULL, OperandInfo102 }, // Inst #706 = FpSET_ST1_80 { 707, 7, 1, 0, "FsANDNPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #707 = FsANDNPDrm { 708, 3, 1, 0, "FsANDNPDrr", 0, 0|5|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #708 = FsANDNPDrr { 709, 7, 1, 0, "FsANDNPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #709 = FsANDNPSrm { 710, 3, 1, 0, "FsANDNPSrr", 0, 0|5|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #710 = FsANDNPSrr { 711, 7, 1, 0, "FsANDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #711 = FsANDPDrm { 712, 3, 1, 0, "FsANDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #712 = FsANDPDrr { 713, 7, 1, 0, "FsANDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #713 = FsANDPSrm { 714, 3, 1, 0, "FsANDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #714 = FsANDPSrr { 715, 1, 1, 0, "FsFLD0SD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo103 }, // Inst #715 = FsFLD0SD { 716, 1, 1, 0, "FsFLD0SS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo104 }, // Inst #716 = FsFLD0SS { 717, 6, 1, 0, "FsMOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #717 = FsMOVAPDrm { 718, 2, 1, 0, "FsMOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #718 = FsMOVAPDrr { 719, 6, 1, 0, "FsMOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #719 = FsMOVAPSrm { 720, 2, 1, 0, "FsMOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #720 = FsMOVAPSrr { 721, 7, 1, 0, "FsORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #721 = FsORPDrm { 722, 3, 1, 0, "FsORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #722 = FsORPDrr { 723, 7, 1, 0, "FsORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #723 = FsORPSrm { 724, 3, 1, 0, "FsORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #724 = FsORPSrr { 725, 7, 1, 0, "FsXORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #725 = FsXORPDrm { 726, 3, 1, 0, "FsXORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #726 = FsXORPDrr { 727, 7, 1, 0, "FsXORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #727 = FsXORPSrm { 728, 3, 1, 0, "FsXORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #728 = FsXORPSrr { 729, 6, 1, 0, "GS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #729 = GS_MOV32rm { 730, 0, 0, 0, "GS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(101<<24), NULL, NULL, NULL, 0 }, // Inst #730 = GS_PREFIX { 731, 7, 1, 0, "HADDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #731 = HADDPDrm { 732, 3, 1, 0, "HADDPDrr", 0, 0|5|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #732 = HADDPDrr { 733, 7, 1, 0, "HADDPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #733 = HADDPSrm { 734, 3, 1, 0, "HADDPSrr", 0, 0|5|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #734 = HADDPSrr { 735, 0, 0, 0, "HLT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(244<<24), NULL, NULL, NULL, 0 }, // Inst #735 = HLT { 736, 7, 1, 0, "HSUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #736 = HSUBPDrm { 737, 3, 1, 0, "HSUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #737 = HSUBPDrr { 738, 7, 1, 0, "HSUBPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #738 = HSUBPSrm { 739, 3, 1, 0, "HSUBPSrr", 0, 0|5|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #739 = HSUBPSrr { 740, 5, 0, 0, "IDIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #740 = IDIV16m { 741, 1, 0, 0, "IDIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #741 = IDIV16r { 742, 5, 0, 0, "IDIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #742 = IDIV32m { 743, 1, 0, 0, "IDIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #743 = IDIV32r { 744, 5, 0, 0, "IDIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #744 = IDIV64m { 745, 1, 0, 0, "IDIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #745 = IDIV64r { 746, 5, 0, 0, "IDIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #746 = IDIV8m { 747, 1, 0, 0, "IDIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #747 = IDIV8r { 748, 5, 0, 0, "ILD_F16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #748 = ILD_F16m { 749, 5, 0, 0, "ILD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #749 = ILD_F32m { 750, 5, 0, 0, "ILD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #750 = ILD_F64m { 751, 6, 1, 0, "ILD_Fp16m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #751 = ILD_Fp16m32 { 752, 6, 1, 0, "ILD_Fp16m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #752 = ILD_Fp16m64 { 753, 6, 1, 0, "ILD_Fp16m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #753 = ILD_Fp16m80 { 754, 6, 1, 0, "ILD_Fp32m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #754 = ILD_Fp32m32 { 755, 6, 1, 0, "ILD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #755 = ILD_Fp32m64 { 756, 6, 1, 0, "ILD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #756 = ILD_Fp32m80 { 757, 6, 1, 0, "ILD_Fp64m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #757 = ILD_Fp64m32 { 758, 6, 1, 0, "ILD_Fp64m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #758 = ILD_Fp64m64 { 759, 6, 1, 0, "ILD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #759 = ILD_Fp64m80 { 760, 5, 0, 0, "IMUL16m", 0|(1<<TID::MayLoad), 0|29|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #760 = IMUL16m { 761, 1, 0, 0, "IMUL16r", 0, 0|21|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #761 = IMUL16r { 762, 7, 1, 0, "IMUL16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #762 = IMUL16rm { 763, 7, 1, 0, "IMUL16rmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #763 = IMUL16rmi { 764, 7, 1, 0, "IMUL16rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #764 = IMUL16rmi8 { 765, 3, 1, 0, "IMUL16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #765 = IMUL16rr { 766, 3, 1, 0, "IMUL16rri", 0, 0|5|(1<<6)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #766 = IMUL16rri { 767, 3, 1, 0, "IMUL16rri8", 0, 0|5|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #767 = IMUL16rri8 { 768, 5, 0, 0, "IMUL32m", 0|(1<<TID::MayLoad), 0|29|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #768 = IMUL32m { 769, 1, 0, 0, "IMUL32r", 0, 0|21|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #769 = IMUL32r { 770, 7, 1, 0, "IMUL32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #770 = IMUL32rm { 771, 7, 1, 0, "IMUL32rmi", 0|(1<<TID::MayLoad), 0|6|(4<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #771 = IMUL32rmi { 772, 7, 1, 0, "IMUL32rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #772 = IMUL32rmi8 { 773, 3, 1, 0, "IMUL32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #773 = IMUL32rr { 774, 3, 1, 0, "IMUL32rri", 0, 0|5|(4<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #774 = IMUL32rri { 775, 3, 1, 0, "IMUL32rri8", 0, 0|5|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #775 = IMUL32rri8 { 776, 5, 0, 0, "IMUL64m", 0|(1<<TID::MayLoad), 0|29|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #776 = IMUL64m { 777, 1, 0, 0, "IMUL64r", 0, 0|21|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #777 = IMUL64r { 778, 7, 1, 0, "IMUL64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #778 = IMUL64rm { 779, 7, 1, 0, "IMUL64rmi32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(4<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #779 = IMUL64rmi32 { 780, 7, 1, 0, "IMUL64rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #780 = IMUL64rmi8 { 781, 3, 1, 0, "IMUL64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #781 = IMUL64rr { 782, 3, 1, 0, "IMUL64rri32", 0, 0|5|(1<<12)|(4<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo115 }, // Inst #782 = IMUL64rri32 { 783, 3, 1, 0, "IMUL64rri8", 0, 0|5|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo115 }, // Inst #783 = IMUL64rri8 { 784, 5, 0, 0, "IMUL8m", 0|(1<<TID::MayLoad), 0|29|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #784 = IMUL8m { 785, 1, 0, 0, "IMUL8r", 0, 0|21|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #785 = IMUL8r { 786, 0, 0, 0, "IN16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(109<<24), NULL, NULL, NULL, 0 }, // Inst #786 = IN16 { 787, 1, 0, 0, "IN16ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(229<<24), NULL, ImplicitList12, NULL, OperandInfo5 }, // Inst #787 = IN16ri { 788, 0, 0, 0, "IN16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(237<<24), ImplicitList26, ImplicitList12, NULL, 0 }, // Inst #788 = IN16rr { 789, 0, 0, 0, "IN32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(109<<24), NULL, NULL, NULL, 0 }, // Inst #789 = IN32 { 790, 1, 0, 0, "IN32ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(229<<24), NULL, ImplicitList13, NULL, OperandInfo5 }, // Inst #790 = IN32ri { 791, 0, 0, 0, "IN32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(237<<24), ImplicitList26, ImplicitList13, NULL, 0 }, // Inst #791 = IN32rr { 792, 0, 0, 0, "IN8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(108<<24), NULL, NULL, NULL, 0 }, // Inst #792 = IN8 { 793, 1, 0, 0, "IN8ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(228<<24), NULL, ImplicitList11, NULL, OperandInfo5 }, // Inst #793 = IN8ri { 794, 0, 0, 0, "IN8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(236<<24), ImplicitList26, ImplicitList11, NULL, 0 }, // Inst #794 = IN8rr { 795, 5, 0, 0, "INC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #795 = INC16m { 796, 2, 1, 0, "INC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #796 = INC16r { 797, 5, 0, 0, "INC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #797 = INC32m { 798, 2, 1, 0, "INC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #798 = INC32r { 799, 5, 0, 0, "INC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #799 = INC64_16m { 800, 2, 1, 0, "INC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #800 = INC64_16r { 801, 5, 0, 0, "INC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #801 = INC64_32m { 802, 2, 1, 0, "INC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #802 = INC64_32r { 803, 5, 0, 0, "INC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #803 = INC64m { 804, 2, 1, 0, "INC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #804 = INC64r { 805, 5, 0, 0, "INC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #805 = INC8m { 806, 2, 1, 0, "INC8r", 0, 0|16|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #806 = INC8r { 807, 8, 1, 0, "INSERTPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #807 = INSERTPSrm { 808, 4, 1, 0, "INSERTPSrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #808 = INSERTPSrr { 809, 1, 0, 0, "INT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(205<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #809 = INT { 810, 0, 0, 0, "INT3", 0|(1<<TID::UnmodeledSideEffects), 0|1|(204<<24), NULL, NULL, NULL, 0 }, // Inst #810 = INT3 { 811, 0, 0, 0, "INVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(8<<24), NULL, NULL, NULL, 0 }, // Inst #811 = INVD { 812, 0, 0, 0, "INVEPT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(13<<8)|(128<<24), NULL, NULL, NULL, 0 }, // Inst #812 = INVEPT { 813, 5, 0, 0, "INVLPG", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #813 = INVLPG { 814, 0, 0, 0, "INVVPID", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(13<<8)|(129<<24), NULL, NULL, NULL, 0 }, // Inst #814 = INVVPID { 815, 0, 0, 0, "IRET16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(207<<24), NULL, NULL, NULL, 0 }, // Inst #815 = IRET16 { 816, 0, 0, 0, "IRET32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(207<<24), NULL, NULL, NULL, 0 }, // Inst #816 = IRET32 { 817, 0, 0, 0, "IRET64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(207<<24), NULL, NULL, NULL, 0 }, // Inst #817 = IRET64 { 818, 5, 0, 0, "ISTT_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #818 = ISTT_FP16m { 819, 5, 0, 0, "ISTT_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #819 = ISTT_FP32m { 820, 5, 0, 0, "ISTT_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #820 = ISTT_FP64m { 821, 6, 0, 0, "ISTT_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #821 = ISTT_Fp16m32 { 822, 6, 0, 0, "ISTT_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #822 = ISTT_Fp16m64 { 823, 6, 0, 0, "ISTT_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #823 = ISTT_Fp16m80 { 824, 6, 0, 0, "ISTT_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #824 = ISTT_Fp32m32 { 825, 6, 0, 0, "ISTT_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #825 = ISTT_Fp32m64 { 826, 6, 0, 0, "ISTT_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #826 = ISTT_Fp32m80 { 827, 6, 0, 0, "ISTT_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #827 = ISTT_Fp64m32 { 828, 6, 0, 0, "ISTT_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #828 = ISTT_Fp64m64 { 829, 6, 0, 0, "ISTT_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #829 = ISTT_Fp64m80 { 830, 5, 0, 0, "IST_F16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #830 = IST_F16m { 831, 5, 0, 0, "IST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #831 = IST_F32m { 832, 5, 0, 0, "IST_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #832 = IST_FP16m { 833, 5, 0, 0, "IST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #833 = IST_FP32m { 834, 5, 0, 0, "IST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #834 = IST_FP64m { 835, 6, 0, 0, "IST_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #835 = IST_Fp16m32 { 836, 6, 0, 0, "IST_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #836 = IST_Fp16m64 { 837, 6, 0, 0, "IST_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #837 = IST_Fp16m80 { 838, 6, 0, 0, "IST_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #838 = IST_Fp32m32 { 839, 6, 0, 0, "IST_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #839 = IST_Fp32m64 { 840, 6, 0, 0, "IST_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #840 = IST_Fp32m80 { 841, 6, 0, 0, "IST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #841 = IST_Fp64m32 { 842, 6, 0, 0, "IST_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #842 = IST_Fp64m64 { 843, 6, 0, 0, "IST_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #843 = IST_Fp64m80 { 844, 8, 1, 0, "Int_CMPSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #844 = Int_CMPSDrm { 845, 4, 1, 0, "Int_CMPSDrr", 0, 0|5|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #845 = Int_CMPSDrr { 846, 8, 1, 0, "Int_CMPSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #846 = Int_CMPSSrm { 847, 4, 1, 0, "Int_CMPSSrr", 0, 0|5|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #847 = Int_CMPSSrr { 848, 6, 0, 0, "Int_COMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #848 = Int_COMISDrm { 849, 2, 0, 0, "Int_COMISDrr", 0, 0|5|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #849 = Int_COMISDrr { 850, 6, 0, 0, "Int_COMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #850 = Int_COMISSrm { 851, 2, 0, 0, "Int_COMISSrr", 0, 0|5|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #851 = Int_COMISSrr { 852, 6, 1, 0, "Int_CVTDQ2PDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #852 = Int_CVTDQ2PDrm { 853, 2, 1, 0, "Int_CVTDQ2PDrr", 0, 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #853 = Int_CVTDQ2PDrr { 854, 6, 1, 0, "Int_CVTDQ2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #854 = Int_CVTDQ2PSrm { 855, 2, 1, 0, "Int_CVTDQ2PSrr", 0, 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #855 = Int_CVTDQ2PSrr { 856, 6, 1, 0, "Int_CVTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #856 = Int_CVTPD2DQrm { 857, 2, 1, 0, "Int_CVTPD2DQrr", 0, 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #857 = Int_CVTPD2DQrr { 858, 6, 1, 0, "Int_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #858 = Int_CVTPD2PIrm { 859, 2, 1, 0, "Int_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #859 = Int_CVTPD2PIrr { 860, 6, 1, 0, "Int_CVTPD2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #860 = Int_CVTPD2PSrm { 861, 2, 1, 0, "Int_CVTPD2PSrr", 0, 0|5|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #861 = Int_CVTPD2PSrr { 862, 6, 1, 0, "Int_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #862 = Int_CVTPI2PDrm { 863, 2, 1, 0, "Int_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #863 = Int_CVTPI2PDrr { 864, 7, 1, 0, "Int_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #864 = Int_CVTPI2PSrm { 865, 3, 1, 0, "Int_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #865 = Int_CVTPI2PSrr { 866, 6, 1, 0, "Int_CVTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #866 = Int_CVTPS2DQrm { 867, 2, 1, 0, "Int_CVTPS2DQrr", 0, 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #867 = Int_CVTPS2DQrr { 868, 6, 1, 0, "Int_CVTPS2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #868 = Int_CVTPS2PDrm { 869, 2, 1, 0, "Int_CVTPS2PDrr", 0, 0|5|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #869 = Int_CVTPS2PDrr { 870, 6, 1, 0, "Int_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #870 = Int_CVTPS2PIrm { 871, 2, 1, 0, "Int_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #871 = Int_CVTPS2PIrr { 872, 6, 1, 0, "Int_CVTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #872 = Int_CVTSD2SI64rm { 873, 2, 1, 0, "Int_CVTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #873 = Int_CVTSD2SI64rr { 874, 6, 1, 0, "Int_CVTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #874 = Int_CVTSD2SIrm { 875, 2, 1, 0, "Int_CVTSD2SIrr", 0, 0|5|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #875 = Int_CVTSD2SIrr { 876, 7, 1, 0, "Int_CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #876 = Int_CVTSD2SSrm { 877, 3, 1, 0, "Int_CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #877 = Int_CVTSD2SSrr { 878, 7, 1, 0, "Int_CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #878 = Int_CVTSI2SD64rm { 879, 3, 1, 0, "Int_CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #879 = Int_CVTSI2SD64rr { 880, 7, 1, 0, "Int_CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #880 = Int_CVTSI2SDrm { 881, 3, 1, 0, "Int_CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #881 = Int_CVTSI2SDrr { 882, 7, 1, 0, "Int_CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #882 = Int_CVTSI2SS64rm { 883, 3, 1, 0, "Int_CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #883 = Int_CVTSI2SS64rr { 884, 7, 1, 0, "Int_CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #884 = Int_CVTSI2SSrm { 885, 3, 1, 0, "Int_CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #885 = Int_CVTSI2SSrr { 886, 7, 1, 0, "Int_CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #886 = Int_CVTSS2SDrm { 887, 3, 1, 0, "Int_CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #887 = Int_CVTSS2SDrr { 888, 6, 1, 0, "Int_CVTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #888 = Int_CVTSS2SI64rm { 889, 2, 1, 0, "Int_CVTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #889 = Int_CVTSS2SI64rr { 890, 6, 1, 0, "Int_CVTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #890 = Int_CVTSS2SIrm { 891, 2, 1, 0, "Int_CVTSS2SIrr", 0, 0|5|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #891 = Int_CVTSS2SIrr { 892, 6, 1, 0, "Int_CVTTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #892 = Int_CVTTPD2DQrm { 893, 2, 1, 0, "Int_CVTTPD2DQrr", 0, 0|5|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #893 = Int_CVTTPD2DQrr { 894, 6, 1, 0, "Int_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #894 = Int_CVTTPD2PIrm { 895, 2, 1, 0, "Int_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #895 = Int_CVTTPD2PIrr { 896, 6, 1, 0, "Int_CVTTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #896 = Int_CVTTPS2DQrm { 897, 2, 1, 0, "Int_CVTTPS2DQrr", 0, 0|5|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #897 = Int_CVTTPS2DQrr { 898, 6, 1, 0, "Int_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #898 = Int_CVTTPS2PIrm { 899, 2, 1, 0, "Int_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #899 = Int_CVTTPS2PIrr { 900, 6, 1, 0, "Int_CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #900 = Int_CVTTSD2SI64rm { 901, 2, 1, 0, "Int_CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #901 = Int_CVTTSD2SI64rr { 902, 6, 1, 0, "Int_CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #902 = Int_CVTTSD2SIrm { 903, 2, 1, 0, "Int_CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #903 = Int_CVTTSD2SIrr { 904, 6, 1, 0, "Int_CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #904 = Int_CVTTSS2SI64rm { 905, 2, 1, 0, "Int_CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #905 = Int_CVTTSS2SI64rr { 906, 6, 1, 0, "Int_CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #906 = Int_CVTTSS2SIrm { 907, 2, 1, 0, "Int_CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #907 = Int_CVTTSS2SIrr { 908, 6, 0, 0, "Int_UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #908 = Int_UCOMISDrm { 909, 2, 0, 0, "Int_UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #909 = Int_UCOMISDrr { 910, 6, 0, 0, "Int_UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #910 = Int_UCOMISSrm { 911, 2, 0, 0, "Int_UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #911 = Int_UCOMISSrr { 912, 1, 0, 0, "JAE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(115<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #912 = JAE_1 { 913, 1, 0, 0, "JAE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(131<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #913 = JAE_4 { 914, 1, 0, 0, "JA_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(119<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #914 = JA_1 { 915, 1, 0, 0, "JA_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(135<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #915 = JA_4 { 916, 1, 0, 0, "JBE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(118<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #916 = JBE_1 { 917, 1, 0, 0, "JBE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(134<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #917 = JBE_4 { 918, 1, 0, 0, "JB_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(114<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #918 = JB_1 { 919, 1, 0, 0, "JB_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(130<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #919 = JB_4 { 920, 1, 0, 0, "JCXZ8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(227<<24), ImplicitList27, NULL, NULL, OperandInfo5 }, // Inst #920 = JCXZ8 { 921, 1, 0, 0, "JE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(116<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #921 = JE_1 { 922, 1, 0, 0, "JE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(132<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #922 = JE_4 { 923, 1, 0, 0, "JGE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(125<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #923 = JGE_1 { 924, 1, 0, 0, "JGE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(141<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #924 = JGE_4 { 925, 1, 0, 0, "JG_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(127<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #925 = JG_1 { 926, 1, 0, 0, "JG_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(143<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #926 = JG_4 { 927, 1, 0, 0, "JLE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(126<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #927 = JLE_1 { 928, 1, 0, 0, "JLE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(142<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #928 = JLE_4 { 929, 1, 0, 0, "JL_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(124<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #929 = JL_1 { 930, 1, 0, 0, "JL_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(140<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #930 = JL_4 { 931, 5, 0, 0, "JMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #931 = JMP32m { 932, 1, 0, 0, "JMP32r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #932 = JMP32r { 933, 5, 0, 0, "JMP64m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #933 = JMP64m { 934, 1, 0, 0, "JMP64pcrel32", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #934 = JMP64pcrel32 { 935, 1, 0, 0, "JMP64r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #935 = JMP64r { 936, 1, 0, 0, "JMP_1", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(235<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #936 = JMP_1 { 937, 1, 0, 0, "JMP_4", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(5<<13)|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #937 = JMP_4 { 938, 1, 0, 0, "JNE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(117<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #938 = JNE_1 { 939, 1, 0, 0, "JNE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(133<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #939 = JNE_4 { 940, 1, 0, 0, "JNO_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(113<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #940 = JNO_1 { 941, 1, 0, 0, "JNO_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(129<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #941 = JNO_4 { 942, 1, 0, 0, "JNP_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(123<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #942 = JNP_1 { 943, 1, 0, 0, "JNP_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(139<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #943 = JNP_4 { 944, 1, 0, 0, "JNS_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(121<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #944 = JNS_1 { 945, 1, 0, 0, "JNS_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(137<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #945 = JNS_4 { 946, 1, 0, 0, "JO_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(112<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #946 = JO_1 { 947, 1, 0, 0, "JO_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(128<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #947 = JO_4 { 948, 1, 0, 0, "JP_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(122<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #948 = JP_1 { 949, 1, 0, 0, "JP_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(138<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #949 = JP_4 { 950, 1, 0, 0, "JS_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(120<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #950 = JS_1 { 951, 1, 0, 0, "JS_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(136<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #951 = JS_4 { 952, 0, 0, 0, "LAHF", 0, 0|1|(159<<24), ImplicitList1, ImplicitList28, NULL, 0 }, // Inst #952 = LAHF { 953, 6, 1, 0, "LAR16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #953 = LAR16rm { 954, 2, 1, 0, "LAR16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #954 = LAR16rr { 955, 6, 1, 0, "LAR32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #955 = LAR32rm { 956, 2, 1, 0, "LAR32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #956 = LAR32rr { 957, 6, 1, 0, "LAR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #957 = LAR64rm { 958, 2, 1, 0, "LAR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #958 = LAR64rr { 959, 6, 0, 0, "LCMPXCHG16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<19)|(177<<24), ImplicitList12, ImplicitList29, Barriers1, OperandInfo7 }, // Inst #959 = LCMPXCHG16 { 960, 6, 0, 0, "LCMPXCHG32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(177<<24), ImplicitList13, ImplicitList30, Barriers1, OperandInfo11 }, // Inst #960 = LCMPXCHG32 { 961, 6, 0, 0, "LCMPXCHG64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<19)|(177<<24), ImplicitList15, ImplicitList31, Barriers1, OperandInfo15 }, // Inst #961 = LCMPXCHG64 { 962, 6, 0, 0, "LCMPXCHG8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(176<<24), ImplicitList11, ImplicitList32, Barriers1, OperandInfo20 }, // Inst #962 = LCMPXCHG8 { 963, 5, 0, 0, "LCMPXCHG8B", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(1<<19)|(199<<24), ImplicitList6, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #963 = LCMPXCHG8B { 964, 6, 1, 0, "LDDQUrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(240<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #964 = LDDQUrm { 965, 5, 0, 0, "LDMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #965 = LDMXCSR { 966, 6, 1, 0, "LDS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(197<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #966 = LDS16rm { 967, 6, 1, 0, "LDS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(197<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #967 = LDS32rm { 968, 0, 0, 0, "LD_F0", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(238<<24), NULL, NULL, NULL, 0 }, // Inst #968 = LD_F0 { 969, 0, 0, 0, "LD_F1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(232<<24), NULL, NULL, NULL, 0 }, // Inst #969 = LD_F1 { 970, 5, 0, 0, "LD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #970 = LD_F32m { 971, 5, 0, 0, "LD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #971 = LD_F64m { 972, 5, 0, 0, "LD_F80m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #972 = LD_F80m { 973, 1, 1, 0, "LD_Fp032", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #973 = LD_Fp032 { 974, 1, 1, 0, "LD_Fp064", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #974 = LD_Fp064 { 975, 1, 1, 0, "LD_Fp080", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #975 = LD_Fp080 { 976, 1, 1, 0, "LD_Fp132", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #976 = LD_Fp132 { 977, 1, 1, 0, "LD_Fp164", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #977 = LD_Fp164 { 978, 1, 1, 0, "LD_Fp180", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #978 = LD_Fp180 { 979, 6, 1, 0, "LD_Fp32m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #979 = LD_Fp32m { 980, 6, 1, 0, "LD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #980 = LD_Fp32m64 { 981, 6, 1, 0, "LD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #981 = LD_Fp32m80 { 982, 6, 1, 0, "LD_Fp64m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #982 = LD_Fp64m { 983, 6, 1, 0, "LD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #983 = LD_Fp64m80 { 984, 6, 1, 0, "LD_Fp80m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #984 = LD_Fp80m { 985, 1, 0, 0, "LD_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #985 = LD_Frr { 986, 5, 1, 0, "LEA16r", 0, 0|6|(1<<6)|(141<<24), NULL, NULL, NULL, OperandInfo126 }, // Inst #986 = LEA16r { 987, 5, 1, 0, "LEA32r", 0|(1<<TID::Rematerializable), 0|6|(141<<24), NULL, NULL, NULL, OperandInfo127 }, // Inst #987 = LEA32r { 988, 5, 1, 0, "LEA64_32r", 0, 0|6|(141<<24), NULL, NULL, NULL, OperandInfo127 }, // Inst #988 = LEA64_32r { 989, 5, 1, 0, "LEA64r", 0|(1<<TID::Rematerializable), 0|6|(1<<12)|(141<<24), NULL, NULL, NULL, OperandInfo128 }, // Inst #989 = LEA64r { 990, 0, 0, 0, "LEAVE", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList33, ImplicitList33, NULL, 0 }, // Inst #990 = LEAVE { 991, 0, 0, 0, "LEAVE64", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList34, ImplicitList34, NULL, 0 }, // Inst #991 = LEAVE64 { 992, 6, 1, 0, "LES16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(196<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #992 = LES16rm { 993, 6, 1, 0, "LES32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(196<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #993 = LES32rm { 994, 0, 0, 0, "LFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|39|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #994 = LFENCE { 995, 6, 1, 0, "LFS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(180<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #995 = LFS16rm { 996, 6, 1, 0, "LFS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(180<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #996 = LFS32rm { 997, 6, 1, 0, "LFS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(180<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #997 = LFS64rm { 998, 5, 0, 0, "LGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #998 = LGDTm { 999, 6, 1, 0, "LGS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(181<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #999 = LGS16rm { 1000, 6, 1, 0, "LGS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(181<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1000 = LGS32rm { 1001, 6, 1, 0, "LGS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(181<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1001 = LGS64rm { 1002, 5, 0, 0, "LIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1002 = LIDTm { 1003, 5, 0, 0, "LLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #1003 = LLDT16m { 1004, 1, 0, 0, "LLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #1004 = LLDT16r { 1005, 5, 0, 0, "LMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1005 = LMSW16m { 1006, 1, 0, 0, "LMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #1006 = LMSW16r { 1007, 6, 0, 0, "LOCK_ADD16mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1007 = LOCK_ADD16mi { 1008, 6, 0, 0, "LOCK_ADD16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1008 = LOCK_ADD16mi8 { 1009, 6, 0, 0, "LOCK_ADD16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1009 = LOCK_ADD16mr { 1010, 6, 0, 0, "LOCK_ADD32mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(4<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1010 = LOCK_ADD32mi { 1011, 6, 0, 0, "LOCK_ADD32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1011 = LOCK_ADD32mi8 { 1012, 6, 0, 0, "LOCK_ADD32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1012 = LOCK_ADD32mr { 1013, 6, 0, 0, "LOCK_ADD64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(4<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1013 = LOCK_ADD64mi32 { 1014, 6, 0, 0, "LOCK_ADD64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1014 = LOCK_ADD64mi8 { 1015, 6, 0, 0, "LOCK_ADD64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1015 = LOCK_ADD64mr { 1016, 6, 0, 0, "LOCK_ADD8mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1016 = LOCK_ADD8mi { 1017, 6, 0, 0, "LOCK_ADD8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1017 = LOCK_ADD8mr { 1018, 5, 0, 0, "LOCK_DEC16m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1018 = LOCK_DEC16m { 1019, 5, 0, 0, "LOCK_DEC32m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1019 = LOCK_DEC32m { 1020, 5, 0, 0, "LOCK_DEC64m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1020 = LOCK_DEC64m { 1021, 5, 0, 0, "LOCK_DEC8m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1021 = LOCK_DEC8m { 1022, 5, 0, 0, "LOCK_INC16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1022 = LOCK_INC16m { 1023, 5, 0, 0, "LOCK_INC32m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1023 = LOCK_INC32m { 1024, 5, 0, 0, "LOCK_INC64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1024 = LOCK_INC64m { 1025, 5, 0, 0, "LOCK_INC8m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1025 = LOCK_INC8m { 1026, 0, 0, 0, "LOCK_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(240<<24), NULL, NULL, NULL, 0 }, // Inst #1026 = LOCK_PREFIX { 1027, 6, 0, 0, "LOCK_SUB16mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1027 = LOCK_SUB16mi { 1028, 6, 0, 0, "LOCK_SUB16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1028 = LOCK_SUB16mi8 { 1029, 6, 0, 0, "LOCK_SUB16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1029 = LOCK_SUB16mr { 1030, 6, 0, 0, "LOCK_SUB32mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(4<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1030 = LOCK_SUB32mi { 1031, 6, 0, 0, "LOCK_SUB32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1031 = LOCK_SUB32mi8 { 1032, 6, 0, 0, "LOCK_SUB32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1032 = LOCK_SUB32mr { 1033, 6, 0, 0, "LOCK_SUB64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(4<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1033 = LOCK_SUB64mi32 { 1034, 6, 0, 0, "LOCK_SUB64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1034 = LOCK_SUB64mi8 { 1035, 6, 0, 0, "LOCK_SUB64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1035 = LOCK_SUB64mr { 1036, 6, 0, 0, "LOCK_SUB8mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1036 = LOCK_SUB8mi { 1037, 6, 0, 0, "LOCK_SUB8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1037 = LOCK_SUB8mr { 1038, 0, 0, 0, "LODSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(172<<24), NULL, NULL, NULL, 0 }, // Inst #1038 = LODSB { 1039, 0, 0, 0, "LODSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1039 = LODSD { 1040, 0, 0, 0, "LODSQ", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1040 = LODSQ { 1041, 0, 0, 0, "LODSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1041 = LODSW { 1042, 1, 1, 0, "LOOP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(226<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1042 = LOOP { 1043, 1, 1, 0, "LOOPE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(225<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1043 = LOOPE { 1044, 1, 1, 0, "LOOPNE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(224<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1044 = LOOPNE { 1045, 0, 0, 0, "LRET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(7<<16)|(203<<24), NULL, NULL, NULL, 0 }, // Inst #1045 = LRET { 1046, 1, 0, 0, "LRETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(7<<16)|(202<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1046 = LRETI { 1047, 6, 1, 0, "LSL16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1047 = LSL16rm { 1048, 2, 1, 0, "LSL16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1048 = LSL16rr { 1049, 6, 1, 0, "LSL32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1049 = LSL32rm { 1050, 2, 1, 0, "LSL32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1050 = LSL32rr { 1051, 6, 1, 0, "LSL64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(3<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1051 = LSL64rm { 1052, 2, 1, 0, "LSL64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(3<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1052 = LSL64rr { 1053, 6, 1, 0, "LSS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(178<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1053 = LSS16rm { 1054, 6, 1, 0, "LSS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(178<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1054 = LSS32rm { 1055, 6, 1, 0, "LSS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(178<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1055 = LSS64rm { 1056, 5, 0, 0, "LTRm", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #1056 = LTRm { 1057, 1, 0, 0, "LTRr", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #1057 = LTRr { 1058, 7, 1, 0, "LXADD16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1058 = LXADD16 { 1059, 7, 1, 0, "LXADD32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1059 = LXADD32 { 1060, 7, 1, 0, "LXADD64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<12)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1060 = LXADD64 { 1061, 7, 1, 0, "LXADD8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1061 = LXADD8 { 1062, 2, 0, 0, "MASKMOVDQU", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList35, NULL, NULL, OperandInfo75 }, // Inst #1062 = MASKMOVDQU { 1063, 2, 0, 0, "MASKMOVDQU64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList36, NULL, NULL, OperandInfo75 }, // Inst #1063 = MASKMOVDQU64 { 1064, 7, 1, 0, "MAXPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1064 = MAXPDrm { 1065, 7, 1, 0, "MAXPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1065 = MAXPDrm_Int { 1066, 3, 1, 0, "MAXPDrr", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1066 = MAXPDrr { 1067, 3, 1, 0, "MAXPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1067 = MAXPDrr_Int { 1068, 7, 1, 0, "MAXPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1068 = MAXPSrm { 1069, 7, 1, 0, "MAXPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1069 = MAXPSrm_Int { 1070, 3, 1, 0, "MAXPSrr", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1070 = MAXPSrr { 1071, 3, 1, 0, "MAXPSrr_Int", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1071 = MAXPSrr_Int { 1072, 7, 1, 0, "MAXSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1072 = MAXSDrm { 1073, 7, 1, 0, "MAXSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1073 = MAXSDrm_Int { 1074, 3, 1, 0, "MAXSDrr", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1074 = MAXSDrr { 1075, 3, 1, 0, "MAXSDrr_Int", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1075 = MAXSDrr_Int { 1076, 7, 1, 0, "MAXSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1076 = MAXSSrm { 1077, 7, 1, 0, "MAXSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1077 = MAXSSrm_Int { 1078, 3, 1, 0, "MAXSSrr", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1078 = MAXSSrr { 1079, 3, 1, 0, "MAXSSrr_Int", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1079 = MAXSSrr_Int { 1080, 0, 0, 0, "MFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|40|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #1080 = MFENCE { 1081, 0, 0, 0, "MINGW_ALLOCA", 0|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, 0 }, // Inst #1081 = MINGW_ALLOCA { 1082, 7, 1, 0, "MINPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1082 = MINPDrm { 1083, 7, 1, 0, "MINPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1083 = MINPDrm_Int { 1084, 3, 1, 0, "MINPDrr", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1084 = MINPDrr { 1085, 3, 1, 0, "MINPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1085 = MINPDrr_Int { 1086, 7, 1, 0, "MINPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1086 = MINPSrm { 1087, 7, 1, 0, "MINPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1087 = MINPSrm_Int { 1088, 3, 1, 0, "MINPSrr", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1088 = MINPSrr { 1089, 3, 1, 0, "MINPSrr_Int", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1089 = MINPSrr_Int { 1090, 7, 1, 0, "MINSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1090 = MINSDrm { 1091, 7, 1, 0, "MINSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1091 = MINSDrm_Int { 1092, 3, 1, 0, "MINSDrr", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1092 = MINSDrr { 1093, 3, 1, 0, "MINSDrr_Int", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1093 = MINSDrr_Int { 1094, 7, 1, 0, "MINSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1094 = MINSSrm { 1095, 7, 1, 0, "MINSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1095 = MINSSrm_Int { 1096, 3, 1, 0, "MINSSrr", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1096 = MINSSrr { 1097, 3, 1, 0, "MINSSrr_Int", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1097 = MINSSrr_Int { 1098, 6, 1, 0, "MMX_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1098 = MMX_CVTPD2PIrm { 1099, 2, 1, 0, "MMX_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1099 = MMX_CVTPD2PIrr { 1100, 6, 1, 0, "MMX_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1100 = MMX_CVTPI2PDrm { 1101, 2, 1, 0, "MMX_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1101 = MMX_CVTPI2PDrr { 1102, 6, 1, 0, "MMX_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1102 = MMX_CVTPI2PSrm { 1103, 2, 1, 0, "MMX_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1103 = MMX_CVTPI2PSrr { 1104, 6, 1, 0, "MMX_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1104 = MMX_CVTPS2PIrm { 1105, 2, 1, 0, "MMX_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1105 = MMX_CVTPS2PIrr { 1106, 6, 1, 0, "MMX_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1106 = MMX_CVTTPD2PIrm { 1107, 2, 1, 0, "MMX_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1107 = MMX_CVTTPD2PIrr { 1108, 6, 1, 0, "MMX_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1108 = MMX_CVTTPS2PIrm { 1109, 2, 1, 0, "MMX_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1109 = MMX_CVTTPS2PIrr { 1110, 0, 0, 0, "MMX_EMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(119<<24), NULL, NULL, NULL, 0 }, // Inst #1110 = MMX_EMMS { 1111, 0, 0, 0, "MMX_FEMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(14<<24), NULL, NULL, NULL, 0 }, // Inst #1111 = MMX_FEMMS { 1112, 2, 0, 0, "MMX_MASKMOVQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList35, NULL, NULL, OperandInfo129 }, // Inst #1112 = MMX_MASKMOVQ { 1113, 2, 0, 0, "MMX_MASKMOVQ64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList36, NULL, NULL, OperandInfo129 }, // Inst #1113 = MMX_MASKMOVQ64 { 1114, 2, 1, 0, "MMX_MOVD64from64rr", 0, 0|3|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo130 }, // Inst #1114 = MMX_MOVD64from64rr { 1115, 2, 0, 0, "MMX_MOVD64grr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1115 = MMX_MOVD64grr { 1116, 6, 0, 0, "MMX_MOVD64mr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1116 = MMX_MOVD64mr { 1117, 6, 1, 0, "MMX_MOVD64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1117 = MMX_MOVD64rm { 1118, 2, 1, 0, "MMX_MOVD64rr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1118 = MMX_MOVD64rr { 1119, 2, 1, 0, "MMX_MOVD64rrv164", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1119 = MMX_MOVD64rrv164 { 1120, 2, 1, 0, "MMX_MOVD64to64rr", 0, 0|5|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1120 = MMX_MOVD64to64rr { 1121, 2, 1, 0, "MMX_MOVDQ2Qrr", 0, 0|5|(11<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1121 = MMX_MOVDQ2Qrr { 1122, 6, 0, 0, "MMX_MOVNTQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1122 = MMX_MOVNTQmr { 1123, 2, 1, 0, "MMX_MOVQ2DQrr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1123 = MMX_MOVQ2DQrr { 1124, 2, 1, 0, "MMX_MOVQ2FR64rr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1124 = MMX_MOVQ2FR64rr { 1125, 6, 0, 0, "MMX_MOVQ64gmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1125 = MMX_MOVQ64gmr { 1126, 6, 0, 0, "MMX_MOVQ64mr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1126 = MMX_MOVQ64mr { 1127, 6, 1, 0, "MMX_MOVQ64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1127 = MMX_MOVQ64rm { 1128, 2, 1, 0, "MMX_MOVQ64rr", 0, 0|5|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1128 = MMX_MOVQ64rr { 1129, 6, 1, 0, "MMX_MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1129 = MMX_MOVZDI2PDIrm { 1130, 2, 1, 0, "MMX_MOVZDI2PDIrr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1130 = MMX_MOVZDI2PDIrr { 1131, 7, 1, 0, "MMX_PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1131 = MMX_PACKSSDWrm { 1132, 3, 1, 0, "MMX_PACKSSDWrr", 0, 0|5|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1132 = MMX_PACKSSDWrr { 1133, 7, 1, 0, "MMX_PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1133 = MMX_PACKSSWBrm { 1134, 3, 1, 0, "MMX_PACKSSWBrr", 0, 0|5|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1134 = MMX_PACKSSWBrr { 1135, 7, 1, 0, "MMX_PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1135 = MMX_PACKUSWBrm { 1136, 3, 1, 0, "MMX_PACKUSWBrr", 0, 0|5|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1136 = MMX_PACKUSWBrr { 1137, 7, 1, 0, "MMX_PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1137 = MMX_PADDBrm { 1138, 3, 1, 0, "MMX_PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1138 = MMX_PADDBrr { 1139, 7, 1, 0, "MMX_PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1139 = MMX_PADDDrm { 1140, 3, 1, 0, "MMX_PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1140 = MMX_PADDDrr { 1141, 7, 1, 0, "MMX_PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1141 = MMX_PADDQrm { 1142, 3, 1, 0, "MMX_PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1142 = MMX_PADDQrr { 1143, 7, 1, 0, "MMX_PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1143 = MMX_PADDSBrm { 1144, 3, 1, 0, "MMX_PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1144 = MMX_PADDSBrr { 1145, 7, 1, 0, "MMX_PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1145 = MMX_PADDSWrm { 1146, 3, 1, 0, "MMX_PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1146 = MMX_PADDSWrr { 1147, 7, 1, 0, "MMX_PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1147 = MMX_PADDUSBrm { 1148, 3, 1, 0, "MMX_PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1148 = MMX_PADDUSBrr { 1149, 7, 1, 0, "MMX_PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1149 = MMX_PADDUSWrm { 1150, 3, 1, 0, "MMX_PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1150 = MMX_PADDUSWrr { 1151, 7, 1, 0, "MMX_PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1151 = MMX_PADDWrm { 1152, 3, 1, 0, "MMX_PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1152 = MMX_PADDWrr { 1153, 7, 1, 0, "MMX_PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1153 = MMX_PANDNrm { 1154, 3, 1, 0, "MMX_PANDNrr", 0, 0|5|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1154 = MMX_PANDNrr { 1155, 7, 1, 0, "MMX_PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1155 = MMX_PANDrm { 1156, 3, 1, 0, "MMX_PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1156 = MMX_PANDrr { 1157, 7, 1, 0, "MMX_PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1157 = MMX_PAVGBrm { 1158, 3, 1, 0, "MMX_PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1158 = MMX_PAVGBrr { 1159, 7, 1, 0, "MMX_PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1159 = MMX_PAVGWrm { 1160, 3, 1, 0, "MMX_PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1160 = MMX_PAVGWrr { 1161, 7, 1, 0, "MMX_PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1161 = MMX_PCMPEQBrm { 1162, 3, 1, 0, "MMX_PCMPEQBrr", 0, 0|5|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1162 = MMX_PCMPEQBrr { 1163, 7, 1, 0, "MMX_PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1163 = MMX_PCMPEQDrm { 1164, 3, 1, 0, "MMX_PCMPEQDrr", 0, 0|5|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1164 = MMX_PCMPEQDrr { 1165, 7, 1, 0, "MMX_PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1165 = MMX_PCMPEQWrm { 1166, 3, 1, 0, "MMX_PCMPEQWrr", 0, 0|5|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1166 = MMX_PCMPEQWrr { 1167, 7, 1, 0, "MMX_PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1167 = MMX_PCMPGTBrm { 1168, 3, 1, 0, "MMX_PCMPGTBrr", 0, 0|5|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1168 = MMX_PCMPGTBrr { 1169, 7, 1, 0, "MMX_PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1169 = MMX_PCMPGTDrm { 1170, 3, 1, 0, "MMX_PCMPGTDrr", 0, 0|5|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1170 = MMX_PCMPGTDrr { 1171, 7, 1, 0, "MMX_PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1171 = MMX_PCMPGTWrm { 1172, 3, 1, 0, "MMX_PCMPGTWrr", 0, 0|5|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1172 = MMX_PCMPGTWrr { 1173, 3, 1, 0, "MMX_PEXTRWri", 0, 0|5|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo138 }, // Inst #1173 = MMX_PEXTRWri { 1174, 8, 1, 0, "MMX_PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1174 = MMX_PINSRWrmi { 1175, 4, 1, 0, "MMX_PINSRWrri", 0, 0|5|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo140 }, // Inst #1175 = MMX_PINSRWrri { 1176, 7, 1, 0, "MMX_PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1176 = MMX_PMADDWDrm { 1177, 3, 1, 0, "MMX_PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1177 = MMX_PMADDWDrr { 1178, 7, 1, 0, "MMX_PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1178 = MMX_PMAXSWrm { 1179, 3, 1, 0, "MMX_PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1179 = MMX_PMAXSWrr { 1180, 7, 1, 0, "MMX_PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1180 = MMX_PMAXUBrm { 1181, 3, 1, 0, "MMX_PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1181 = MMX_PMAXUBrr { 1182, 7, 1, 0, "MMX_PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1182 = MMX_PMINSWrm { 1183, 3, 1, 0, "MMX_PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1183 = MMX_PMINSWrr { 1184, 7, 1, 0, "MMX_PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1184 = MMX_PMINUBrm { 1185, 3, 1, 0, "MMX_PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1185 = MMX_PMINUBrr { 1186, 2, 1, 0, "MMX_PMOVMSKBrr", 0, 0|5|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1186 = MMX_PMOVMSKBrr { 1187, 7, 1, 0, "MMX_PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1187 = MMX_PMULHUWrm { 1188, 3, 1, 0, "MMX_PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1188 = MMX_PMULHUWrr { 1189, 7, 1, 0, "MMX_PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1189 = MMX_PMULHWrm { 1190, 3, 1, 0, "MMX_PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1190 = MMX_PMULHWrr { 1191, 7, 1, 0, "MMX_PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1191 = MMX_PMULLWrm { 1192, 3, 1, 0, "MMX_PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1192 = MMX_PMULLWrr { 1193, 7, 1, 0, "MMX_PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1193 = MMX_PMULUDQrm { 1194, 3, 1, 0, "MMX_PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1194 = MMX_PMULUDQrr { 1195, 7, 1, 0, "MMX_PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1195 = MMX_PORrm { 1196, 3, 1, 0, "MMX_PORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1196 = MMX_PORrr { 1197, 7, 1, 0, "MMX_PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1197 = MMX_PSADBWrm { 1198, 3, 1, 0, "MMX_PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1198 = MMX_PSADBWrr { 1199, 7, 1, 0, "MMX_PSHUFWmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo141 }, // Inst #1199 = MMX_PSHUFWmi { 1200, 3, 1, 0, "MMX_PSHUFWri", 0, 0|5|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1200 = MMX_PSHUFWri { 1201, 3, 1, 0, "MMX_PSLLDri", 0, 0|22|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1201 = MMX_PSLLDri { 1202, 7, 1, 0, "MMX_PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1202 = MMX_PSLLDrm { 1203, 3, 1, 0, "MMX_PSLLDrr", 0, 0|5|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1203 = MMX_PSLLDrr { 1204, 3, 1, 0, "MMX_PSLLQri", 0, 0|22|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1204 = MMX_PSLLQri { 1205, 7, 1, 0, "MMX_PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1205 = MMX_PSLLQrm { 1206, 3, 1, 0, "MMX_PSLLQrr", 0, 0|5|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1206 = MMX_PSLLQrr { 1207, 3, 1, 0, "MMX_PSLLWri", 0, 0|22|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1207 = MMX_PSLLWri { 1208, 7, 1, 0, "MMX_PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1208 = MMX_PSLLWrm { 1209, 3, 1, 0, "MMX_PSLLWrr", 0, 0|5|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1209 = MMX_PSLLWrr { 1210, 3, 1, 0, "MMX_PSRADri", 0, 0|20|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1210 = MMX_PSRADri { 1211, 7, 1, 0, "MMX_PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1211 = MMX_PSRADrm { 1212, 3, 1, 0, "MMX_PSRADrr", 0, 0|5|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1212 = MMX_PSRADrr { 1213, 3, 1, 0, "MMX_PSRAWri", 0, 0|20|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1213 = MMX_PSRAWri { 1214, 7, 1, 0, "MMX_PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1214 = MMX_PSRAWrm { 1215, 3, 1, 0, "MMX_PSRAWrr", 0, 0|5|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1215 = MMX_PSRAWrr { 1216, 3, 1, 0, "MMX_PSRLDri", 0, 0|18|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1216 = MMX_PSRLDri { 1217, 7, 1, 0, "MMX_PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1217 = MMX_PSRLDrm { 1218, 3, 1, 0, "MMX_PSRLDrr", 0, 0|5|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1218 = MMX_PSRLDrr { 1219, 3, 1, 0, "MMX_PSRLQri", 0, 0|18|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1219 = MMX_PSRLQri { 1220, 7, 1, 0, "MMX_PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1220 = MMX_PSRLQrm { 1221, 3, 1, 0, "MMX_PSRLQrr", 0, 0|5|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1221 = MMX_PSRLQrr { 1222, 3, 1, 0, "MMX_PSRLWri", 0, 0|18|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1222 = MMX_PSRLWri { 1223, 7, 1, 0, "MMX_PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1223 = MMX_PSRLWrm { 1224, 3, 1, 0, "MMX_PSRLWrr", 0, 0|5|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1224 = MMX_PSRLWrr { 1225, 7, 1, 0, "MMX_PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1225 = MMX_PSUBBrm { 1226, 3, 1, 0, "MMX_PSUBBrr", 0, 0|5|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1226 = MMX_PSUBBrr { 1227, 7, 1, 0, "MMX_PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1227 = MMX_PSUBDrm { 1228, 3, 1, 0, "MMX_PSUBDrr", 0, 0|5|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1228 = MMX_PSUBDrr { 1229, 7, 1, 0, "MMX_PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1229 = MMX_PSUBQrm { 1230, 3, 1, 0, "MMX_PSUBQrr", 0, 0|5|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1230 = MMX_PSUBQrr { 1231, 7, 1, 0, "MMX_PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1231 = MMX_PSUBSBrm { 1232, 3, 1, 0, "MMX_PSUBSBrr", 0, 0|5|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1232 = MMX_PSUBSBrr { 1233, 7, 1, 0, "MMX_PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1233 = MMX_PSUBSWrm { 1234, 3, 1, 0, "MMX_PSUBSWrr", 0, 0|5|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1234 = MMX_PSUBSWrr { 1235, 7, 1, 0, "MMX_PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1235 = MMX_PSUBUSBrm { 1236, 3, 1, 0, "MMX_PSUBUSBrr", 0, 0|5|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1236 = MMX_PSUBUSBrr { 1237, 7, 1, 0, "MMX_PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1237 = MMX_PSUBUSWrm { 1238, 3, 1, 0, "MMX_PSUBUSWrr", 0, 0|5|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1238 = MMX_PSUBUSWrr { 1239, 7, 1, 0, "MMX_PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1239 = MMX_PSUBWrm { 1240, 3, 1, 0, "MMX_PSUBWrr", 0, 0|5|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1240 = MMX_PSUBWrr { 1241, 7, 1, 0, "MMX_PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1241 = MMX_PUNPCKHBWrm { 1242, 3, 1, 0, "MMX_PUNPCKHBWrr", 0, 0|5|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1242 = MMX_PUNPCKHBWrr { 1243, 7, 1, 0, "MMX_PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1243 = MMX_PUNPCKHDQrm { 1244, 3, 1, 0, "MMX_PUNPCKHDQrr", 0, 0|5|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1244 = MMX_PUNPCKHDQrr { 1245, 7, 1, 0, "MMX_PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1245 = MMX_PUNPCKHWDrm { 1246, 3, 1, 0, "MMX_PUNPCKHWDrr", 0, 0|5|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1246 = MMX_PUNPCKHWDrr { 1247, 7, 1, 0, "MMX_PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1247 = MMX_PUNPCKLBWrm { 1248, 3, 1, 0, "MMX_PUNPCKLBWrr", 0, 0|5|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1248 = MMX_PUNPCKLBWrr { 1249, 7, 1, 0, "MMX_PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1249 = MMX_PUNPCKLDQrm { 1250, 3, 1, 0, "MMX_PUNPCKLDQrr", 0, 0|5|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1250 = MMX_PUNPCKLDQrr { 1251, 7, 1, 0, "MMX_PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1251 = MMX_PUNPCKLWDrm { 1252, 3, 1, 0, "MMX_PUNPCKLWDrr", 0, 0|5|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1252 = MMX_PUNPCKLWDrr { 1253, 7, 1, 0, "MMX_PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1253 = MMX_PXORrm { 1254, 3, 1, 0, "MMX_PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1254 = MMX_PXORrr { 1255, 1, 1, 0, "MMX_V_SET0", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1255 = MMX_V_SET0 { 1256, 1, 1, 0, "MMX_V_SETALLONES", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1256 = MMX_V_SETALLONES { 1257, 0, 0, 0, "MONITOR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|37|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1257 = MONITOR { 1258, 1, 1, 0, "MOV16ao16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1258 = MOV16ao16 { 1259, 6, 0, 0, "MOV16mi", 0|(1<<TID::MayStore), 0|24|(1<<6)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1259 = MOV16mi { 1260, 6, 0, 0, "MOV16mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #1260 = MOV16mr { 1261, 6, 1, 0, "MOV16ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1261 = MOV16ms { 1262, 1, 0, 0, "MOV16o16a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1262 = MOV16o16a { 1263, 1, 1, 0, "MOV16r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #1263 = MOV16r0 { 1264, 2, 1, 0, "MOV16ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<6)|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo54 }, // Inst #1264 = MOV16ri { 1265, 6, 1, 0, "MOV16rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1265 = MOV16rm { 1266, 2, 1, 0, "MOV16rr", 0, 0|3|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1266 = MOV16rr { 1267, 2, 1, 0, "MOV16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1267 = MOV16rr_REV { 1268, 2, 1, 0, "MOV16rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(140<<24), NULL, NULL, NULL, OperandInfo146 }, // Inst #1268 = MOV16rs { 1269, 6, 1, 0, "MOV16sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1269 = MOV16sm { 1270, 2, 1, 0, "MOV16sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(142<<24), NULL, NULL, NULL, OperandInfo148 }, // Inst #1270 = MOV16sr { 1271, 1, 1, 0, "MOV32ao32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1271 = MOV32ao32 { 1272, 2, 1, 0, "MOV32cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo149 }, // Inst #1272 = MOV32cr { 1273, 2, 1, 0, "MOV32dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo150 }, // Inst #1273 = MOV32dr { 1274, 6, 0, 0, "MOV32mi", 0|(1<<TID::MayStore), 0|24|(4<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1274 = MOV32mi { 1275, 6, 0, 0, "MOV32mr", 0|(1<<TID::MayStore), 0|4|(137<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1275 = MOV32mr { 1276, 1, 0, 0, "MOV32o32a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1276 = MOV32o32a { 1277, 1, 1, 0, "MOV32r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #1277 = MOV32r0 { 1278, 2, 1, 0, "MOV32rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo151 }, // Inst #1278 = MOV32rc { 1279, 2, 1, 0, "MOV32rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo152 }, // Inst #1279 = MOV32rd { 1280, 2, 1, 0, "MOV32ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(4<<13)|(184<<24), NULL, NULL, NULL, OperandInfo55 }, // Inst #1280 = MOV32ri { 1281, 6, 1, 0, "MOV32rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1281 = MOV32rm { 1282, 2, 1, 0, "MOV32rr", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1282 = MOV32rr { 1283, 2, 1, 0, "MOV32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1283 = MOV32rr_REV { 1284, 6, 1, 0, "MOV64FSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1284 = MOV64FSrm { 1285, 6, 1, 0, "MOV64GSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1285 = MOV64GSrm { 1286, 1, 1, 0, "MOV64ao64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1286 = MOV64ao64 { 1287, 1, 1, 0, "MOV64ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1287 = MOV64ao8 { 1288, 2, 1, 0, "MOV64cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo153 }, // Inst #1288 = MOV64cr { 1289, 2, 1, 0, "MOV64dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1289 = MOV64dr { 1290, 6, 0, 0, "MOV64mi32", 0|(1<<TID::MayStore), 0|24|(1<<12)|(4<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1290 = MOV64mi32 { 1291, 6, 0, 0, "MOV64mr", 0|(1<<TID::MayStore), 0|4|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #1291 = MOV64mr { 1292, 6, 1, 0, "MOV64ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1292 = MOV64ms { 1293, 1, 0, 0, "MOV64o64a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1293 = MOV64o64a { 1294, 1, 0, 0, "MOV64o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1294 = MOV64o8a { 1295, 1, 1, 0, "MOV64r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #1295 = MOV64r0 { 1296, 2, 1, 0, "MOV64rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo155 }, // Inst #1296 = MOV64rc { 1297, 2, 1, 0, "MOV64rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo156 }, // Inst #1297 = MOV64rd { 1298, 2, 1, 0, "MOV64ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<12)|(6<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1298 = MOV64ri { 1299, 2, 1, 0, "MOV64ri32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|16|(1<<12)|(4<<13)|(199<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1299 = MOV64ri32 { 1300, 2, 1, 0, "MOV64ri64i32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(4<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1300 = MOV64ri64i32 { 1301, 6, 1, 0, "MOV64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1301 = MOV64rm { 1302, 2, 1, 0, "MOV64rr", 0, 0|3|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1302 = MOV64rr { 1303, 2, 1, 0, "MOV64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1303 = MOV64rr_REV { 1304, 2, 1, 0, "MOV64rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo157 }, // Inst #1304 = MOV64rs { 1305, 6, 1, 0, "MOV64sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1305 = MOV64sm { 1306, 2, 1, 0, "MOV64sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo158 }, // Inst #1306 = MOV64sr { 1307, 2, 1, 0, "MOV64toPQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1307 = MOV64toPQIrr { 1308, 6, 1, 0, "MOV64toSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1308 = MOV64toSDrm { 1309, 2, 1, 0, "MOV64toSDrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #1309 = MOV64toSDrr { 1310, 1, 1, 0, "MOV8ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1310 = MOV8ao8 { 1311, 6, 0, 0, "MOV8mi", 0|(1<<TID::MayStore), 0|24|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1311 = MOV8mi { 1312, 6, 0, 0, "MOV8mr", 0|(1<<TID::MayStore), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #1312 = MOV8mr { 1313, 6, 0, 0, "MOV8mr_NOREX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo160 }, // Inst #1313 = MOV8mr_NOREX { 1314, 1, 0, 0, "MOV8o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1314 = MOV8o8a { 1315, 1, 1, 0, "MOV8r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #1315 = MOV8r0 { 1316, 2, 1, 0, "MOV8ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<13)|(176<<24), NULL, NULL, NULL, OperandInfo68 }, // Inst #1316 = MOV8ri { 1317, 6, 1, 0, "MOV8rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo69 }, // Inst #1317 = MOV8rm { 1318, 6, 1, 0, "MOV8rm_NOREX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo161 }, // Inst #1318 = MOV8rm_NOREX { 1319, 2, 1, 0, "MOV8rr", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1319 = MOV8rr { 1320, 2, 1, 0, "MOV8rr_NOREX", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo162 }, // Inst #1320 = MOV8rr_NOREX { 1321, 2, 1, 0, "MOV8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(138<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1321 = MOV8rr_REV { 1322, 6, 0, 0, "MOVAPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1322 = MOVAPDmr { 1323, 6, 1, 0, "MOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1323 = MOVAPDrm { 1324, 2, 1, 0, "MOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1324 = MOVAPDrr { 1325, 6, 0, 0, "MOVAPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1325 = MOVAPSmr { 1326, 6, 1, 0, "MOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1326 = MOVAPSrm { 1327, 2, 1, 0, "MOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1327 = MOVAPSrr { 1328, 6, 1, 0, "MOVDDUPrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1328 = MOVDDUPrm { 1329, 2, 1, 0, "MOVDDUPrr", 0, 0|5|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1329 = MOVDDUPrr { 1330, 6, 1, 0, "MOVDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1330 = MOVDI2PDIrm { 1331, 2, 1, 0, "MOVDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1331 = MOVDI2PDIrr { 1332, 6, 1, 0, "MOVDI2SSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1332 = MOVDI2SSrm { 1333, 2, 1, 0, "MOVDI2SSrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #1333 = MOVDI2SSrr { 1334, 6, 0, 0, "MOVDQAmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1334 = MOVDQAmr { 1335, 6, 1, 0, "MOVDQArm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1335 = MOVDQArm { 1336, 2, 1, 0, "MOVDQArr", 0, 0|5|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1336 = MOVDQArr { 1337, 6, 0, 0, "MOVDQUmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1337 = MOVDQUmr { 1338, 6, 0, 0, "MOVDQUmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1338 = MOVDQUmr_Int { 1339, 6, 1, 0, "MOVDQUrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1339 = MOVDQUrm { 1340, 6, 1, 0, "MOVDQUrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1340 = MOVDQUrm_Int { 1341, 3, 1, 0, "MOVHLPSrr", 0, 0|5|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1341 = MOVHLPSrr { 1342, 6, 0, 0, "MOVHPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1342 = MOVHPDmr { 1343, 7, 1, 0, "MOVHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1343 = MOVHPDrm { 1344, 6, 0, 0, "MOVHPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1344 = MOVHPSmr { 1345, 7, 1, 0, "MOVHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1345 = MOVHPSrm { 1346, 3, 1, 0, "MOVLHPSrr", 0, 0|5|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1346 = MOVLHPSrr { 1347, 6, 0, 0, "MOVLPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1347 = MOVLPDmr { 1348, 7, 1, 0, "MOVLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1348 = MOVLPDrm { 1349, 6, 0, 0, "MOVLPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1349 = MOVLPSmr { 1350, 7, 1, 0, "MOVLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1350 = MOVLPSrm { 1351, 6, 0, 0, "MOVLQ128mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1351 = MOVLQ128mr { 1352, 2, 1, 0, "MOVMSKPDrr", 0, 0|5|(1<<6)|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1352 = MOVMSKPDrr { 1353, 2, 1, 0, "MOVMSKPSrr", 0, 0|5|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1353 = MOVMSKPSrr { 1354, 6, 1, 0, "MOVNTDQArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1354 = MOVNTDQArm { 1355, 6, 0, 0, "MOVNTDQ_64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1355 = MOVNTDQ_64mr { 1356, 6, 0, 0, "MOVNTDQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1356 = MOVNTDQmr { 1357, 6, 0, 0, "MOVNTDQmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1357 = MOVNTDQmr_Int { 1358, 6, 0, 0, "MOVNTI_64mr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(195<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #1358 = MOVNTI_64mr { 1359, 6, 0, 0, "MOVNTImr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1359 = MOVNTImr { 1360, 6, 0, 0, "MOVNTImr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1360 = MOVNTImr_Int { 1361, 6, 0, 0, "MOVNTPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1361 = MOVNTPDmr { 1362, 6, 0, 0, "MOVNTPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1362 = MOVNTPDmr_Int { 1363, 6, 0, 0, "MOVNTPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1363 = MOVNTPSmr { 1364, 6, 0, 0, "MOVNTPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1364 = MOVNTPSmr_Int { 1365, 2, 1, 0, "MOVPC32r", 0|(1<<TID::NotDuplicable), 0|(4<<13)|(232<<24), ImplicitList2, NULL, NULL, OperandInfo55 }, // Inst #1365 = MOVPC32r { 1366, 6, 0, 0, "MOVPDI2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1366 = MOVPDI2DImr { 1367, 2, 1, 0, "MOVPDI2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1367 = MOVPDI2DIrr { 1368, 6, 0, 0, "MOVPQI2QImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1368 = MOVPQI2QImr { 1369, 2, 1, 0, "MOVPQIto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1369 = MOVPQIto64rr { 1370, 6, 1, 0, "MOVQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1370 = MOVQI2PQIrm { 1371, 2, 1, 0, "MOVQxrxr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1371 = MOVQxrxr { 1372, 0, 0, 0, "MOVSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(164<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1372 = MOVSB { 1373, 0, 0, 0, "MOVSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(165<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1373 = MOVSD { 1374, 6, 0, 0, "MOVSDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1374 = MOVSDmr { 1375, 6, 1, 0, "MOVSDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1375 = MOVSDrm { 1376, 3, 1, 0, "MOVSDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo166 }, // Inst #1376 = MOVSDrr { 1377, 6, 0, 0, "MOVSDto64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1377 = MOVSDto64mr { 1378, 2, 1, 0, "MOVSDto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #1378 = MOVSDto64rr { 1379, 6, 1, 0, "MOVSHDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1379 = MOVSHDUPrm { 1380, 2, 1, 0, "MOVSHDUPrr", 0, 0|5|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1380 = MOVSHDUPrr { 1381, 6, 1, 0, "MOVSLDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1381 = MOVSLDUPrm { 1382, 2, 1, 0, "MOVSLDUPrr", 0, 0|5|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1382 = MOVSLDUPrr { 1383, 6, 0, 0, "MOVSS2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1383 = MOVSS2DImr { 1384, 2, 1, 0, "MOVSS2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #1384 = MOVSS2DIrr { 1385, 6, 0, 0, "MOVSSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1385 = MOVSSmr { 1386, 6, 1, 0, "MOVSSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1386 = MOVSSrm { 1387, 3, 1, 0, "MOVSSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo168 }, // Inst #1387 = MOVSSrr { 1388, 0, 0, 0, "MOVSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(165<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1388 = MOVSW { 1389, 6, 1, 0, "MOVSX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1389 = MOVSX16rm8 { 1390, 6, 1, 0, "MOVSX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1390 = MOVSX16rm8W { 1391, 2, 1, 0, "MOVSX16rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1391 = MOVSX16rr8 { 1392, 2, 1, 0, "MOVSX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1392 = MOVSX16rr8W { 1393, 6, 1, 0, "MOVSX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1393 = MOVSX32rm16 { 1394, 6, 1, 0, "MOVSX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1394 = MOVSX32rm8 { 1395, 2, 1, 0, "MOVSX32rr16", 0, 0|5|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1395 = MOVSX32rr16 { 1396, 2, 1, 0, "MOVSX32rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1396 = MOVSX32rr8 { 1397, 6, 1, 0, "MOVSX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1397 = MOVSX64rm16 { 1398, 6, 1, 0, "MOVSX64rm32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1398 = MOVSX64rm32 { 1399, 6, 1, 0, "MOVSX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1399 = MOVSX64rm8 { 1400, 2, 1, 0, "MOVSX64rr16", 0, 0|5|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1400 = MOVSX64rr16 { 1401, 2, 1, 0, "MOVSX64rr32", 0, 0|5|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1401 = MOVSX64rr32 { 1402, 2, 1, 0, "MOVSX64rr8", 0, 0|5|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1402 = MOVSX64rr8 { 1403, 6, 0, 0, "MOVUPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1403 = MOVUPDmr { 1404, 6, 0, 0, "MOVUPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1404 = MOVUPDmr_Int { 1405, 6, 1, 0, "MOVUPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1405 = MOVUPDrm { 1406, 6, 1, 0, "MOVUPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1406 = MOVUPDrm_Int { 1407, 2, 1, 0, "MOVUPDrr", 0, 0|5|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1407 = MOVUPDrr { 1408, 6, 0, 0, "MOVUPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1408 = MOVUPSmr { 1409, 6, 0, 0, "MOVUPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1409 = MOVUPSmr_Int { 1410, 6, 1, 0, "MOVUPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1410 = MOVUPSrm { 1411, 6, 1, 0, "MOVUPSrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1411 = MOVUPSrm_Int { 1412, 2, 1, 0, "MOVUPSrr", 0, 0|5|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1412 = MOVUPSrr { 1413, 6, 1, 0, "MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1413 = MOVZDI2PDIrm { 1414, 2, 1, 0, "MOVZDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1414 = MOVZDI2PDIrr { 1415, 6, 1, 0, "MOVZPQILo2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1415 = MOVZPQILo2PQIrm { 1416, 2, 1, 0, "MOVZPQILo2PQIrr", 0, 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1416 = MOVZPQILo2PQIrr { 1417, 6, 1, 0, "MOVZQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1417 = MOVZQI2PQIrm { 1418, 2, 1, 0, "MOVZQI2PQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1418 = MOVZQI2PQIrr { 1419, 6, 1, 0, "MOVZX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1419 = MOVZX16rm8 { 1420, 6, 1, 0, "MOVZX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1420 = MOVZX16rm8W { 1421, 2, 1, 0, "MOVZX16rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1421 = MOVZX16rr8 { 1422, 2, 1, 0, "MOVZX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1422 = MOVZX16rr8W { 1423, 6, 1, 0, "MOVZX32_NOREXrm8", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1423 = MOVZX32_NOREXrm8 { 1424, 2, 1, 0, "MOVZX32_NOREXrr8", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1424 = MOVZX32_NOREXrr8 { 1425, 6, 1, 0, "MOVZX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1425 = MOVZX32rm16 { 1426, 6, 1, 0, "MOVZX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1426 = MOVZX32rm8 { 1427, 2, 1, 0, "MOVZX32rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1427 = MOVZX32rr16 { 1428, 2, 1, 0, "MOVZX32rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1428 = MOVZX32rr8 { 1429, 6, 1, 0, "MOVZX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1429 = MOVZX64rm16 { 1430, 6, 1, 0, "MOVZX64rm16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1430 = MOVZX64rm16_Q { 1431, 6, 1, 0, "MOVZX64rm32", 0|(1<<TID::MayLoad), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1431 = MOVZX64rm32 { 1432, 6, 1, 0, "MOVZX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1432 = MOVZX64rm8 { 1433, 6, 1, 0, "MOVZX64rm8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1433 = MOVZX64rm8_Q { 1434, 2, 1, 0, "MOVZX64rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1434 = MOVZX64rr16 { 1435, 2, 1, 0, "MOVZX64rr16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1435 = MOVZX64rr16_Q { 1436, 2, 1, 0, "MOVZX64rr32", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1436 = MOVZX64rr32 { 1437, 2, 1, 0, "MOVZX64rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1437 = MOVZX64rr8 { 1438, 2, 1, 0, "MOVZX64rr8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1438 = MOVZX64rr8_Q { 1439, 2, 1, 0, "MOV_Fp3232", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #1439 = MOV_Fp3232 { 1440, 2, 1, 0, "MOV_Fp3264", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo176 }, // Inst #1440 = MOV_Fp3264 { 1441, 2, 1, 0, "MOV_Fp3280", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo177 }, // Inst #1441 = MOV_Fp3280 { 1442, 2, 1, 0, "MOV_Fp6432", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo178 }, // Inst #1442 = MOV_Fp6432 { 1443, 2, 1, 0, "MOV_Fp6464", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #1443 = MOV_Fp6464 { 1444, 2, 1, 0, "MOV_Fp6480", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo179 }, // Inst #1444 = MOV_Fp6480 { 1445, 2, 1, 0, "MOV_Fp8032", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo180 }, // Inst #1445 = MOV_Fp8032 { 1446, 2, 1, 0, "MOV_Fp8064", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo181 }, // Inst #1446 = MOV_Fp8064 { 1447, 2, 1, 0, "MOV_Fp8080", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #1447 = MOV_Fp8080 { 1448, 8, 1, 0, "MPSADBWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1448 = MPSADBWrmi { 1449, 4, 1, 0, "MPSADBWrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1449 = MPSADBWrri { 1450, 5, 0, 0, "MUL16m", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #1450 = MUL16m { 1451, 1, 0, 0, "MUL16r", 0, 0|20|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #1451 = MUL16r { 1452, 5, 0, 0, "MUL32m", 0|(1<<TID::MayLoad), 0|28|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #1452 = MUL32m { 1453, 1, 0, 0, "MUL32r", 0, 0|20|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #1453 = MUL32r { 1454, 5, 0, 0, "MUL64m", 0|(1<<TID::MayLoad), 0|28|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #1454 = MUL64m { 1455, 1, 0, 0, "MUL64r", 0, 0|20|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #1455 = MUL64r { 1456, 5, 0, 0, "MUL8m", 0|(1<<TID::MayLoad), 0|28|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #1456 = MUL8m { 1457, 1, 0, 0, "MUL8r", 0, 0|20|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #1457 = MUL8r { 1458, 7, 1, 0, "MULPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1458 = MULPDrm { 1459, 3, 1, 0, "MULPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1459 = MULPDrr { 1460, 7, 1, 0, "MULPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1460 = MULPSrm { 1461, 3, 1, 0, "MULPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1461 = MULPSrr { 1462, 7, 1, 0, "MULSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1462 = MULSDrm { 1463, 7, 1, 0, "MULSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1463 = MULSDrm_Int { 1464, 3, 1, 0, "MULSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1464 = MULSDrr { 1465, 3, 1, 0, "MULSDrr_Int", 0, 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1465 = MULSDrr_Int { 1466, 7, 1, 0, "MULSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1466 = MULSSrm { 1467, 7, 1, 0, "MULSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1467 = MULSSrm_Int { 1468, 3, 1, 0, "MULSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1468 = MULSSrr { 1469, 3, 1, 0, "MULSSrr_Int", 0, 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1469 = MULSSrr_Int { 1470, 5, 0, 0, "MUL_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1470 = MUL_F32m { 1471, 5, 0, 0, "MUL_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1471 = MUL_F64m { 1472, 5, 0, 0, "MUL_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1472 = MUL_FI16m { 1473, 5, 0, 0, "MUL_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1473 = MUL_FI32m { 1474, 1, 0, 0, "MUL_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1474 = MUL_FPrST0 { 1475, 1, 0, 0, "MUL_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1475 = MUL_FST0r { 1476, 3, 1, 0, "MUL_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1476 = MUL_Fp32 { 1477, 7, 1, 0, "MUL_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1477 = MUL_Fp32m { 1478, 3, 1, 0, "MUL_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1478 = MUL_Fp64 { 1479, 7, 1, 0, "MUL_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1479 = MUL_Fp64m { 1480, 7, 1, 0, "MUL_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1480 = MUL_Fp64m32 { 1481, 3, 1, 0, "MUL_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1481 = MUL_Fp80 { 1482, 7, 1, 0, "MUL_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1482 = MUL_Fp80m32 { 1483, 7, 1, 0, "MUL_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1483 = MUL_Fp80m64 { 1484, 7, 1, 0, "MUL_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1484 = MUL_FpI16m32 { 1485, 7, 1, 0, "MUL_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1485 = MUL_FpI16m64 { 1486, 7, 1, 0, "MUL_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1486 = MUL_FpI16m80 { 1487, 7, 1, 0, "MUL_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1487 = MUL_FpI32m32 { 1488, 7, 1, 0, "MUL_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1488 = MUL_FpI32m64 { 1489, 7, 1, 0, "MUL_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1489 = MUL_FpI32m80 { 1490, 1, 0, 0, "MUL_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1490 = MUL_FrST0 { 1491, 0, 0, 0, "MWAIT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|38|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1491 = MWAIT { 1492, 5, 0, 0, "NEG16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1492 = NEG16m { 1493, 2, 1, 0, "NEG16r", 0, 0|19|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1493 = NEG16r { 1494, 5, 0, 0, "NEG32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1494 = NEG32m { 1495, 2, 1, 0, "NEG32r", 0, 0|19|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1495 = NEG32r { 1496, 5, 0, 0, "NEG64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1496 = NEG64m { 1497, 2, 1, 0, "NEG64r", 0, 0|19|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1497 = NEG64r { 1498, 5, 0, 0, "NEG8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1498 = NEG8m { 1499, 2, 1, 0, "NEG8r", 0, 0|19|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1499 = NEG8r { 1500, 0, 0, 0, "NOOP", 0, 0|1|(144<<24), NULL, NULL, NULL, 0 }, // Inst #1500 = NOOP { 1501, 5, 0, 0, "NOOPL", 0, 0|24|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1501 = NOOPL { 1502, 5, 0, 0, "NOOPW", 0, 0|24|(1<<6)|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1502 = NOOPW { 1503, 5, 0, 0, "NOT16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1503 = NOT16m { 1504, 2, 1, 0, "NOT16r", 0, 0|18|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo91 }, // Inst #1504 = NOT16r { 1505, 5, 0, 0, "NOT32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1505 = NOT32m { 1506, 2, 1, 0, "NOT32r", 0, 0|18|(247<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #1506 = NOT32r { 1507, 5, 0, 0, "NOT64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1507 = NOT64m { 1508, 2, 1, 0, "NOT64r", 0, 0|18|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #1508 = NOT64r { 1509, 5, 0, 0, "NOT8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(246<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1509 = NOT8m { 1510, 2, 1, 0, "NOT8r", 0, 0|18|(246<<24), NULL, NULL, NULL, OperandInfo92 }, // Inst #1510 = NOT8r { 1511, 1, 0, 0, "OR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1511 = OR16i16 { 1512, 6, 0, 0, "OR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1512 = OR16mi { 1513, 6, 0, 0, "OR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1513 = OR16mi8 { 1514, 6, 0, 0, "OR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1514 = OR16mr { 1515, 3, 1, 0, "OR16ri", 0, 0|17|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1515 = OR16ri { 1516, 3, 1, 0, "OR16ri8", 0, 0|17|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1516 = OR16ri8 { 1517, 7, 1, 0, "OR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1517 = OR16rm { 1518, 3, 1, 0, "OR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1518 = OR16rr { 1519, 3, 1, 0, "OR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1519 = OR16rr_REV { 1520, 1, 0, 0, "OR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1520 = OR32i32 { 1521, 6, 0, 0, "OR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1521 = OR32mi { 1522, 6, 0, 0, "OR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1522 = OR32mi8 { 1523, 6, 0, 0, "OR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1523 = OR32mr { 1524, 3, 1, 0, "OR32ri", 0, 0|17|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1524 = OR32ri { 1525, 3, 1, 0, "OR32ri8", 0, 0|17|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1525 = OR32ri8 { 1526, 7, 1, 0, "OR32rm", 0|(1<<TID::MayLoad), 0|6|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1526 = OR32rm { 1527, 3, 1, 0, "OR32rr", 0|(1<<TID::Commutable), 0|3|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1527 = OR32rr { 1528, 3, 1, 0, "OR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1528 = OR32rr_REV { 1529, 1, 0, 0, "OR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1529 = OR64i32 { 1530, 6, 0, 0, "OR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1530 = OR64mi32 { 1531, 6, 0, 0, "OR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1531 = OR64mi8 { 1532, 6, 0, 0, "OR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1532 = OR64mr { 1533, 3, 1, 0, "OR64ri32", 0, 0|17|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1533 = OR64ri32 { 1534, 3, 1, 0, "OR64ri8", 0, 0|17|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1534 = OR64ri8 { 1535, 7, 1, 0, "OR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1535 = OR64rm { 1536, 3, 1, 0, "OR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1536 = OR64rr { 1537, 3, 1, 0, "OR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1537 = OR64rr_REV { 1538, 1, 0, 0, "OR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(12<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1538 = OR8i8 { 1539, 6, 0, 0, "OR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1539 = OR8mi { 1540, 6, 0, 0, "OR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1540 = OR8mr { 1541, 3, 1, 0, "OR8ri", 0, 0|17|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1541 = OR8ri { 1542, 7, 1, 0, "OR8rm", 0|(1<<TID::MayLoad), 0|6|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1542 = OR8rm { 1543, 3, 1, 0, "OR8rr", 0|(1<<TID::Commutable), 0|3|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1543 = OR8rr { 1544, 3, 1, 0, "OR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1544 = OR8rr_REV { 1545, 7, 1, 0, "ORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1545 = ORPDrm { 1546, 3, 1, 0, "ORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1546 = ORPDrr { 1547, 7, 1, 0, "ORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1547 = ORPSrm { 1548, 3, 1, 0, "ORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1548 = ORPSrr { 1549, 1, 0, 0, "OUT16ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(231<<24), ImplicitList12, NULL, NULL, OperandInfo5 }, // Inst #1549 = OUT16ir { 1550, 0, 0, 0, "OUT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(239<<24), ImplicitList39, NULL, NULL, 0 }, // Inst #1550 = OUT16rr { 1551, 1, 0, 0, "OUT32ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(231<<24), ImplicitList13, NULL, NULL, OperandInfo5 }, // Inst #1551 = OUT32ir { 1552, 0, 0, 0, "OUT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(239<<24), ImplicitList40, NULL, NULL, 0 }, // Inst #1552 = OUT32rr { 1553, 1, 0, 0, "OUT8ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(230<<24), ImplicitList11, NULL, NULL, OperandInfo5 }, // Inst #1553 = OUT8ir { 1554, 0, 0, 0, "OUT8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(238<<24), ImplicitList41, NULL, NULL, 0 }, // Inst #1554 = OUT8rr { 1555, 0, 0, 0, "OUTSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(110<<24), NULL, NULL, NULL, 0 }, // Inst #1555 = OUTSB { 1556, 0, 0, 0, "OUTSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1556 = OUTSD { 1557, 0, 0, 0, "OUTSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1557 = OUTSW { 1558, 6, 1, 0, "PABSBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1558 = PABSBrm128 { 1559, 6, 1, 0, "PABSBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1559 = PABSBrm64 { 1560, 2, 1, 0, "PABSBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1560 = PABSBrr128 { 1561, 2, 1, 0, "PABSBrr64", 0, 0|5|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1561 = PABSBrr64 { 1562, 6, 1, 0, "PABSDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1562 = PABSDrm128 { 1563, 6, 1, 0, "PABSDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1563 = PABSDrm64 { 1564, 2, 1, 0, "PABSDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1564 = PABSDrr128 { 1565, 2, 1, 0, "PABSDrr64", 0, 0|5|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1565 = PABSDrr64 { 1566, 6, 1, 0, "PABSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1566 = PABSWrm128 { 1567, 6, 1, 0, "PABSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1567 = PABSWrm64 { 1568, 2, 1, 0, "PABSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1568 = PABSWrr128 { 1569, 2, 1, 0, "PABSWrr64", 0, 0|5|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1569 = PABSWrr64 { 1570, 7, 1, 0, "PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1570 = PACKSSDWrm { 1571, 3, 1, 0, "PACKSSDWrr", 0, 0|5|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1571 = PACKSSDWrr { 1572, 7, 1, 0, "PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1572 = PACKSSWBrm { 1573, 3, 1, 0, "PACKSSWBrr", 0, 0|5|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1573 = PACKSSWBrr { 1574, 7, 1, 0, "PACKUSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1574 = PACKUSDWrm { 1575, 3, 1, 0, "PACKUSDWrr", 0, 0|5|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1575 = PACKUSDWrr { 1576, 7, 1, 0, "PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1576 = PACKUSWBrm { 1577, 3, 1, 0, "PACKUSWBrr", 0, 0|5|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1577 = PACKUSWBrr { 1578, 7, 1, 0, "PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1578 = PADDBrm { 1579, 3, 1, 0, "PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1579 = PADDBrr { 1580, 7, 1, 0, "PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1580 = PADDDrm { 1581, 3, 1, 0, "PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1581 = PADDDrr { 1582, 7, 1, 0, "PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1582 = PADDQrm { 1583, 3, 1, 0, "PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1583 = PADDQrr { 1584, 7, 1, 0, "PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1584 = PADDSBrm { 1585, 3, 1, 0, "PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1585 = PADDSBrr { 1586, 7, 1, 0, "PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1586 = PADDSWrm { 1587, 3, 1, 0, "PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1587 = PADDSWrr { 1588, 7, 1, 0, "PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1588 = PADDUSBrm { 1589, 3, 1, 0, "PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1589 = PADDUSBrr { 1590, 7, 1, 0, "PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1590 = PADDUSWrm { 1591, 3, 1, 0, "PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1591 = PADDUSWrr { 1592, 7, 1, 0, "PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1592 = PADDWrm { 1593, 3, 1, 0, "PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1593 = PADDWrr { 1594, 8, 1, 0, "PALIGNR128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1594 = PALIGNR128rm { 1595, 4, 1, 0, "PALIGNR128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1595 = PALIGNR128rr { 1596, 8, 1, 0, "PALIGNR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1596 = PALIGNR64rm { 1597, 4, 1, 0, "PALIGNR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo182 }, // Inst #1597 = PALIGNR64rr { 1598, 7, 1, 0, "PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1598 = PANDNrm { 1599, 3, 1, 0, "PANDNrr", 0, 0|5|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1599 = PANDNrr { 1600, 7, 1, 0, "PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1600 = PANDrm { 1601, 3, 1, 0, "PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1601 = PANDrr { 1602, 7, 1, 0, "PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1602 = PAVGBrm { 1603, 3, 1, 0, "PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1603 = PAVGBrr { 1604, 7, 1, 0, "PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1604 = PAVGWrm { 1605, 3, 1, 0, "PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1605 = PAVGWrr { 1606, 7, 1, 0, "PBLENDVBrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #1606 = PBLENDVBrm0 { 1607, 3, 1, 0, "PBLENDVBrr0", 0, 0|5|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #1607 = PBLENDVBrr0 { 1608, 8, 1, 0, "PBLENDWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1608 = PBLENDWrmi { 1609, 4, 1, 0, "PBLENDWrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1609 = PBLENDWrri { 1610, 7, 1, 0, "PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1610 = PCMPEQBrm { 1611, 3, 1, 0, "PCMPEQBrr", 0, 0|5|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1611 = PCMPEQBrr { 1612, 7, 1, 0, "PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1612 = PCMPEQDrm { 1613, 3, 1, 0, "PCMPEQDrr", 0, 0|5|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1613 = PCMPEQDrr { 1614, 7, 1, 0, "PCMPEQQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1614 = PCMPEQQrm { 1615, 3, 1, 0, "PCMPEQQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1615 = PCMPEQQrr { 1616, 7, 1, 0, "PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1616 = PCMPEQWrm { 1617, 3, 1, 0, "PCMPEQWrr", 0, 0|5|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1617 = PCMPEQWrr { 1618, 7, 0, 0, "PCMPESTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1618 = PCMPESTRIArm { 1619, 3, 0, 0, "PCMPESTRIArr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1619 = PCMPESTRIArr { 1620, 7, 0, 0, "PCMPESTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1620 = PCMPESTRICrm { 1621, 3, 0, 0, "PCMPESTRICrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1621 = PCMPESTRICrr { 1622, 7, 0, 0, "PCMPESTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1622 = PCMPESTRIOrm { 1623, 3, 0, 0, "PCMPESTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1623 = PCMPESTRIOrr { 1624, 7, 0, 0, "PCMPESTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1624 = PCMPESTRISrm { 1625, 3, 0, 0, "PCMPESTRISrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1625 = PCMPESTRISrr { 1626, 7, 0, 0, "PCMPESTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1626 = PCMPESTRIZrm { 1627, 3, 0, 0, "PCMPESTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1627 = PCMPESTRIZrr { 1628, 7, 0, 0, "PCMPESTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1628 = PCMPESTRIrm { 1629, 3, 0, 0, "PCMPESTRIrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1629 = PCMPESTRIrr { 1630, 8, 1, 0, "PCMPESTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1630 = PCMPESTRM128MEM { 1631, 4, 1, 0, "PCMPESTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1631 = PCMPESTRM128REG { 1632, 7, 0, 0, "PCMPESTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList43, Barriers1, OperandInfo183 }, // Inst #1632 = PCMPESTRM128rm { 1633, 3, 0, 0, "PCMPESTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList43, Barriers1, OperandInfo184 }, // Inst #1633 = PCMPESTRM128rr { 1634, 7, 1, 0, "PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1634 = PCMPGTBrm { 1635, 3, 1, 0, "PCMPGTBrr", 0, 0|5|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1635 = PCMPGTBrr { 1636, 7, 1, 0, "PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1636 = PCMPGTDrm { 1637, 3, 1, 0, "PCMPGTDrr", 0, 0|5|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1637 = PCMPGTDrr { 1638, 7, 1, 0, "PCMPGTQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1638 = PCMPGTQrm { 1639, 3, 1, 0, "PCMPGTQrr", 0, 0|5|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1639 = PCMPGTQrr { 1640, 7, 1, 0, "PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1640 = PCMPGTWrm { 1641, 3, 1, 0, "PCMPGTWrr", 0, 0|5|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1641 = PCMPGTWrr { 1642, 7, 0, 0, "PCMPISTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1642 = PCMPISTRIArm { 1643, 3, 0, 0, "PCMPISTRIArr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1643 = PCMPISTRIArr { 1644, 7, 0, 0, "PCMPISTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1644 = PCMPISTRICrm { 1645, 3, 0, 0, "PCMPISTRICrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1645 = PCMPISTRICrr { 1646, 7, 0, 0, "PCMPISTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1646 = PCMPISTRIOrm { 1647, 3, 0, 0, "PCMPISTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1647 = PCMPISTRIOrr { 1648, 7, 0, 0, "PCMPISTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1648 = PCMPISTRISrm { 1649, 3, 0, 0, "PCMPISTRISrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1649 = PCMPISTRISrr { 1650, 7, 0, 0, "PCMPISTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1650 = PCMPISTRIZrm { 1651, 3, 0, 0, "PCMPISTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1651 = PCMPISTRIZrr { 1652, 7, 0, 0, "PCMPISTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1652 = PCMPISTRIrm { 1653, 3, 0, 0, "PCMPISTRIrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1653 = PCMPISTRIrr { 1654, 8, 1, 0, "PCMPISTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1654 = PCMPISTRM128MEM { 1655, 4, 1, 0, "PCMPISTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1655 = PCMPISTRM128REG { 1656, 7, 0, 0, "PCMPISTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList43, Barriers1, OperandInfo183 }, // Inst #1656 = PCMPISTRM128rm { 1657, 3, 0, 0, "PCMPISTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList43, Barriers1, OperandInfo184 }, // Inst #1657 = PCMPISTRM128rr { 1658, 7, 0, 0, "PEXTRBmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1658 = PEXTRBmr { 1659, 3, 1, 0, "PEXTRBrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1659 = PEXTRBrr { 1660, 7, 0, 0, "PEXTRDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1660 = PEXTRDmr { 1661, 3, 1, 0, "PEXTRDrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1661 = PEXTRDrr { 1662, 7, 0, 0, "PEXTRQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1662 = PEXTRQmr { 1663, 3, 1, 0, "PEXTRQrr", 0, 0|3|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo186 }, // Inst #1663 = PEXTRQrr { 1664, 7, 0, 0, "PEXTRWmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(21<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1664 = PEXTRWmr { 1665, 3, 1, 0, "PEXTRWri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1665 = PEXTRWri { 1666, 7, 1, 0, "PHADDDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1666 = PHADDDrm128 { 1667, 7, 1, 0, "PHADDDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1667 = PHADDDrm64 { 1668, 3, 1, 0, "PHADDDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1668 = PHADDDrr128 { 1669, 3, 1, 0, "PHADDDrr64", 0, 0|5|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1669 = PHADDDrr64 { 1670, 7, 1, 0, "PHADDSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1670 = PHADDSWrm128 { 1671, 7, 1, 0, "PHADDSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1671 = PHADDSWrm64 { 1672, 3, 1, 0, "PHADDSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1672 = PHADDSWrr128 { 1673, 3, 1, 0, "PHADDSWrr64", 0, 0|5|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1673 = PHADDSWrr64 { 1674, 7, 1, 0, "PHADDWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1674 = PHADDWrm128 { 1675, 7, 1, 0, "PHADDWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1675 = PHADDWrm64 { 1676, 3, 1, 0, "PHADDWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1676 = PHADDWrr128 { 1677, 3, 1, 0, "PHADDWrr64", 0, 0|5|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1677 = PHADDWrr64 { 1678, 6, 1, 0, "PHMINPOSUWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1678 = PHMINPOSUWrm128 { 1679, 2, 1, 0, "PHMINPOSUWrr128", 0, 0|5|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1679 = PHMINPOSUWrr128 { 1680, 7, 1, 0, "PHSUBDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1680 = PHSUBDrm128 { 1681, 7, 1, 0, "PHSUBDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1681 = PHSUBDrm64 { 1682, 3, 1, 0, "PHSUBDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1682 = PHSUBDrr128 { 1683, 3, 1, 0, "PHSUBDrr64", 0, 0|5|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1683 = PHSUBDrr64 { 1684, 7, 1, 0, "PHSUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1684 = PHSUBSWrm128 { 1685, 7, 1, 0, "PHSUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1685 = PHSUBSWrm64 { 1686, 3, 1, 0, "PHSUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1686 = PHSUBSWrr128 { 1687, 3, 1, 0, "PHSUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1687 = PHSUBSWrr64 { 1688, 7, 1, 0, "PHSUBWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1688 = PHSUBWrm128 { 1689, 7, 1, 0, "PHSUBWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1689 = PHSUBWrm64 { 1690, 3, 1, 0, "PHSUBWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1690 = PHSUBWrr128 { 1691, 3, 1, 0, "PHSUBWrr64", 0, 0|5|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1691 = PHSUBWrr64 { 1692, 8, 1, 0, "PINSRBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1692 = PINSRBrm { 1693, 4, 1, 0, "PINSRBrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1693 = PINSRBrr { 1694, 8, 1, 0, "PINSRDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1694 = PINSRDrm { 1695, 4, 1, 0, "PINSRDrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1695 = PINSRDrr { 1696, 8, 1, 0, "PINSRQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1696 = PINSRQrm { 1697, 4, 1, 0, "PINSRQrr", 0, 0|5|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1697 = PINSRQrr { 1698, 8, 1, 0, "PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1698 = PINSRWrmi { 1699, 4, 1, 0, "PINSRWrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1699 = PINSRWrri { 1700, 7, 1, 0, "PMADDUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1700 = PMADDUBSWrm128 { 1701, 7, 1, 0, "PMADDUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1701 = PMADDUBSWrm64 { 1702, 3, 1, 0, "PMADDUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1702 = PMADDUBSWrr128 { 1703, 3, 1, 0, "PMADDUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1703 = PMADDUBSWrr64 { 1704, 7, 1, 0, "PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1704 = PMADDWDrm { 1705, 3, 1, 0, "PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1705 = PMADDWDrr { 1706, 7, 1, 0, "PMAXSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1706 = PMAXSBrm { 1707, 3, 1, 0, "PMAXSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1707 = PMAXSBrr { 1708, 7, 1, 0, "PMAXSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1708 = PMAXSDrm { 1709, 3, 1, 0, "PMAXSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1709 = PMAXSDrr { 1710, 7, 1, 0, "PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1710 = PMAXSWrm { 1711, 3, 1, 0, "PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1711 = PMAXSWrr { 1712, 7, 1, 0, "PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1712 = PMAXUBrm { 1713, 3, 1, 0, "PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1713 = PMAXUBrr { 1714, 7, 1, 0, "PMAXUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1714 = PMAXUDrm { 1715, 3, 1, 0, "PMAXUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1715 = PMAXUDrr { 1716, 7, 1, 0, "PMAXUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1716 = PMAXUWrm { 1717, 3, 1, 0, "PMAXUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1717 = PMAXUWrr { 1718, 7, 1, 0, "PMINSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1718 = PMINSBrm { 1719, 3, 1, 0, "PMINSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1719 = PMINSBrr { 1720, 7, 1, 0, "PMINSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1720 = PMINSDrm { 1721, 3, 1, 0, "PMINSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1721 = PMINSDrr { 1722, 7, 1, 0, "PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1722 = PMINSWrm { 1723, 3, 1, 0, "PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1723 = PMINSWrr { 1724, 7, 1, 0, "PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1724 = PMINUBrm { 1725, 3, 1, 0, "PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1725 = PMINUBrr { 1726, 7, 1, 0, "PMINUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1726 = PMINUDrm { 1727, 3, 1, 0, "PMINUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1727 = PMINUDrr { 1728, 7, 1, 0, "PMINUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1728 = PMINUWrm { 1729, 3, 1, 0, "PMINUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1729 = PMINUWrr { 1730, 2, 1, 0, "PMOVMSKBrr", 0, 0|5|(1<<6)|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1730 = PMOVMSKBrr { 1731, 6, 1, 0, "PMOVSXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1731 = PMOVSXBDrm { 1732, 2, 1, 0, "PMOVSXBDrr", 0, 0|5|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1732 = PMOVSXBDrr { 1733, 6, 1, 0, "PMOVSXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1733 = PMOVSXBQrm { 1734, 2, 1, 0, "PMOVSXBQrr", 0, 0|5|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1734 = PMOVSXBQrr { 1735, 6, 1, 0, "PMOVSXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1735 = PMOVSXBWrm { 1736, 2, 1, 0, "PMOVSXBWrr", 0, 0|5|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1736 = PMOVSXBWrr { 1737, 6, 1, 0, "PMOVSXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1737 = PMOVSXDQrm { 1738, 2, 1, 0, "PMOVSXDQrr", 0, 0|5|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1738 = PMOVSXDQrr { 1739, 6, 1, 0, "PMOVSXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1739 = PMOVSXWDrm { 1740, 2, 1, 0, "PMOVSXWDrr", 0, 0|5|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1740 = PMOVSXWDrr { 1741, 6, 1, 0, "PMOVSXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1741 = PMOVSXWQrm { 1742, 2, 1, 0, "PMOVSXWQrr", 0, 0|5|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1742 = PMOVSXWQrr { 1743, 6, 1, 0, "PMOVZXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1743 = PMOVZXBDrm { 1744, 2, 1, 0, "PMOVZXBDrr", 0, 0|5|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1744 = PMOVZXBDrr { 1745, 6, 1, 0, "PMOVZXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1745 = PMOVZXBQrm { 1746, 2, 1, 0, "PMOVZXBQrr", 0, 0|5|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1746 = PMOVZXBQrr { 1747, 6, 1, 0, "PMOVZXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1747 = PMOVZXBWrm { 1748, 2, 1, 0, "PMOVZXBWrr", 0, 0|5|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1748 = PMOVZXBWrr { 1749, 6, 1, 0, "PMOVZXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1749 = PMOVZXDQrm { 1750, 2, 1, 0, "PMOVZXDQrr", 0, 0|5|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1750 = PMOVZXDQrr { 1751, 6, 1, 0, "PMOVZXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1751 = PMOVZXWDrm { 1752, 2, 1, 0, "PMOVZXWDrr", 0, 0|5|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1752 = PMOVZXWDrr { 1753, 6, 1, 0, "PMOVZXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1753 = PMOVZXWQrm { 1754, 2, 1, 0, "PMOVZXWQrr", 0, 0|5|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1754 = PMOVZXWQrr { 1755, 7, 1, 0, "PMULDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1755 = PMULDQrm { 1756, 3, 1, 0, "PMULDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1756 = PMULDQrr { 1757, 7, 1, 0, "PMULHRSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1757 = PMULHRSWrm128 { 1758, 7, 1, 0, "PMULHRSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1758 = PMULHRSWrm64 { 1759, 3, 1, 0, "PMULHRSWrr128", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1759 = PMULHRSWrr128 { 1760, 3, 1, 0, "PMULHRSWrr64", 0|(1<<TID::Commutable), 0|5|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1760 = PMULHRSWrr64 { 1761, 7, 1, 0, "PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1761 = PMULHUWrm { 1762, 3, 1, 0, "PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1762 = PMULHUWrr { 1763, 7, 1, 0, "PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1763 = PMULHWrm { 1764, 3, 1, 0, "PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1764 = PMULHWrr { 1765, 7, 1, 0, "PMULLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1765 = PMULLDrm { 1766, 7, 1, 0, "PMULLDrm_int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1766 = PMULLDrm_int { 1767, 3, 1, 0, "PMULLDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1767 = PMULLDrr { 1768, 3, 1, 0, "PMULLDrr_int", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1768 = PMULLDrr_int { 1769, 7, 1, 0, "PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1769 = PMULLWrm { 1770, 3, 1, 0, "PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1770 = PMULLWrr { 1771, 7, 1, 0, "PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1771 = PMULUDQrm { 1772, 3, 1, 0, "PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1772 = PMULUDQrr { 1773, 1, 1, 0, "POP16r", 0|(1<<TID::MayLoad), 0|2|(1<<6)|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1773 = POP16r { 1774, 5, 1, 0, "POP16rmm", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1774 = POP16rmm { 1775, 1, 1, 0, "POP16rmr", 0|(1<<TID::MayLoad), 0|16|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1775 = POP16rmr { 1776, 1, 1, 0, "POP32r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1776 = POP32r { 1777, 5, 1, 0, "POP32rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1777 = POP32rmm { 1778, 1, 1, 0, "POP32rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1778 = POP32rmr { 1779, 1, 1, 0, "POP64r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1779 = POP64r { 1780, 5, 1, 0, "POP64rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1780 = POP64rmm { 1781, 1, 1, 0, "POP64rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1781 = POP64rmr { 1782, 6, 1, 0, "POPCNT16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1782 = POPCNT16rm { 1783, 2, 1, 0, "POPCNT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1783 = POPCNT16rr { 1784, 6, 1, 0, "POPCNT32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1784 = POPCNT32rm { 1785, 2, 1, 0, "POPCNT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1785 = POPCNT32rr { 1786, 6, 1, 0, "POPCNT64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1786 = POPCNT64rm { 1787, 2, 1, 0, "POPCNT64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1787 = POPCNT64rr { 1788, 0, 0, 0, "POPF", 0|(1<<TID::MayLoad), 0|1|(1<<6)|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1788 = POPF { 1789, 0, 0, 0, "POPFD", 0|(1<<TID::MayLoad), 0|1|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1789 = POPFD { 1790, 0, 0, 0, "POPFQ", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(157<<24), ImplicitList4, ImplicitList5, Barriers1, 0 }, // Inst #1790 = POPFQ { 1791, 0, 0, 0, "POPFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1791 = POPFS16 { 1792, 0, 0, 0, "POPFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1792 = POPFS32 { 1793, 0, 0, 0, "POPFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1793 = POPFS64 { 1794, 0, 0, 0, "POPGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1794 = POPGS16 { 1795, 0, 0, 0, "POPGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1795 = POPGS32 { 1796, 0, 0, 0, "POPGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1796 = POPGS64 { 1797, 7, 1, 0, "PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1797 = PORrm { 1798, 3, 1, 0, "PORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1798 = PORrr { 1799, 5, 0, 0, "PREFETCHNTA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1799 = PREFETCHNTA { 1800, 5, 0, 0, "PREFETCHT0", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1800 = PREFETCHT0 { 1801, 5, 0, 0, "PREFETCHT1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1801 = PREFETCHT1 { 1802, 5, 0, 0, "PREFETCHT2", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1802 = PREFETCHT2 { 1803, 7, 1, 0, "PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1803 = PSADBWrm { 1804, 3, 1, 0, "PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1804 = PSADBWrr { 1805, 7, 1, 0, "PSHUFBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo24 }, // Inst #1805 = PSHUFBrm128 { 1806, 7, 1, 0, "PSHUFBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo136 }, // Inst #1806 = PSHUFBrm64 { 1807, 3, 1, 0, "PSHUFBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo25 }, // Inst #1807 = PSHUFBrr128 { 1808, 3, 1, 0, "PSHUFBrr64", 0, 0|5|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo137 }, // Inst #1808 = PSHUFBrr64 { 1809, 7, 1, 0, "PSHUFDmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #1809 = PSHUFDmi { 1810, 3, 1, 0, "PSHUFDri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1810 = PSHUFDri { 1811, 7, 1, 0, "PSHUFHWmi", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #1811 = PSHUFHWmi { 1812, 3, 1, 0, "PSHUFHWri", 0, 0|5|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1812 = PSHUFHWri { 1813, 7, 1, 0, "PSHUFLWmi", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #1813 = PSHUFLWmi { 1814, 3, 1, 0, "PSHUFLWri", 0, 0|5|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1814 = PSHUFLWri { 1815, 7, 1, 0, "PSIGNBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1815 = PSIGNBrm128 { 1816, 7, 1, 0, "PSIGNBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1816 = PSIGNBrm64 { 1817, 3, 1, 0, "PSIGNBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1817 = PSIGNBrr128 { 1818, 3, 1, 0, "PSIGNBrr64", 0, 0|5|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1818 = PSIGNBrr64 { 1819, 7, 1, 0, "PSIGNDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1819 = PSIGNDrm128 { 1820, 7, 1, 0, "PSIGNDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1820 = PSIGNDrm64 { 1821, 3, 1, 0, "PSIGNDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1821 = PSIGNDrr128 { 1822, 3, 1, 0, "PSIGNDrr64", 0, 0|5|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1822 = PSIGNDrr64 { 1823, 7, 1, 0, "PSIGNWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1823 = PSIGNWrm128 { 1824, 7, 1, 0, "PSIGNWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1824 = PSIGNWrm64 { 1825, 3, 1, 0, "PSIGNWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1825 = PSIGNWrr128 { 1826, 3, 1, 0, "PSIGNWrr64", 0, 0|5|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1826 = PSIGNWrr64 { 1827, 3, 1, 0, "PSLLDQri", 0, 0|23|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1827 = PSLLDQri { 1828, 3, 1, 0, "PSLLDri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1828 = PSLLDri { 1829, 7, 1, 0, "PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1829 = PSLLDrm { 1830, 3, 1, 0, "PSLLDrr", 0, 0|5|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1830 = PSLLDrr { 1831, 3, 1, 0, "PSLLQri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1831 = PSLLQri { 1832, 7, 1, 0, "PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1832 = PSLLQrm { 1833, 3, 1, 0, "PSLLQrr", 0, 0|5|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1833 = PSLLQrr { 1834, 3, 1, 0, "PSLLWri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1834 = PSLLWri { 1835, 7, 1, 0, "PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1835 = PSLLWrm { 1836, 3, 1, 0, "PSLLWrr", 0, 0|5|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1836 = PSLLWrr { 1837, 3, 1, 0, "PSRADri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1837 = PSRADri { 1838, 7, 1, 0, "PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1838 = PSRADrm { 1839, 3, 1, 0, "PSRADrr", 0, 0|5|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1839 = PSRADrr { 1840, 3, 1, 0, "PSRAWri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1840 = PSRAWri { 1841, 7, 1, 0, "PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1841 = PSRAWrm { 1842, 3, 1, 0, "PSRAWrr", 0, 0|5|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1842 = PSRAWrr { 1843, 3, 1, 0, "PSRLDQri", 0, 0|19|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1843 = PSRLDQri { 1844, 3, 1, 0, "PSRLDri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1844 = PSRLDri { 1845, 7, 1, 0, "PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1845 = PSRLDrm { 1846, 3, 1, 0, "PSRLDrr", 0, 0|5|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1846 = PSRLDrr { 1847, 3, 1, 0, "PSRLQri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1847 = PSRLQri { 1848, 7, 1, 0, "PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1848 = PSRLQrm { 1849, 3, 1, 0, "PSRLQrr", 0, 0|5|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1849 = PSRLQrr { 1850, 3, 1, 0, "PSRLWri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1850 = PSRLWri { 1851, 7, 1, 0, "PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1851 = PSRLWrm { 1852, 3, 1, 0, "PSRLWrr", 0, 0|5|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1852 = PSRLWrr { 1853, 7, 1, 0, "PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1853 = PSUBBrm { 1854, 3, 1, 0, "PSUBBrr", 0, 0|5|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1854 = PSUBBrr { 1855, 7, 1, 0, "PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1855 = PSUBDrm { 1856, 3, 1, 0, "PSUBDrr", 0, 0|5|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1856 = PSUBDrr { 1857, 7, 1, 0, "PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1857 = PSUBQrm { 1858, 3, 1, 0, "PSUBQrr", 0, 0|5|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1858 = PSUBQrr { 1859, 7, 1, 0, "PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1859 = PSUBSBrm { 1860, 3, 1, 0, "PSUBSBrr", 0, 0|5|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1860 = PSUBSBrr { 1861, 7, 1, 0, "PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1861 = PSUBSWrm { 1862, 3, 1, 0, "PSUBSWrr", 0, 0|5|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1862 = PSUBSWrr { 1863, 7, 1, 0, "PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1863 = PSUBUSBrm { 1864, 3, 1, 0, "PSUBUSBrr", 0, 0|5|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1864 = PSUBUSBrr { 1865, 7, 1, 0, "PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1865 = PSUBUSWrm { 1866, 3, 1, 0, "PSUBUSWrr", 0, 0|5|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1866 = PSUBUSWrr { 1867, 7, 1, 0, "PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1867 = PSUBWrm { 1868, 3, 1, 0, "PSUBWrr", 0, 0|5|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1868 = PSUBWrr { 1869, 6, 0, 0, "PTESTrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #1869 = PTESTrm { 1870, 2, 0, 0, "PTESTrr", 0, 0|5|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #1870 = PTESTrr { 1871, 7, 1, 0, "PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1871 = PUNPCKHBWrm { 1872, 3, 1, 0, "PUNPCKHBWrr", 0, 0|5|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1872 = PUNPCKHBWrr { 1873, 7, 1, 0, "PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1873 = PUNPCKHDQrm { 1874, 3, 1, 0, "PUNPCKHDQrr", 0, 0|5|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1874 = PUNPCKHDQrr { 1875, 7, 1, 0, "PUNPCKHQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1875 = PUNPCKHQDQrm { 1876, 3, 1, 0, "PUNPCKHQDQrr", 0, 0|5|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1876 = PUNPCKHQDQrr { 1877, 7, 1, 0, "PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1877 = PUNPCKHWDrm { 1878, 3, 1, 0, "PUNPCKHWDrr", 0, 0|5|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1878 = PUNPCKHWDrr { 1879, 7, 1, 0, "PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1879 = PUNPCKLBWrm { 1880, 3, 1, 0, "PUNPCKLBWrr", 0, 0|5|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1880 = PUNPCKLBWrr { 1881, 7, 1, 0, "PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1881 = PUNPCKLDQrm { 1882, 3, 1, 0, "PUNPCKLDQrr", 0, 0|5|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1882 = PUNPCKLDQrr { 1883, 7, 1, 0, "PUNPCKLQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1883 = PUNPCKLQDQrm { 1884, 3, 1, 0, "PUNPCKLQDQrr", 0, 0|5|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1884 = PUNPCKLQDQrr { 1885, 7, 1, 0, "PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1885 = PUNPCKLWDrm { 1886, 3, 1, 0, "PUNPCKLWDrr", 0, 0|5|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1886 = PUNPCKLWDrr { 1887, 1, 0, 0, "PUSH16r", 0|(1<<TID::MayStore), 0|2|(1<<6)|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1887 = PUSH16r { 1888, 5, 0, 0, "PUSH16rmm", 0|(1<<TID::MayStore), 0|30|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1888 = PUSH16rmm { 1889, 1, 0, 0, "PUSH16rmr", 0|(1<<TID::MayStore), 0|22|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1889 = PUSH16rmr { 1890, 1, 0, 0, "PUSH32i16", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1890 = PUSH32i16 { 1891, 1, 0, 0, "PUSH32i32", 0|(1<<TID::MayStore), 0|1|(4<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1891 = PUSH32i32 { 1892, 1, 0, 0, "PUSH32i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1892 = PUSH32i8 { 1893, 1, 0, 0, "PUSH32r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1893 = PUSH32r { 1894, 5, 0, 0, "PUSH32rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1894 = PUSH32rmm { 1895, 1, 0, 0, "PUSH32rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1895 = PUSH32rmr { 1896, 1, 0, 0, "PUSH64i16", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1896 = PUSH64i16 { 1897, 1, 0, 0, "PUSH64i32", 0|(1<<TID::MayStore), 0|1|(4<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1897 = PUSH64i32 { 1898, 1, 0, 0, "PUSH64i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1898 = PUSH64i8 { 1899, 1, 0, 0, "PUSH64r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1899 = PUSH64r { 1900, 5, 0, 0, "PUSH64rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1900 = PUSH64rmm { 1901, 1, 0, 0, "PUSH64rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1901 = PUSH64rmr { 1902, 0, 0, 0, "PUSHF", 0|(1<<TID::MayStore), 0|1|(1<<6)|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1902 = PUSHF { 1903, 0, 0, 0, "PUSHFD", 0|(1<<TID::MayStore), 0|1|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1903 = PUSHFD { 1904, 0, 0, 0, "PUSHFQ64", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(156<<24), ImplicitList5, ImplicitList4, NULL, 0 }, // Inst #1904 = PUSHFQ64 { 1905, 0, 0, 0, "PUSHFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1905 = PUSHFS16 { 1906, 0, 0, 0, "PUSHFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1906 = PUSHFS32 { 1907, 0, 0, 0, "PUSHFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1907 = PUSHFS64 { 1908, 0, 0, 0, "PUSHGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1908 = PUSHGS16 { 1909, 0, 0, 0, "PUSHGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1909 = PUSHGS32 { 1910, 0, 0, 0, "PUSHGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1910 = PUSHGS64 { 1911, 7, 1, 0, "PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1911 = PXORrm { 1912, 3, 1, 0, "PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1912 = PXORrr { 1913, 5, 0, 0, "RCL16m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1913 = RCL16m1 { 1914, 5, 0, 0, "RCL16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1914 = RCL16mCL { 1915, 6, 0, 0, "RCL16mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1915 = RCL16mi { 1916, 2, 1, 0, "RCL16r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1916 = RCL16r1 { 1917, 2, 1, 0, "RCL16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1917 = RCL16rCL { 1918, 3, 1, 0, "RCL16ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1918 = RCL16ri { 1919, 5, 0, 0, "RCL32m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1919 = RCL32m1 { 1920, 5, 0, 0, "RCL32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1920 = RCL32mCL { 1921, 6, 0, 0, "RCL32mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1921 = RCL32mi { 1922, 2, 1, 0, "RCL32r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1922 = RCL32r1 { 1923, 2, 1, 0, "RCL32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1923 = RCL32rCL { 1924, 3, 1, 0, "RCL32ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1924 = RCL32ri { 1925, 5, 0, 0, "RCL64m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1925 = RCL64m1 { 1926, 5, 0, 0, "RCL64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1926 = RCL64mCL { 1927, 6, 0, 0, "RCL64mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1927 = RCL64mi { 1928, 2, 1, 0, "RCL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1928 = RCL64r1 { 1929, 2, 1, 0, "RCL64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1929 = RCL64rCL { 1930, 3, 1, 0, "RCL64ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1930 = RCL64ri { 1931, 5, 0, 0, "RCL8m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1931 = RCL8m1 { 1932, 5, 0, 0, "RCL8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1932 = RCL8mCL { 1933, 6, 0, 0, "RCL8mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1933 = RCL8mi { 1934, 2, 1, 0, "RCL8r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1934 = RCL8r1 { 1935, 2, 1, 0, "RCL8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1935 = RCL8rCL { 1936, 3, 1, 0, "RCL8ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1936 = RCL8ri { 1937, 6, 1, 0, "RCPPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1937 = RCPPSm { 1938, 6, 1, 0, "RCPPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1938 = RCPPSm_Int { 1939, 2, 1, 0, "RCPPSr", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1939 = RCPPSr { 1940, 2, 1, 0, "RCPPSr_Int", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1940 = RCPPSr_Int { 1941, 6, 1, 0, "RCPSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1941 = RCPSSm { 1942, 6, 1, 0, "RCPSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1942 = RCPSSm_Int { 1943, 2, 1, 0, "RCPSSr", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1943 = RCPSSr { 1944, 2, 1, 0, "RCPSSr_Int", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1944 = RCPSSr_Int { 1945, 5, 0, 0, "RCR16m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1945 = RCR16m1 { 1946, 5, 0, 0, "RCR16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1946 = RCR16mCL { 1947, 6, 0, 0, "RCR16mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1947 = RCR16mi { 1948, 2, 1, 0, "RCR16r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1948 = RCR16r1 { 1949, 2, 1, 0, "RCR16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1949 = RCR16rCL { 1950, 3, 1, 0, "RCR16ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1950 = RCR16ri { 1951, 5, 0, 0, "RCR32m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1951 = RCR32m1 { 1952, 5, 0, 0, "RCR32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1952 = RCR32mCL { 1953, 6, 0, 0, "RCR32mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1953 = RCR32mi { 1954, 2, 1, 0, "RCR32r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1954 = RCR32r1 { 1955, 2, 1, 0, "RCR32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1955 = RCR32rCL { 1956, 3, 1, 0, "RCR32ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1956 = RCR32ri { 1957, 5, 0, 0, "RCR64m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1957 = RCR64m1 { 1958, 5, 0, 0, "RCR64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1958 = RCR64mCL { 1959, 6, 0, 0, "RCR64mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1959 = RCR64mi { 1960, 2, 1, 0, "RCR64r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1960 = RCR64r1 { 1961, 2, 1, 0, "RCR64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1961 = RCR64rCL { 1962, 3, 1, 0, "RCR64ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1962 = RCR64ri { 1963, 5, 0, 0, "RCR8m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1963 = RCR8m1 { 1964, 5, 0, 0, "RCR8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1964 = RCR8mCL { 1965, 6, 0, 0, "RCR8mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1965 = RCR8mi { 1966, 2, 1, 0, "RCR8r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1966 = RCR8r1 { 1967, 2, 1, 0, "RCR8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1967 = RCR8rCL { 1968, 3, 1, 0, "RCR8ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1968 = RCR8ri { 1969, 0, 0, 0, "RDMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(50<<24), NULL, NULL, NULL, 0 }, // Inst #1969 = RDMSR { 1970, 0, 0, 0, "RDPMC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(51<<24), NULL, NULL, NULL, 0 }, // Inst #1970 = RDPMC { 1971, 0, 0, 0, "RDTSC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(49<<24), NULL, ImplicitList19, NULL, 0 }, // Inst #1971 = RDTSC { 1972, 0, 0, 0, "RDTSCP", 0|(1<<TID::UnmodeledSideEffects), 0|42|(1<<8)|(1<<24), NULL, ImplicitList45, NULL, 0 }, // Inst #1972 = RDTSCP { 1973, 0, 0, 0, "REPNE_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(242<<24), ImplicitList42, ImplicitList27, NULL, 0 }, // Inst #1973 = REPNE_PREFIX { 1974, 0, 0, 0, "REP_MOVSB", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(164<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1974 = REP_MOVSB { 1975, 0, 0, 0, "REP_MOVSD", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(165<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1975 = REP_MOVSD { 1976, 0, 0, 0, "REP_MOVSQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(165<<24), ImplicitList47, ImplicitList47, NULL, 0 }, // Inst #1976 = REP_MOVSQ { 1977, 0, 0, 0, "REP_MOVSW", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(165<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1977 = REP_MOVSW { 1978, 0, 0, 0, "REP_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(243<<24), ImplicitList42, ImplicitList27, NULL, 0 }, // Inst #1978 = REP_PREFIX { 1979, 0, 0, 0, "REP_STOSB", 0|(1<<TID::MayStore), 0|1|(2<<8)|(170<<24), ImplicitList48, ImplicitList49, NULL, 0 }, // Inst #1979 = REP_STOSB { 1980, 0, 0, 0, "REP_STOSD", 0|(1<<TID::MayStore), 0|1|(2<<8)|(171<<24), ImplicitList50, ImplicitList49, NULL, 0 }, // Inst #1980 = REP_STOSD { 1981, 0, 0, 0, "REP_STOSQ", 0|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(171<<24), ImplicitList51, ImplicitList52, NULL, 0 }, // Inst #1981 = REP_STOSQ { 1982, 0, 0, 0, "REP_STOSW", 0|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(171<<24), ImplicitList53, ImplicitList49, NULL, 0 }, // Inst #1982 = REP_STOSW { 1983, 0, 0, 0, "RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(7<<16)|(195<<24), NULL, NULL, NULL, 0 }, // Inst #1983 = RET { 1984, 1, 0, 0, "RETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(3<<13)|(7<<16)|(194<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1984 = RETI { 1985, 5, 0, 0, "ROL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1985 = ROL16m1 { 1986, 5, 0, 0, "ROL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1986 = ROL16mCL { 1987, 6, 0, 0, "ROL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1987 = ROL16mi { 1988, 2, 1, 0, "ROL16r1", 0, 0|16|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1988 = ROL16r1 { 1989, 2, 1, 0, "ROL16rCL", 0, 0|16|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1989 = ROL16rCL { 1990, 3, 1, 0, "ROL16ri", 0, 0|16|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1990 = ROL16ri { 1991, 5, 0, 0, "ROL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1991 = ROL32m1 { 1992, 5, 0, 0, "ROL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1992 = ROL32mCL { 1993, 6, 0, 0, "ROL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1993 = ROL32mi { 1994, 2, 1, 0, "ROL32r1", 0, 0|16|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1994 = ROL32r1 { 1995, 2, 1, 0, "ROL32rCL", 0, 0|16|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1995 = ROL32rCL { 1996, 3, 1, 0, "ROL32ri", 0, 0|16|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1996 = ROL32ri { 1997, 5, 0, 0, "ROL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1997 = ROL64m1 { 1998, 5, 0, 0, "ROL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1998 = ROL64mCL { 1999, 6, 0, 0, "ROL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1999 = ROL64mi { 2000, 2, 1, 0, "ROL64r1", 0, 0|16|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2000 = ROL64r1 { 2001, 2, 1, 0, "ROL64rCL", 0, 0|16|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2001 = ROL64rCL { 2002, 3, 1, 0, "ROL64ri", 0, 0|16|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2002 = ROL64ri { 2003, 5, 0, 0, "ROL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2003 = ROL8m1 { 2004, 5, 0, 0, "ROL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2004 = ROL8mCL { 2005, 6, 0, 0, "ROL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2005 = ROL8mi { 2006, 2, 1, 0, "ROL8r1", 0, 0|16|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2006 = ROL8r1 { 2007, 2, 1, 0, "ROL8rCL", 0, 0|16|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2007 = ROL8rCL { 2008, 3, 1, 0, "ROL8ri", 0, 0|16|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2008 = ROL8ri { 2009, 5, 0, 0, "ROR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2009 = ROR16m1 { 2010, 5, 0, 0, "ROR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2010 = ROR16mCL { 2011, 6, 0, 0, "ROR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2011 = ROR16mi { 2012, 2, 1, 0, "ROR16r1", 0, 0|17|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2012 = ROR16r1 { 2013, 2, 1, 0, "ROR16rCL", 0, 0|17|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2013 = ROR16rCL { 2014, 3, 1, 0, "ROR16ri", 0, 0|17|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2014 = ROR16ri { 2015, 5, 0, 0, "ROR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2015 = ROR32m1 { 2016, 5, 0, 0, "ROR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2016 = ROR32mCL { 2017, 6, 0, 0, "ROR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2017 = ROR32mi { 2018, 2, 1, 0, "ROR32r1", 0, 0|17|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2018 = ROR32r1 { 2019, 2, 1, 0, "ROR32rCL", 0, 0|17|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2019 = ROR32rCL { 2020, 3, 1, 0, "ROR32ri", 0, 0|17|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2020 = ROR32ri { 2021, 5, 0, 0, "ROR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2021 = ROR64m1 { 2022, 5, 0, 0, "ROR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2022 = ROR64mCL { 2023, 6, 0, 0, "ROR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2023 = ROR64mi { 2024, 2, 1, 0, "ROR64r1", 0, 0|17|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2024 = ROR64r1 { 2025, 2, 1, 0, "ROR64rCL", 0, 0|17|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2025 = ROR64rCL { 2026, 3, 1, 0, "ROR64ri", 0, 0|17|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2026 = ROR64ri { 2027, 5, 0, 0, "ROR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2027 = ROR8m1 { 2028, 5, 0, 0, "ROR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2028 = ROR8mCL { 2029, 6, 0, 0, "ROR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2029 = ROR8mi { 2030, 2, 1, 0, "ROR8r1", 0, 0|17|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2030 = ROR8r1 { 2031, 2, 1, 0, "ROR8rCL", 0, 0|17|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2031 = ROR8rCL { 2032, 3, 1, 0, "ROR8ri", 0, 0|17|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2032 = ROR8ri { 2033, 7, 1, 0, "ROUNDPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #2033 = ROUNDPDm_Int { 2034, 3, 1, 0, "ROUNDPDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #2034 = ROUNDPDr_Int { 2035, 7, 1, 0, "ROUNDPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #2035 = ROUNDPSm_Int { 2036, 3, 1, 0, "ROUNDPSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #2036 = ROUNDPSr_Int { 2037, 8, 1, 0, "ROUNDSDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2037 = ROUNDSDm_Int { 2038, 4, 1, 0, "ROUNDSDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2038 = ROUNDSDr_Int { 2039, 8, 1, 0, "ROUNDSSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2039 = ROUNDSSm_Int { 2040, 4, 1, 0, "ROUNDSSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2040 = ROUNDSSr_Int { 2041, 0, 0, 0, "RSM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(170<<24), NULL, NULL, NULL, 0 }, // Inst #2041 = RSM { 2042, 6, 1, 0, "RSQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2042 = RSQRTPSm { 2043, 6, 1, 0, "RSQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2043 = RSQRTPSm_Int { 2044, 2, 1, 0, "RSQRTPSr", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2044 = RSQRTPSr { 2045, 2, 1, 0, "RSQRTPSr_Int", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2045 = RSQRTPSr_Int { 2046, 6, 1, 0, "RSQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2046 = RSQRTSSm { 2047, 6, 1, 0, "RSQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2047 = RSQRTSSm_Int { 2048, 2, 1, 0, "RSQRTSSr", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2048 = RSQRTSSr { 2049, 2, 1, 0, "RSQRTSSr_Int", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2049 = RSQRTSSr_Int { 2050, 0, 0, 0, "SAHF", 0, 0|1|(158<<24), ImplicitList28, ImplicitList1, Barriers1, 0 }, // Inst #2050 = SAHF { 2051, 5, 0, 0, "SAR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2051 = SAR16m1 { 2052, 5, 0, 0, "SAR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2052 = SAR16mCL { 2053, 6, 0, 0, "SAR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2053 = SAR16mi { 2054, 2, 1, 0, "SAR16r1", 0, 0|23|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2054 = SAR16r1 { 2055, 2, 1, 0, "SAR16rCL", 0, 0|23|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2055 = SAR16rCL { 2056, 3, 1, 0, "SAR16ri", 0, 0|23|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2056 = SAR16ri { 2057, 5, 0, 0, "SAR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2057 = SAR32m1 { 2058, 5, 0, 0, "SAR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2058 = SAR32mCL { 2059, 6, 0, 0, "SAR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2059 = SAR32mi { 2060, 2, 1, 0, "SAR32r1", 0, 0|23|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2060 = SAR32r1 { 2061, 2, 1, 0, "SAR32rCL", 0, 0|23|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2061 = SAR32rCL { 2062, 3, 1, 0, "SAR32ri", 0, 0|23|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2062 = SAR32ri { 2063, 5, 0, 0, "SAR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2063 = SAR64m1 { 2064, 5, 0, 0, "SAR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2064 = SAR64mCL { 2065, 6, 0, 0, "SAR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2065 = SAR64mi { 2066, 2, 1, 0, "SAR64r1", 0, 0|23|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2066 = SAR64r1 { 2067, 2, 1, 0, "SAR64rCL", 0, 0|23|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2067 = SAR64rCL { 2068, 3, 1, 0, "SAR64ri", 0, 0|23|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2068 = SAR64ri { 2069, 5, 0, 0, "SAR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2069 = SAR8m1 { 2070, 5, 0, 0, "SAR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2070 = SAR8mCL { 2071, 6, 0, 0, "SAR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2071 = SAR8mi { 2072, 2, 1, 0, "SAR8r1", 0, 0|23|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2072 = SAR8r1 { 2073, 2, 1, 0, "SAR8rCL", 0, 0|23|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2073 = SAR8rCL { 2074, 3, 1, 0, "SAR8ri", 0, 0|23|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2074 = SAR8ri { 2075, 1, 0, 0, "SBB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2075 = SBB16i16 { 2076, 6, 0, 0, "SBB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2076 = SBB16mi { 2077, 6, 0, 0, "SBB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2077 = SBB16mi8 { 2078, 6, 0, 0, "SBB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2078 = SBB16mr { 2079, 3, 1, 0, "SBB16ri", 0, 0|19|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2079 = SBB16ri { 2080, 3, 1, 0, "SBB16ri8", 0, 0|19|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2080 = SBB16ri8 { 2081, 7, 1, 0, "SBB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2081 = SBB16rm { 2082, 3, 1, 0, "SBB16rr", 0, 0|3|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2082 = SBB16rr { 2083, 3, 1, 0, "SBB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2083 = SBB16rr_REV { 2084, 1, 0, 0, "SBB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2084 = SBB32i32 { 2085, 6, 0, 0, "SBB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2085 = SBB32mi { 2086, 6, 0, 0, "SBB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2086 = SBB32mi8 { 2087, 6, 0, 0, "SBB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2087 = SBB32mr { 2088, 3, 1, 0, "SBB32ri", 0, 0|19|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2088 = SBB32ri { 2089, 3, 1, 0, "SBB32ri8", 0, 0|19|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2089 = SBB32ri8 { 2090, 7, 1, 0, "SBB32rm", 0|(1<<TID::MayLoad), 0|6|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2090 = SBB32rm { 2091, 3, 1, 0, "SBB32rr", 0, 0|3|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2091 = SBB32rr { 2092, 3, 1, 0, "SBB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2092 = SBB32rr_REV { 2093, 1, 0, 0, "SBB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2093 = SBB64i32 { 2094, 6, 0, 0, "SBB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2094 = SBB64mi32 { 2095, 6, 0, 0, "SBB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2095 = SBB64mi8 { 2096, 6, 0, 0, "SBB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2096 = SBB64mr { 2097, 3, 1, 0, "SBB64ri32", 0, 0|19|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2097 = SBB64ri32 { 2098, 3, 1, 0, "SBB64ri8", 0, 0|19|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2098 = SBB64ri8 { 2099, 7, 1, 0, "SBB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2099 = SBB64rm { 2100, 3, 1, 0, "SBB64rr", 0, 0|3|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2100 = SBB64rr { 2101, 3, 1, 0, "SBB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2101 = SBB64rr_REV { 2102, 1, 0, 0, "SBB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(28<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2102 = SBB8i8 { 2103, 6, 0, 0, "SBB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2103 = SBB8mi { 2104, 6, 0, 0, "SBB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2104 = SBB8mr { 2105, 3, 1, 0, "SBB8ri", 0, 0|19|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2105 = SBB8ri { 2106, 7, 1, 0, "SBB8rm", 0|(1<<TID::MayLoad), 0|6|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2106 = SBB8rm { 2107, 3, 1, 0, "SBB8rr", 0, 0|3|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2107 = SBB8rr { 2108, 3, 1, 0, "SBB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2108 = SBB8rr_REV { 2109, 0, 0, 0, "SCAS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2109 = SCAS16 { 2110, 0, 0, 0, "SCAS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2110 = SCAS32 { 2111, 0, 0, 0, "SCAS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2111 = SCAS64 { 2112, 0, 0, 0, "SCAS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2112 = SCAS8 { 2113, 5, 0, 0, "SETAEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2113 = SETAEm { 2114, 1, 1, 0, "SETAEr", 0, 0|16|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2114 = SETAEr { 2115, 5, 0, 0, "SETAm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2115 = SETAm { 2116, 1, 1, 0, "SETAr", 0, 0|16|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2116 = SETAr { 2117, 5, 0, 0, "SETBEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2117 = SETBEm { 2118, 1, 1, 0, "SETBEr", 0, 0|16|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2118 = SETBEr { 2119, 1, 1, 0, "SETB_C16r", 0, 0|32|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #2119 = SETB_C16r { 2120, 1, 1, 0, "SETB_C32r", 0, 0|32|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #2120 = SETB_C32r { 2121, 1, 1, 0, "SETB_C64r", 0, 0|32|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #2121 = SETB_C64r { 2122, 1, 1, 0, "SETB_C8r", 0, 0|32|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #2122 = SETB_C8r { 2123, 5, 0, 0, "SETBm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2123 = SETBm { 2124, 1, 1, 0, "SETBr", 0, 0|16|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2124 = SETBr { 2125, 5, 0, 0, "SETEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2125 = SETEm { 2126, 1, 1, 0, "SETEr", 0, 0|16|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2126 = SETEr { 2127, 5, 0, 0, "SETGEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2127 = SETGEm { 2128, 1, 1, 0, "SETGEr", 0, 0|16|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2128 = SETGEr { 2129, 5, 0, 0, "SETGm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2129 = SETGm { 2130, 1, 1, 0, "SETGr", 0, 0|16|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2130 = SETGr { 2131, 5, 0, 0, "SETLEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2131 = SETLEm { 2132, 1, 1, 0, "SETLEr", 0, 0|16|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2132 = SETLEr { 2133, 5, 0, 0, "SETLm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2133 = SETLm { 2134, 1, 1, 0, "SETLr", 0, 0|16|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2134 = SETLr { 2135, 5, 0, 0, "SETNEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2135 = SETNEm { 2136, 1, 1, 0, "SETNEr", 0, 0|16|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2136 = SETNEr { 2137, 5, 0, 0, "SETNOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2137 = SETNOm { 2138, 1, 1, 0, "SETNOr", 0, 0|16|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2138 = SETNOr { 2139, 5, 0, 0, "SETNPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2139 = SETNPm { 2140, 1, 1, 0, "SETNPr", 0, 0|16|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2140 = SETNPr { 2141, 5, 0, 0, "SETNSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2141 = SETNSm { 2142, 1, 1, 0, "SETNSr", 0, 0|16|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2142 = SETNSr { 2143, 5, 0, 0, "SETOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2143 = SETOm { 2144, 1, 1, 0, "SETOr", 0, 0|16|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2144 = SETOr { 2145, 5, 0, 0, "SETPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2145 = SETPm { 2146, 1, 1, 0, "SETPr", 0, 0|16|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2146 = SETPr { 2147, 5, 0, 0, "SETSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2147 = SETSm { 2148, 1, 1, 0, "SETSr", 0, 0|16|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2148 = SETSr { 2149, 0, 0, 0, "SFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2149 = SFENCE { 2150, 5, 1, 0, "SGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2150 = SGDTm { 2151, 5, 0, 0, "SHL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2151 = SHL16m1 { 2152, 5, 0, 0, "SHL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2152 = SHL16mCL { 2153, 6, 0, 0, "SHL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2153 = SHL16mi { 2154, 2, 1, 0, "SHL16r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2154 = SHL16r1 { 2155, 2, 1, 0, "SHL16rCL", 0, 0|20|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2155 = SHL16rCL { 2156, 3, 1, 0, "SHL16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2156 = SHL16ri { 2157, 5, 0, 0, "SHL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2157 = SHL32m1 { 2158, 5, 0, 0, "SHL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2158 = SHL32mCL { 2159, 6, 0, 0, "SHL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2159 = SHL32mi { 2160, 2, 1, 0, "SHL32r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2160 = SHL32r1 { 2161, 2, 1, 0, "SHL32rCL", 0, 0|20|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2161 = SHL32rCL { 2162, 3, 1, 0, "SHL32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2162 = SHL32ri { 2163, 5, 0, 0, "SHL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2163 = SHL64m1 { 2164, 5, 0, 0, "SHL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2164 = SHL64mCL { 2165, 6, 0, 0, "SHL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2165 = SHL64mi { 2166, 2, 1, 0, "SHL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2166 = SHL64r1 { 2167, 2, 1, 0, "SHL64rCL", 0, 0|20|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2167 = SHL64rCL { 2168, 3, 1, 0, "SHL64ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2168 = SHL64ri { 2169, 5, 0, 0, "SHL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2169 = SHL8m1 { 2170, 5, 0, 0, "SHL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2170 = SHL8mCL { 2171, 6, 0, 0, "SHL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2171 = SHL8mi { 2172, 2, 1, 0, "SHL8r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2172 = SHL8r1 { 2173, 2, 1, 0, "SHL8rCL", 0, 0|20|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2173 = SHL8rCL { 2174, 3, 1, 0, "SHL8ri", 0, 0|20|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2174 = SHL8ri { 2175, 6, 0, 0, "SHLD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2175 = SHLD16mrCL { 2176, 7, 0, 0, "SHLD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo190 }, // Inst #2176 = SHLD16mri8 { 2177, 3, 1, 0, "SHLD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2177 = SHLD16rrCL { 2178, 4, 1, 0, "SHLD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo191 }, // Inst #2178 = SHLD16rri8 { 2179, 6, 0, 0, "SHLD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2179 = SHLD32mrCL { 2180, 7, 0, 0, "SHLD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo192 }, // Inst #2180 = SHLD32mri8 { 2181, 3, 1, 0, "SHLD32rrCL", 0, 0|3|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2181 = SHLD32rrCL { 2182, 4, 1, 0, "SHLD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo193 }, // Inst #2182 = SHLD32rri8 { 2183, 6, 0, 0, "SHLD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2183 = SHLD64mrCL { 2184, 7, 0, 0, "SHLD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #2184 = SHLD64mri8 { 2185, 3, 1, 0, "SHLD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2185 = SHLD64rrCL { 2186, 4, 1, 0, "SHLD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #2186 = SHLD64rri8 { 2187, 5, 0, 0, "SHR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2187 = SHR16m1 { 2188, 5, 0, 0, "SHR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2188 = SHR16mCL { 2189, 6, 0, 0, "SHR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2189 = SHR16mi { 2190, 2, 1, 0, "SHR16r1", 0, 0|21|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2190 = SHR16r1 { 2191, 2, 1, 0, "SHR16rCL", 0, 0|21|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2191 = SHR16rCL { 2192, 3, 1, 0, "SHR16ri", 0, 0|21|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2192 = SHR16ri { 2193, 5, 0, 0, "SHR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2193 = SHR32m1 { 2194, 5, 0, 0, "SHR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2194 = SHR32mCL { 2195, 6, 0, 0, "SHR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2195 = SHR32mi { 2196, 2, 1, 0, "SHR32r1", 0, 0|21|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2196 = SHR32r1 { 2197, 2, 1, 0, "SHR32rCL", 0, 0|21|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2197 = SHR32rCL { 2198, 3, 1, 0, "SHR32ri", 0, 0|21|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2198 = SHR32ri { 2199, 5, 0, 0, "SHR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2199 = SHR64m1 { 2200, 5, 0, 0, "SHR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2200 = SHR64mCL { 2201, 6, 0, 0, "SHR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2201 = SHR64mi { 2202, 2, 1, 0, "SHR64r1", 0, 0|21|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2202 = SHR64r1 { 2203, 2, 1, 0, "SHR64rCL", 0, 0|21|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2203 = SHR64rCL { 2204, 3, 1, 0, "SHR64ri", 0, 0|21|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2204 = SHR64ri { 2205, 5, 0, 0, "SHR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2205 = SHR8m1 { 2206, 5, 0, 0, "SHR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2206 = SHR8mCL { 2207, 6, 0, 0, "SHR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2207 = SHR8mi { 2208, 2, 1, 0, "SHR8r1", 0, 0|21|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2208 = SHR8r1 { 2209, 2, 1, 0, "SHR8rCL", 0, 0|21|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2209 = SHR8rCL { 2210, 3, 1, 0, "SHR8ri", 0, 0|21|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2210 = SHR8ri { 2211, 6, 0, 0, "SHRD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2211 = SHRD16mrCL { 2212, 7, 0, 0, "SHRD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo190 }, // Inst #2212 = SHRD16mri8 { 2213, 3, 1, 0, "SHRD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2213 = SHRD16rrCL { 2214, 4, 1, 0, "SHRD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo191 }, // Inst #2214 = SHRD16rri8 { 2215, 6, 0, 0, "SHRD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2215 = SHRD32mrCL { 2216, 7, 0, 0, "SHRD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo192 }, // Inst #2216 = SHRD32mri8 { 2217, 3, 1, 0, "SHRD32rrCL", 0, 0|3|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2217 = SHRD32rrCL { 2218, 4, 1, 0, "SHRD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo193 }, // Inst #2218 = SHRD32rri8 { 2219, 6, 0, 0, "SHRD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2219 = SHRD64mrCL { 2220, 7, 0, 0, "SHRD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #2220 = SHRD64mri8 { 2221, 3, 1, 0, "SHRD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2221 = SHRD64rrCL { 2222, 4, 1, 0, "SHRD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #2222 = SHRD64rri8 { 2223, 8, 1, 0, "SHUFPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2223 = SHUFPDrmi { 2224, 4, 1, 0, "SHUFPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2224 = SHUFPDrri { 2225, 8, 1, 0, "SHUFPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2225 = SHUFPSrmi { 2226, 4, 1, 0, "SHUFPSrri", 0|(1<<TID::ConvertibleTo3Addr), 0|5|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2226 = SHUFPSrri { 2227, 5, 1, 0, "SIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2227 = SIDTm { 2228, 0, 0, 0, "SIN_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(254<<24), NULL, NULL, NULL, 0 }, // Inst #2228 = SIN_F { 2229, 2, 1, 0, "SIN_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2229 = SIN_Fp32 { 2230, 2, 1, 0, "SIN_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2230 = SIN_Fp64 { 2231, 2, 1, 0, "SIN_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2231 = SIN_Fp80 { 2232, 5, 1, 0, "SLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2232 = SLDT16m { 2233, 1, 1, 0, "SLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2233 = SLDT16r { 2234, 5, 1, 0, "SLDT64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo30 }, // Inst #2234 = SLDT64m { 2235, 1, 1, 0, "SLDT64r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo58 }, // Inst #2235 = SLDT64r { 2236, 5, 1, 0, "SMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2236 = SMSW16m { 2237, 1, 1, 0, "SMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2237 = SMSW16r { 2238, 1, 1, 0, "SMSW32r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2238 = SMSW32r { 2239, 1, 1, 0, "SMSW64r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<12)|(1<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2239 = SMSW64r { 2240, 6, 1, 0, "SQRTPDm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2240 = SQRTPDm { 2241, 6, 1, 0, "SQRTPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2241 = SQRTPDm_Int { 2242, 2, 1, 0, "SQRTPDr", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2242 = SQRTPDr { 2243, 2, 1, 0, "SQRTPDr_Int", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2243 = SQRTPDr_Int { 2244, 6, 1, 0, "SQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2244 = SQRTPSm { 2245, 6, 1, 0, "SQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2245 = SQRTPSm_Int { 2246, 2, 1, 0, "SQRTPSr", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2246 = SQRTPSr { 2247, 2, 1, 0, "SQRTPSr_Int", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2247 = SQRTPSr_Int { 2248, 6, 1, 0, "SQRTSDm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #2248 = SQRTSDm { 2249, 6, 1, 0, "SQRTSDm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2249 = SQRTSDm_Int { 2250, 2, 1, 0, "SQRTSDr", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #2250 = SQRTSDr { 2251, 2, 1, 0, "SQRTSDr_Int", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2251 = SQRTSDr_Int { 2252, 6, 1, 0, "SQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2252 = SQRTSSm { 2253, 6, 1, 0, "SQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2253 = SQRTSSm_Int { 2254, 2, 1, 0, "SQRTSSr", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2254 = SQRTSSr { 2255, 2, 1, 0, "SQRTSSr_Int", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2255 = SQRTSSr_Int { 2256, 0, 0, 0, "SQRT_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(250<<24), NULL, NULL, NULL, 0 }, // Inst #2256 = SQRT_F { 2257, 2, 1, 0, "SQRT_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2257 = SQRT_Fp32 { 2258, 2, 1, 0, "SQRT_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2258 = SQRT_Fp64 { 2259, 2, 1, 0, "SQRT_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2259 = SQRT_Fp80 { 2260, 0, 0, 0, "SS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(54<<24), NULL, NULL, NULL, 0 }, // Inst #2260 = SS_PREFIX { 2261, 0, 0, 0, "STC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(249<<24), NULL, NULL, NULL, 0 }, // Inst #2261 = STC { 2262, 0, 0, 0, "STD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(253<<24), NULL, NULL, NULL, 0 }, // Inst #2262 = STD { 2263, 0, 0, 0, "STI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(251<<24), NULL, NULL, NULL, 0 }, // Inst #2263 = STI { 2264, 5, 0, 0, "STMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2264 = STMXCSR { 2265, 0, 0, 0, "STOSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(170<<24), ImplicitList54, ImplicitList35, NULL, 0 }, // Inst #2265 = STOSB { 2266, 0, 0, 0, "STOSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(171<<24), ImplicitList55, ImplicitList35, NULL, 0 }, // Inst #2266 = STOSD { 2267, 0, 0, 0, "STOSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(171<<24), ImplicitList56, ImplicitList35, NULL, 0 }, // Inst #2267 = STOSW { 2268, 5, 1, 0, "STRm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2268 = STRm { 2269, 1, 1, 0, "STRr", 0|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2269 = STRr { 2270, 5, 0, 0, "ST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2270 = ST_F32m { 2271, 5, 0, 0, "ST_F64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2271 = ST_F64m { 2272, 5, 0, 0, "ST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2272 = ST_FP32m { 2273, 5, 0, 0, "ST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2273 = ST_FP64m { 2274, 5, 0, 0, "ST_FP80m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2274 = ST_FP80m { 2275, 1, 0, 0, "ST_FPrr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2275 = ST_FPrr { 2276, 6, 0, 0, "ST_Fp32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2276 = ST_Fp32m { 2277, 6, 0, 0, "ST_Fp64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2277 = ST_Fp64m { 2278, 6, 0, 0, "ST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2278 = ST_Fp64m32 { 2279, 6, 0, 0, "ST_Fp80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2279 = ST_Fp80m32 { 2280, 6, 0, 0, "ST_Fp80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2280 = ST_Fp80m64 { 2281, 6, 0, 0, "ST_FpP32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2281 = ST_FpP32m { 2282, 6, 0, 0, "ST_FpP64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2282 = ST_FpP64m { 2283, 6, 0, 0, "ST_FpP64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2283 = ST_FpP64m32 { 2284, 6, 0, 0, "ST_FpP80m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2284 = ST_FpP80m { 2285, 6, 0, 0, "ST_FpP80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2285 = ST_FpP80m32 { 2286, 6, 0, 0, "ST_FpP80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2286 = ST_FpP80m64 { 2287, 1, 0, 0, "ST_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2287 = ST_Frr { 2288, 1, 0, 0, "SUB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2288 = SUB16i16 { 2289, 6, 0, 0, "SUB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2289 = SUB16mi { 2290, 6, 0, 0, "SUB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2290 = SUB16mi8 { 2291, 6, 0, 0, "SUB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2291 = SUB16mr { 2292, 3, 1, 0, "SUB16ri", 0, 0|21|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2292 = SUB16ri { 2293, 3, 1, 0, "SUB16ri8", 0, 0|21|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2293 = SUB16ri8 { 2294, 7, 1, 0, "SUB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2294 = SUB16rm { 2295, 3, 1, 0, "SUB16rr", 0, 0|3|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2295 = SUB16rr { 2296, 3, 1, 0, "SUB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2296 = SUB16rr_REV { 2297, 1, 0, 0, "SUB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2297 = SUB32i32 { 2298, 6, 0, 0, "SUB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2298 = SUB32mi { 2299, 6, 0, 0, "SUB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2299 = SUB32mi8 { 2300, 6, 0, 0, "SUB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2300 = SUB32mr { 2301, 3, 1, 0, "SUB32ri", 0, 0|21|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2301 = SUB32ri { 2302, 3, 1, 0, "SUB32ri8", 0, 0|21|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2302 = SUB32ri8 { 2303, 7, 1, 0, "SUB32rm", 0|(1<<TID::MayLoad), 0|6|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2303 = SUB32rm { 2304, 3, 1, 0, "SUB32rr", 0, 0|3|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2304 = SUB32rr { 2305, 3, 1, 0, "SUB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2305 = SUB32rr_REV { 2306, 1, 0, 0, "SUB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2306 = SUB64i32 { 2307, 6, 0, 0, "SUB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2307 = SUB64mi32 { 2308, 6, 0, 0, "SUB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2308 = SUB64mi8 { 2309, 6, 0, 0, "SUB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2309 = SUB64mr { 2310, 3, 1, 0, "SUB64ri32", 0, 0|21|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2310 = SUB64ri32 { 2311, 3, 1, 0, "SUB64ri8", 0, 0|21|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2311 = SUB64ri8 { 2312, 7, 1, 0, "SUB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2312 = SUB64rm { 2313, 3, 1, 0, "SUB64rr", 0, 0|3|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2313 = SUB64rr { 2314, 3, 1, 0, "SUB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2314 = SUB64rr_REV { 2315, 1, 0, 0, "SUB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(44<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2315 = SUB8i8 { 2316, 6, 0, 0, "SUB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2316 = SUB8mi { 2317, 6, 0, 0, "SUB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2317 = SUB8mr { 2318, 3, 1, 0, "SUB8ri", 0, 0|21|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2318 = SUB8ri { 2319, 7, 1, 0, "SUB8rm", 0|(1<<TID::MayLoad), 0|6|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2319 = SUB8rm { 2320, 3, 1, 0, "SUB8rr", 0, 0|3|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2320 = SUB8rr { 2321, 3, 1, 0, "SUB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2321 = SUB8rr_REV { 2322, 7, 1, 0, "SUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2322 = SUBPDrm { 2323, 3, 1, 0, "SUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2323 = SUBPDrr { 2324, 7, 1, 0, "SUBPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2324 = SUBPSrm { 2325, 3, 1, 0, "SUBPSrr", 0, 0|5|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2325 = SUBPSrr { 2326, 5, 0, 0, "SUBR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2326 = SUBR_F32m { 2327, 5, 0, 0, "SUBR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2327 = SUBR_F64m { 2328, 5, 0, 0, "SUBR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2328 = SUBR_FI16m { 2329, 5, 0, 0, "SUBR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2329 = SUBR_FI32m { 2330, 1, 0, 0, "SUBR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2330 = SUBR_FPrST0 { 2331, 1, 0, 0, "SUBR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2331 = SUBR_FST0r { 2332, 7, 1, 0, "SUBR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2332 = SUBR_Fp32m { 2333, 7, 1, 0, "SUBR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2333 = SUBR_Fp64m { 2334, 7, 1, 0, "SUBR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2334 = SUBR_Fp64m32 { 2335, 7, 1, 0, "SUBR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2335 = SUBR_Fp80m32 { 2336, 7, 1, 0, "SUBR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2336 = SUBR_Fp80m64 { 2337, 7, 1, 0, "SUBR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2337 = SUBR_FpI16m32 { 2338, 7, 1, 0, "SUBR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2338 = SUBR_FpI16m64 { 2339, 7, 1, 0, "SUBR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2339 = SUBR_FpI16m80 { 2340, 7, 1, 0, "SUBR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2340 = SUBR_FpI32m32 { 2341, 7, 1, 0, "SUBR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2341 = SUBR_FpI32m64 { 2342, 7, 1, 0, "SUBR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2342 = SUBR_FpI32m80 { 2343, 1, 0, 0, "SUBR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2343 = SUBR_FrST0 { 2344, 7, 1, 0, "SUBSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #2344 = SUBSDrm { 2345, 7, 1, 0, "SUBSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2345 = SUBSDrm_Int { 2346, 3, 1, 0, "SUBSDrr", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #2346 = SUBSDrr { 2347, 3, 1, 0, "SUBSDrr_Int", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2347 = SUBSDrr_Int { 2348, 7, 1, 0, "SUBSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #2348 = SUBSSrm { 2349, 7, 1, 0, "SUBSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2349 = SUBSSrm_Int { 2350, 3, 1, 0, "SUBSSrr", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2350 = SUBSSrr { 2351, 3, 1, 0, "SUBSSrr_Int", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2351 = SUBSSrr_Int { 2352, 5, 0, 0, "SUB_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2352 = SUB_F32m { 2353, 5, 0, 0, "SUB_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2353 = SUB_F64m { 2354, 5, 0, 0, "SUB_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2354 = SUB_FI16m { 2355, 5, 0, 0, "SUB_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2355 = SUB_FI32m { 2356, 1, 0, 0, "SUB_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2356 = SUB_FPrST0 { 2357, 1, 0, 0, "SUB_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2357 = SUB_FST0r { 2358, 3, 1, 0, "SUB_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2358 = SUB_Fp32 { 2359, 7, 1, 0, "SUB_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2359 = SUB_Fp32m { 2360, 3, 1, 0, "SUB_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2360 = SUB_Fp64 { 2361, 7, 1, 0, "SUB_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2361 = SUB_Fp64m { 2362, 7, 1, 0, "SUB_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2362 = SUB_Fp64m32 { 2363, 3, 1, 0, "SUB_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2363 = SUB_Fp80 { 2364, 7, 1, 0, "SUB_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2364 = SUB_Fp80m32 { 2365, 7, 1, 0, "SUB_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2365 = SUB_Fp80m64 { 2366, 7, 1, 0, "SUB_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2366 = SUB_FpI16m32 { 2367, 7, 1, 0, "SUB_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2367 = SUB_FpI16m64 { 2368, 7, 1, 0, "SUB_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2368 = SUB_FpI16m80 { 2369, 7, 1, 0, "SUB_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2369 = SUB_FpI32m32 { 2370, 7, 1, 0, "SUB_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2370 = SUB_FpI32m64 { 2371, 7, 1, 0, "SUB_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2371 = SUB_FpI32m80 { 2372, 1, 0, 0, "SUB_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2372 = SUB_FrST0 { 2373, 0, 0, 0, "SWAPGS", 0|(1<<TID::UnmodeledSideEffects), 0|41|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2373 = SWAPGS { 2374, 0, 0, 0, "SYSCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(5<<24), NULL, NULL, NULL, 0 }, // Inst #2374 = SYSCALL { 2375, 0, 0, 0, "SYSENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(52<<24), NULL, NULL, NULL, 0 }, // Inst #2375 = SYSENTER { 2376, 0, 0, 0, "SYSEXIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2376 = SYSEXIT { 2377, 0, 0, 0, "SYSEXIT64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<12)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2377 = SYSEXIT64 { 2378, 0, 0, 0, "SYSRET", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(7<<24), NULL, NULL, NULL, 0 }, // Inst #2378 = SYSRET { 2379, 1, 0, 0, "TAILJMPd", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #2379 = TAILJMPd { 2380, 5, 0, 0, "TAILJMPm", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2380 = TAILJMPm { 2381, 1, 0, 0, "TAILJMPr", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2381 = TAILJMPr { 2382, 1, 0, 0, "TAILJMPr64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2382 = TAILJMPr64 { 2383, 2, 0, 0, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2383 = TCRETURNdi { 2384, 2, 0, 0, "TCRETURNdi64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2384 = TCRETURNdi64 { 2385, 2, 0, 0, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo55 }, // Inst #2385 = TCRETURNri { 2386, 2, 0, 0, "TCRETURNri64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo56 }, // Inst #2386 = TCRETURNri64 { 2387, 1, 0, 0, "TEST16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2387 = TEST16i16 { 2388, 6, 0, 0, "TEST16mi", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2388 = TEST16mi { 2389, 2, 0, 0, "TEST16ri", 0, 0|16|(1<<6)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #2389 = TEST16ri { 2390, 6, 0, 0, "TEST16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #2390 = TEST16rm { 2391, 2, 0, 0, "TEST16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #2391 = TEST16rr { 2392, 1, 0, 0, "TEST32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2392 = TEST32i32 { 2393, 6, 0, 0, "TEST32mi", 0|(1<<TID::MayLoad), 0|24|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2393 = TEST32mi { 2394, 2, 0, 0, "TEST32ri", 0, 0|16|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #2394 = TEST32ri { 2395, 6, 0, 0, "TEST32rm", 0|(1<<TID::MayLoad), 0|6|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #2395 = TEST32rm { 2396, 2, 0, 0, "TEST32rr", 0|(1<<TID::Commutable), 0|3|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #2396 = TEST32rr { 2397, 1, 0, 0, "TEST64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2397 = TEST64i32 { 2398, 6, 0, 0, "TEST64mi32", 0|(1<<TID::MayLoad), 0|24|(1<<12)|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2398 = TEST64mi32 { 2399, 2, 0, 0, "TEST64ri32", 0, 0|16|(1<<12)|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #2399 = TEST64ri32 { 2400, 6, 0, 0, "TEST64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #2400 = TEST64rm { 2401, 2, 0, 0, "TEST64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #2401 = TEST64rr { 2402, 1, 0, 0, "TEST8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(168<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2402 = TEST8i8 { 2403, 6, 0, 0, "TEST8mi", 0|(1<<TID::MayLoad), 0|24|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2403 = TEST8mi { 2404, 2, 0, 0, "TEST8ri", 0, 0|16|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #2404 = TEST8ri { 2405, 6, 0, 0, "TEST8rm", 0|(1<<TID::MayLoad), 0|6|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo69 }, // Inst #2405 = TEST8rm { 2406, 2, 0, 0, "TEST8rr", 0|(1<<TID::Commutable), 0|3|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #2406 = TEST8rr { 2407, 4, 0, 0, "TLS_addr32", 0, 0, ImplicitList2, ImplicitList9, Barriers3, OperandInfo197 }, // Inst #2407 = TLS_addr32 { 2408, 4, 0, 0, "TLS_addr64", 0, 0, ImplicitList4, ImplicitList10, Barriers4, OperandInfo198 }, // Inst #2408 = TLS_addr64 { 2409, 0, 0, 0, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(11<<24), NULL, NULL, NULL, 0 }, // Inst #2409 = TRAP { 2410, 0, 0, 0, "TST_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(228<<24), NULL, NULL, NULL, 0 }, // Inst #2410 = TST_F { 2411, 1, 0, 0, "TST_Fp32", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #2411 = TST_Fp32 { 2412, 1, 0, 0, "TST_Fp64", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #2412 = TST_Fp64 { 2413, 1, 0, 0, "TST_Fp80", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #2413 = TST_Fp80 { 2414, 6, 0, 0, "UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo82 }, // Inst #2414 = UCOMISDrm { 2415, 2, 0, 0, "UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo105 }, // Inst #2415 = UCOMISDrr { 2416, 6, 0, 0, "UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo80 }, // Inst #2416 = UCOMISSrm { 2417, 2, 0, 0, "UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo106 }, // Inst #2417 = UCOMISSrr { 2418, 1, 0, 0, "UCOM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2418 = UCOM_FIPr { 2419, 1, 0, 0, "UCOM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2419 = UCOM_FIr { 2420, 0, 0, 0, "UCOM_FPPr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(5<<8)|(233<<24), ImplicitList24, ImplicitList1, Barriers1, 0 }, // Inst #2420 = UCOM_FPPr { 2421, 1, 0, 0, "UCOM_FPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2421 = UCOM_FPr { 2422, 2, 0, 0, "UCOM_FpIr32", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2422 = UCOM_FpIr32 { 2423, 2, 0, 0, "UCOM_FpIr64", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2423 = UCOM_FpIr64 { 2424, 2, 0, 0, "UCOM_FpIr80", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2424 = UCOM_FpIr80 { 2425, 2, 0, 0, "UCOM_Fpr32", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2425 = UCOM_Fpr32 { 2426, 2, 0, 0, "UCOM_Fpr64", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2426 = UCOM_Fpr64 { 2427, 2, 0, 0, "UCOM_Fpr80", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2427 = UCOM_Fpr80 { 2428, 1, 0, 0, "UCOM_Fr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(224<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2428 = UCOM_Fr { 2429, 7, 1, 0, "UNPCKHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2429 = UNPCKHPDrm { 2430, 3, 1, 0, "UNPCKHPDrr", 0, 0|5|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2430 = UNPCKHPDrr { 2431, 7, 1, 0, "UNPCKHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2431 = UNPCKHPSrm { 2432, 3, 1, 0, "UNPCKHPSrr", 0, 0|5|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2432 = UNPCKHPSrr { 2433, 7, 1, 0, "UNPCKLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2433 = UNPCKLPDrm { 2434, 3, 1, 0, "UNPCKLPDrr", 0, 0|5|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2434 = UNPCKLPDrr { 2435, 7, 1, 0, "UNPCKLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2435 = UNPCKLPSrm { 2436, 3, 1, 0, "UNPCKLPSrr", 0, 0|5|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2436 = UNPCKLPSrr { 2437, 3, 0, 0, "VASTART_SAVE_XMM_REGS", 0|(1<<TID::UsesCustomInserter)|(1<<TID::Variadic), 0, NULL, NULL, NULL, OperandInfo199 }, // Inst #2437 = VASTART_SAVE_XMM_REGS { 2438, 5, 0, 0, "VERRm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2438 = VERRm { 2439, 1, 0, 0, "VERRr", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2439 = VERRr { 2440, 5, 0, 0, "VERWm", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2440 = VERWm { 2441, 1, 0, 0, "VERWr", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2441 = VERWr { 2442, 0, 0, 0, "VMCALL", 0|(1<<TID::UnmodeledSideEffects), 0|33|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2442 = VMCALL { 2443, 5, 0, 0, "VMCLEARm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2443 = VMCLEARm { 2444, 0, 0, 0, "VMLAUNCH", 0|(1<<TID::UnmodeledSideEffects), 0|34|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2444 = VMLAUNCH { 2445, 5, 0, 0, "VMPTRLDm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2445 = VMPTRLDm { 2446, 5, 1, 0, "VMPTRSTm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2446 = VMPTRSTm { 2447, 6, 1, 0, "VMREAD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2447 = VMREAD32rm { 2448, 2, 1, 0, "VMREAD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2448 = VMREAD32rr { 2449, 6, 1, 0, "VMREAD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2449 = VMREAD64rm { 2450, 2, 1, 0, "VMREAD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2450 = VMREAD64rr { 2451, 0, 0, 0, "VMRESUME", 0|(1<<TID::UnmodeledSideEffects), 0|35|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2451 = VMRESUME { 2452, 6, 1, 0, "VMWRITE32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #2452 = VMWRITE32rm { 2453, 2, 1, 0, "VMWRITE32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2453 = VMWRITE32rr { 2454, 6, 1, 0, "VMWRITE64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #2454 = VMWRITE64rm { 2455, 2, 1, 0, "VMWRITE64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2455 = VMWRITE64rr { 2456, 0, 0, 0, "VMXOFF", 0|(1<<TID::UnmodeledSideEffects), 0|36|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2456 = VMXOFF { 2457, 5, 0, 0, "VMXON", 0|(1<<TID::UnmodeledSideEffects), 0|30|(11<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2457 = VMXON { 2458, 1, 1, 0, "V_SET0", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo200 }, // Inst #2458 = V_SET0 { 2459, 1, 1, 0, "V_SETALLONES", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo200 }, // Inst #2459 = V_SETALLONES { 2460, 0, 0, 0, "WAIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(155<<24), NULL, NULL, NULL, 0 }, // Inst #2460 = WAIT { 2461, 0, 0, 0, "WBINVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(9<<24), NULL, NULL, NULL, 0 }, // Inst #2461 = WBINVD { 2462, 5, 0, 0, "WINCALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo30 }, // Inst #2462 = WINCALL64m { 2463, 1, 0, 0, "WINCALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(232<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo5 }, // Inst #2463 = WINCALL64pcrel32 { 2464, 1, 0, 0, "WINCALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo58 }, // Inst #2464 = WINCALL64r { 2465, 0, 0, 0, "WRMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(48<<24), NULL, NULL, NULL, 0 }, // Inst #2465 = WRMSR { 2466, 6, 0, 0, "XADD16rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #2466 = XADD16rm { 2467, 2, 1, 0, "XADD16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #2467 = XADD16rr { 2468, 6, 0, 0, "XADD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2468 = XADD32rm { 2469, 2, 1, 0, "XADD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2469 = XADD32rr { 2470, 6, 0, 0, "XADD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2470 = XADD64rm { 2471, 2, 1, 0, "XADD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2471 = XADD64rr { 2472, 6, 0, 0, "XADD8rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #2472 = XADD8rm { 2473, 2, 1, 0, "XADD8rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #2473 = XADD8rr { 2474, 1, 0, 0, "XCHG16ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<6)|(144<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2474 = XCHG16ar { 2475, 7, 1, 0, "XCHG16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo9 }, // Inst #2475 = XCHG16rm { 2476, 3, 1, 0, "XCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo10 }, // Inst #2476 = XCHG16rr { 2477, 1, 0, 0, "XCHG32ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(144<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2477 = XCHG32ar { 2478, 7, 1, 0, "XCHG32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(135<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #2478 = XCHG32rm { 2479, 3, 1, 0, "XCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(135<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #2479 = XCHG32rr { 2480, 1, 0, 0, "XCHG64ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<12)|(144<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2480 = XCHG64ar { 2481, 7, 1, 0, "XCHG64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #2481 = XCHG64rm { 2482, 3, 1, 0, "XCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #2482 = XCHG64rr { 2483, 7, 1, 0, "XCHG8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(134<<24), NULL, NULL, NULL, OperandInfo22 }, // Inst #2483 = XCHG8rm { 2484, 3, 1, 0, "XCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(134<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2484 = XCHG8rr { 2485, 1, 0, 0, "XCH_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2485 = XCH_F { 2486, 0, 0, 0, "XLAT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(215<<24), NULL, NULL, NULL, 0 }, // Inst #2486 = XLAT { 2487, 1, 0, 0, "XOR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2487 = XOR16i16 { 2488, 6, 0, 0, "XOR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2488 = XOR16mi { 2489, 6, 0, 0, "XOR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2489 = XOR16mi8 { 2490, 6, 0, 0, "XOR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2490 = XOR16mr { 2491, 3, 1, 0, "XOR16ri", 0, 0|22|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2491 = XOR16ri { 2492, 3, 1, 0, "XOR16ri8", 0, 0|22|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2492 = XOR16ri8 { 2493, 7, 1, 0, "XOR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2493 = XOR16rm { 2494, 3, 1, 0, "XOR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2494 = XOR16rr { 2495, 3, 1, 0, "XOR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2495 = XOR16rr_REV { 2496, 1, 0, 0, "XOR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2496 = XOR32i32 { 2497, 6, 0, 0, "XOR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2497 = XOR32mi { 2498, 6, 0, 0, "XOR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2498 = XOR32mi8 { 2499, 6, 0, 0, "XOR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2499 = XOR32mr { 2500, 3, 1, 0, "XOR32ri", 0, 0|22|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2500 = XOR32ri { 2501, 3, 1, 0, "XOR32ri8", 0, 0|22|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2501 = XOR32ri8 { 2502, 7, 1, 0, "XOR32rm", 0|(1<<TID::MayLoad), 0|6|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2502 = XOR32rm { 2503, 3, 1, 0, "XOR32rr", 0|(1<<TID::Commutable), 0|3|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2503 = XOR32rr { 2504, 3, 1, 0, "XOR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2504 = XOR32rr_REV { 2505, 1, 0, 0, "XOR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2505 = XOR64i32 { 2506, 6, 0, 0, "XOR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2506 = XOR64mi32 { 2507, 6, 0, 0, "XOR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2507 = XOR64mi8 { 2508, 6, 0, 0, "XOR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2508 = XOR64mr { 2509, 3, 1, 0, "XOR64ri32", 0, 0|22|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2509 = XOR64ri32 { 2510, 3, 1, 0, "XOR64ri8", 0, 0|22|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2510 = XOR64ri8 { 2511, 7, 1, 0, "XOR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2511 = XOR64rm { 2512, 3, 1, 0, "XOR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2512 = XOR64rr { 2513, 3, 1, 0, "XOR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2513 = XOR64rr_REV { 2514, 1, 0, 0, "XOR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(52<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2514 = XOR8i8 { 2515, 6, 0, 0, "XOR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2515 = XOR8mi { 2516, 6, 0, 0, "XOR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2516 = XOR8mr { 2517, 3, 1, 0, "XOR8ri", 0, 0|22|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2517 = XOR8ri { 2518, 7, 1, 0, "XOR8rm", 0|(1<<TID::MayLoad), 0|6|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2518 = XOR8rm { 2519, 3, 1, 0, "XOR8rr", 0|(1<<TID::Commutable), 0|3|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2519 = XOR8rr { 2520, 3, 1, 0, "XOR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2520 = XOR8rr_REV { 2521, 7, 1, 0, "XORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2521 = XORPDrm { 2522, 3, 1, 0, "XORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2522 = XORPDrr { 2523, 7, 1, 0, "XORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2523 = XORPSrm { 2524, 3, 1, 0, "XORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2524 = XORPSrr }; } // End llvm namespace