//===- TableGen'erated file -------------------------------------*- C++ -*-===//
//
// Assembly Writer Source Fragment
//
// Automatically generated file, do not edit!
//
//===----------------------------------------------------------------------===//
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
static const unsigned OpInfo[] = {
0U, // PHI
0U, // INLINEASM
0U, // DBG_LABEL
0U, // EH_LABEL
0U, // GC_LABEL
0U, // KILL
0U, // EXTRACT_SUBREG
0U, // INSERT_SUBREG
0U, // IMPLICIT_DEF
0U, // SUBREG_TO_REG
0U, // COPY_TO_REGCLASS
1U, // DBG_VALUE
67108875U, // ADCSSri
67108875U, // ADCSSrr
67108875U, // ADCSSrs
134758417U, // ADCri
134774801U, // ADCrr
202375185U, // ADCrs
135839765U, // ADDSri
135839765U, // ADDSrr
202948629U, // ADDSrs
134758426U, // ADDri
134774810U, // ADDrr
202375194U, // ADDrs
69206046U, // ADJCALLSTACKDOWN
69206066U, // ADJCALLSTACKUP
134758468U, // ANDri
134774852U, // ANDrr
202375236U, // ANDrs
271056968U, // ATOMIC_CMP_SWAP_I16
271581256U, // ATOMIC_CMP_SWAP_I32
272105544U, // ATOMIC_CMP_SWAP_I8
272629832U, // ATOMIC_LOAD_ADD_I16
273154120U, // ATOMIC_LOAD_ADD_I32
273678408U, // ATOMIC_LOAD_ADD_I8
274202696U, // ATOMIC_LOAD_AND_I16
274726984U, // ATOMIC_LOAD_AND_I32
275251272U, // ATOMIC_LOAD_AND_I8
275775560U, // ATOMIC_LOAD_NAND_I16
276299848U, // ATOMIC_LOAD_NAND_I32
276824136U, // ATOMIC_LOAD_NAND_I8
277348424U, // ATOMIC_LOAD_OR_I16
277872712U, // ATOMIC_LOAD_OR_I32
278397000U, // ATOMIC_LOAD_OR_I8
278921288U, // ATOMIC_LOAD_SUB_I16
279445576U, // ATOMIC_LOAD_SUB_I32
279969864U, // ATOMIC_LOAD_SUB_I8
280494152U, // ATOMIC_LOAD_XOR_I16
281018440U, // ATOMIC_LOAD_XOR_I32
281542728U, // ATOMIC_LOAD_XOR_I8
282067016U, // ATOMIC_SWAP_I16
282591304U, // ATOMIC_SWAP_I32
283115592U, // ATOMIC_SWAP_I8
69206089U, // B
135839820U, // BFC
134758480U, // BICri
134774864U, // BICrr
202375248U, // BICrs
337166420U, // BKPT
402653273U, // BL
69206109U, // BLX
69206109U, // BLXr9
337182818U, // BL_pred
402653273U, // BLr9
337182818U, // BLr9_pred
69206117U, // BRIND
67108969U, // BR_JTadd
469762162U, // BR_JTm
82313339U, // BR_JTr
69206148U, // BX
337166484U, // BXJ
552599704U, // BX_RET
69206148U, // BXr9
337166491U, // Bcc
620314781U, // CDP
687866017U, // CDP2
739819688U, // CLZ
739819692U, // CMNzri
739819692U, // CMNzrr
806928556U, // CMNzrs
739819696U, // CMPri
739819696U, // CMPrr
806928560U, // CMPrs
739819696U, // CMPzri
739819696U, // CMPzrr
806928560U, // CMPzrs
872415304U, // CONSTPOOL_ENTRY
939524276U, // CPS
337166520U, // DBG
134758588U, // EORri
134774972U, // EORrr
202375356U, // EORrs
755597504U, // FCONSTD
756121792U, // FCONSTS
555221189U, // FMSTAT
85983434U, // Int_MemBarrierV6
215U, // Int_MemBarrierV7
86507722U, // Int_SyncBarrierV6
219U, // Int_SyncBarrierV7
87032031U, // Int_eh_sjlj_setjmp
1008320745U, // LDM
1008320745U, // LDM_RET
806928621U, // LDR
806928625U, // LDRB
202948849U, // LDRBT
202948849U, // LDRB_POST
202948849U, // LDRB_PRE
202948854U, // LDRD
739819771U, // LDREX
739819777U, // LDREXB
135840008U, // LDREXD
739819791U, // LDREXH
806928662U, // LDRH
202948886U, // LDRH_POST
202948886U, // LDRH_PRE
806928667U, // LDRSB
202948891U, // LDRSB_POST
202948891U, // LDRSB_PRE
806928673U, // LDRSH
202948897U, // LDRSH_POST
202948897U, // LDRSH_PRE
202948903U, // LDRT
202948845U, // LDR_POST
202948845U, // LDR_PRE
806928621U, // LDRcp
1094189356U, // LEApcrel
1094713644U, // LEApcrelJT
620331314U, // MCR
671121718U, // MCR2
217678141U, // MCRR
671121730U, // MCRR2
826802506U, // MLA
806928718U, // MLS
135840082U, // MOVCCi
135840082U, // MOVCCr
202948946U, // MOVCCs
135840086U, // MOVTi16
760349010U, // MOVi
739819867U, // MOVi16
739819858U, // MOVi2pieces
739819867U, // MOVi32imm
760217938U, // MOVr
760217938U, // MOVrx
826949970U, // MOVs
739819872U, // MOVsra_flag
739819872U, // MOVsrl_flag
620331365U, // MRC
671121769U, // MRC2
217678192U, // MRRC
671121781U, // MRRC2
337166717U, // MRS
337166717U, // MRSsys
358089085U, // MSR
358613373U, // MSRsys
134775169U, // MUL
760349061U, // MVNi
760217989U, // MVNr
826950021U, // MVNs
538968457U, // NOP
134758797U, // ORRri
134775181U, // ORRrr
202375565U, // ORRrs
1164444049U, // PICADD
1232077201U, // PICLDR
1232601489U, // PICLDRB
1233125777U, // PICLDRH
1233650065U, // PICLDRSB
1234174353U, // PICLDRSH
1234698641U, // PICSTR
1235222929U, // PICSTRB
1235747217U, // PICSTRH
806928787U, // PKHBT
806928793U, // PKHTB
135840159U, // QADD
135840164U, // QADD16
135840171U, // QADD8
135840177U, // QASX
135840182U, // QDADD
135840188U, // QDSUB
135840194U, // QSAX
135840199U, // QSUB
135840204U, // QSUB16
135840211U, // QSUB8
739819993U, // RBIT
739819998U, // REV
739820002U, // REV16
739820008U, // REVSH
135840238U, // RSBSri
202949102U, // RSBSrs
134758899U, // RSBri
202375667U, // RSBrs
67109367U, // RSCSri
67109367U, // RSCSrs
134758909U, // RSCri
202375677U, // RSCrs
67109377U, // SBCSSri
67109377U, // SBCSSrr
67109377U, // SBCSSrs
134758919U, // SBCri
134775303U, // SBCrr
202375687U, // SBCrs
806928907U, // SBFX
528U, // SETENDBE
538U, // SETENDLE
538968612U, // SEV
806928936U, // SMLABB
806928943U, // SMLABT
826802742U, // SMLAL
806928956U, // SMLALBB
806928964U, // SMLALBT
806928972U, // SMLALTB
806928980U, // SMLALTT
806928988U, // SMLATB
806928995U, // SMLATT
806929002U, // SMLAWB
806929009U, // SMLAWT
806929016U, // SMMLA
806929022U, // SMMLS
135840388U, // SMMUL
135840394U, // SMULBB
135840401U, // SMULBT
826802840U, // SMULL
135840414U, // SMULTB
135840421U, // SMULTT
135840428U, // SMULWB
135840435U, // SMULWT
1008321210U, // STM
806929086U, // STR
806929090U, // STRB
202900167U, // STRBT
202900162U, // STRB_POST
202900162U, // STRB_PRE
202949325U, // STRD
135840466U, // STREX
135840472U, // STREXB
806929119U, // STREXD
135840486U, // STREXH
806929133U, // STRH
202900205U, // STRH_POST
202900205U, // STRH_PRE
202900210U, // STRT
202900158U, // STR_POST
202900158U, // STR_PRE
135840503U, // SUBSri
135840503U, // SUBSrr
202949367U, // SUBSrs
134759164U, // SUBri
134775548U, // SUBrr
202375932U, // SUBrs
337167104U, // SVC
135840516U, // SWP
135840520U, // SWPB
135840525U, // SXTABrr
806929165U, // SXTABrr_rot
135840531U, // SXTAHrr
806929171U, // SXTAHrr_rot
739820313U, // SXTBr
135840537U, // SXTBr_rot
739820318U, // SXTHr
135840542U, // SXTHr_rot
739820323U, // TEQri
739820323U, // TEQrr
806929187U, // TEQrs
807U, // TPsoft
538968890U, // TRAP
739820351U, // TSTri
739820351U, // TSTrr
806929215U, // TSTrs
806929219U, // UBFX
806929224U, // UMAAL
826803022U, // UMLAL
826803028U, // UMULL
135840602U, // UQADD16
135840610U, // UQADD8
135840617U, // UQASX
135840623U, // UQSAX
135840629U, // UQSUB16
135840637U, // UQSUB8
135840644U, // UXTABrr
806929284U, // UXTABrr_rot
135840650U, // UXTAHrr
806929290U, // UXTAHrr_rot
739820432U, // UXTB16r
135840656U, // UXTB16r_rot
739820439U, // UXTBr
135840663U, // UXTBr_rot
739820444U, // UXTHr
135840668U, // UXTHr_rot
833651617U, // VABALsv2i64
834175905U, // VABALsv4i32
834700193U, // VABALsv8i16
835224481U, // VABALuv2i64
835748769U, // VABALuv4i32
836273057U, // VABALuv8i16
834700199U, // VABAsv16i8
833651623U, // VABAsv2i32
834175911U, // VABAsv4i16
833651623U, // VABAsv4i32
834175911U, // VABAsv8i16
834700199U, // VABAsv8i8
836273063U, // VABAuv16i8
835224487U, // VABAuv2i32
835748775U, // VABAuv4i16
835224487U, // VABAuv4i32
835748775U, // VABAuv8i16
836273063U, // VABAuv8i8
162530220U, // VABDLsv2i64
163054508U, // VABDLsv4i32
163578796U, // VABDLsv8i16
164103084U, // VABDLuv2i64
164627372U, // VABDLuv4i32
165151660U, // VABDLuv8i16
152142770U, // VABDfd
152142770U, // VABDfq
163578802U, // VABDsv16i8
162530226U, // VABDsv2i32
163054514U, // VABDsv4i16
162530226U, // VABDsv4i32
163054514U, // VABDsv8i16
163578802U, // VABDsv8i8
165151666U, // VABDuv16i8
164103090U, // VABDuv2i32
164627378U, // VABDuv4i16
164103090U, // VABDuv4i32
164627378U, // VABDuv8i16
165151666U, // VABDuv8i8
755598263U, // VABSD
756122551U, // VABSS
756122551U, // VABSfd
756122551U, // VABSfd_sfp
756122551U, // VABSfq
767558583U, // VABSv16i8
766510007U, // VABSv2i32
767034295U, // VABSv4i16
766510007U, // VABSv4i32
767034295U, // VABSv8i16
767558583U, // VABSv8i8
152142780U, // VACGEd
152142780U, // VACGEq
152142786U, // VACGTd
152142786U, // VACGTq
151618504U, // VADDD
165675981U, // VADDHNv2i32
166200269U, // VADDHNv4i16
166724557U, // VADDHNv8i8
162530260U, // VADDLsv2i64
163054548U, // VADDLsv4i32
163578836U, // VADDLsv8i16
164103124U, // VADDLuv2i64
164627412U, // VADDLuv4i32
165151700U, // VADDLuv8i16
152142792U, // VADDS
162530266U, // VADDWsv2i64
163054554U, // VADDWsv4i32
163578842U, // VADDWsv8i16
164103130U, // VADDWuv2i64
164627418U, // VADDWuv4i32
165151706U, // VADDWuv8i16
152142792U, // VADDfd
152142792U, // VADDfd_sfp
152142792U, // VADDfq
167248840U, // VADDv16i8
165675976U, // VADDv1i64
166200264U, // VADDv2i32
165675976U, // VADDv2i64
166724552U, // VADDv4i16
166200264U, // VADDv4i32
166724552U, // VADDv8i16
167248840U, // VADDv8i8
135840736U, // VANDd
135840736U, // VANDq
135840741U, // VBICd
135840741U, // VBICq
806929386U, // VBIFd
806929386U, // VBIFq
806929391U, // VBITd
806929391U, // VBITq
806929396U, // VBSLd
806929396U, // VBSLq
152142841U, // VCEQfd
152142841U, // VCEQfq
167248889U, // VCEQv16i8
166200313U, // VCEQv2i32
166724601U, // VCEQv4i16
166200313U, // VCEQv4i32
166724601U, // VCEQv8i16
167248889U, // VCEQv8i8
152142846U, // VCGEfd
152142846U, // VCGEfq
163578878U, // VCGEsv16i8
162530302U, // VCGEsv2i32
163054590U, // VCGEsv4i16
162530302U, // VCGEsv4i32
163054590U, // VCGEsv8i16
163578878U, // VCGEsv8i8
165151742U, // VCGEuv16i8
164103166U, // VCGEuv2i32
164627454U, // VCGEuv4i16
164103166U, // VCGEuv4i32
164627454U, // VCGEuv8i16
165151742U, // VCGEuv8i8
152142851U, // VCGTfd
152142851U, // VCGTfq
163578883U, // VCGTsv16i8
162530307U, // VCGTsv2i32
163054595U, // VCGTsv4i16
162530307U, // VCGTsv4i32
163054595U, // VCGTsv8i16
163578883U, // VCGTsv8i8
165151747U, // VCGTuv16i8
164103171U, // VCGTuv2i32
164627459U, // VCGTuv4i16
164103171U, // VCGTuv4i32
164627459U, // VCGTuv8i16
165151747U, // VCGTuv8i8
767558664U, // VCLSv16i8
766510088U, // VCLSv2i32
767034376U, // VCLSv4i16
766510088U, // VCLSv4i32
767034376U, // VCLSv8i16
767558664U, // VCLSv8i8
771228685U, // VCLZv16i8
770180109U, // VCLZv2i32
770704397U, // VCLZv4i16
770180109U, // VCLZv4i32
770704397U, // VCLZv8i16
771228685U, // VCLZv8i8
755598354U, // VCMPD
755598359U, // VCMPED
756122647U, // VCMPES
353010711U, // VCMPEZD
353534999U, // VCMPEZS
756122642U, // VCMPS
353010706U, // VCMPZD
353534994U, // VCMPZS
771802141U, // VCNTd
771802141U, // VCNTq
772277282U, // VCVTBHS
772801570U, // VCVTBSH
773325864U, // VCVTDS
773850152U, // VCVTSD
772277293U, // VCVTTHS
772801581U, // VCVTTSH
774554664U, // VCVTf2sd
774554664U, // VCVTf2sd_sfp
774554664U, // VCVTf2sq
775078952U, // VCVTf2ud
775078952U, // VCVTf2ud_sfp
775078952U, // VCVTf2uq
170492968U, // VCVTf2xsd
170492968U, // VCVTf2xsq
171017256U, // VCVTf2xud
171017256U, // VCVTf2xuq
775603240U, // VCVTs2fd
775603240U, // VCVTs2fd_sfp
775603240U, // VCVTs2fq
776127528U, // VCVTu2fd
776127528U, // VCVTu2fd_sfp
776127528U, // VCVTu2fq
171541544U, // VCVTxs2fd
171541544U, // VCVTxs2fq
172065832U, // VCVTxu2fd
172065832U, // VCVTxu2fq
151618611U, // VDIVD
152142899U, // VDIVS
776520760U, // VDUP16d
776520760U, // VDUP16q
777045048U, // VDUP32d
777045048U, // VDUP32q
771802168U, // VDUP8d
771802168U, // VDUP8q
172540984U, // VDUPLN16d
172540984U, // VDUPLN16q
173065272U, // VDUPLN32d
173065272U, // VDUPLN32q
167822392U, // VDUPLN8d
167822392U, // VDUPLN8q
173065272U, // VDUPLNfd
173065272U, // VDUPLNfq
777045048U, // VDUPfd
777045048U, // VDUPfdf
777045048U, // VDUPfq
777045048U, // VDUPfqf
135840829U, // VEORd
135840829U, // VEORq
843629634U, // VEXTd16
844153922U, // VEXTd32
838911042U, // VEXTd8
844153922U, // VEXTdf
843629634U, // VEXTq16
844153922U, // VEXTq32
838911042U, // VEXTq8
844153922U, // VEXTqf
173064384U, // VGETLNi32
163053760U, // VGETLNs16
163578048U, // VGETLNs8
164626624U, // VGETLNu16
165150912U, // VGETLNu8
163578951U, // VHADDsv16i8
162530375U, // VHADDsv2i32
163054663U, // VHADDsv4i16
162530375U, // VHADDsv4i32
163054663U, // VHADDsv8i16
163578951U, // VHADDsv8i8
165151815U, // VHADDuv16i8
164103239U, // VHADDuv2i32
164627527U, // VHADDuv4i16
164103239U, // VHADDuv4i32
164627527U, // VHADDuv8i16
165151815U, // VHADDuv8i8
163578957U, // VHSUBsv16i8
162530381U, // VHSUBsv2i32
163054669U, // VHSUBsv4i16
162530381U, // VHSUBsv4i32
163054669U, // VHSUBsv8i16
163578957U, // VHSUBsv8i8
165151821U, // VHSUBuv16i8
164103245U, // VHSUBuv2i32
164627533U, // VHSUBuv4i16
164103245U, // VHSUBuv4i32
164627533U, // VHSUBuv8i16
165151821U, // VHSUBuv8i8
240698451U, // VLD1d16
241222739U, // VLD1d32
241747027U, // VLD1d64
242271315U, // VLD1d8
241222739U, // VLD1df
239797331U, // VLD1q16
240321619U, // VLD1q32
242943059U, // VLD1q64
235078739U, // VLD1q8
240321619U, // VLD1qf
1314440280U, // VLD2LNd16
1314964568U, // VLD2LNd32
1316013144U, // VLD2LNd8
1314440280U, // VLD2LNq16a
1314440280U, // VLD2LNq16b
1314964568U, // VLD2LNq32a
1314964568U, // VLD2LNq32b
643351640U, // VLD2d16
643875928U, // VLD2d32
644400211U, // VLD2d64
644924504U, // VLD2d8
1381549144U, // VLD2q16
1382073432U, // VLD2q32
1383122008U, // VLD2q8
1448658013U, // VLD3LNd16
1449182301U, // VLD3LNd32
1450230877U, // VLD3LNd8
1448658013U, // VLD3LNq16a
1448658013U, // VLD3LNq16b
1449182301U, // VLD3LNq32a
1449182301U, // VLD3LNq32b
1515766877U, // VLD3d16
1516291165U, // VLD3d32
1516815443U, // VLD3d64
1517339741U, // VLD3d8
1381549149U, // VLD3q16a
1381549149U, // VLD3q16b
1382073437U, // VLD3q32a
1382073437U, // VLD3q32b
1383122013U, // VLD3q8a
1383122013U, // VLD3q8b
1582875746U, // VLD4LNd16
1583400034U, // VLD4LNd32
1584448610U, // VLD4LNd8
1582875746U, // VLD4LNq16a
1582875746U, // VLD4LNq16b
1583400034U, // VLD4LNq32a
1583400034U, // VLD4LNq32b
1381549154U, // VLD4d16
1382073442U, // VLD4d32
1382597715U, // VLD4d64
1383122018U, // VLD4d8
1314440290U, // VLD4q16a
1314440290U, // VLD4q16b
1314964578U, // VLD4q32a
1314964578U, // VLD4q32b
1316013154U, // VLD4q8a
1316013154U, // VLD4q8b
1610613863U, // VLDMD
1610613863U, // VLDMS
175686764U, // VLDRD
136004721U, // VLDRQ
173065324U, // VLDRS
152142968U, // VMAXfd
152142968U, // VMAXfq
163579000U, // VMAXsv16i8
162530424U, // VMAXsv2i32
163054712U, // VMAXsv4i16
162530424U, // VMAXsv4i32
163054712U, // VMAXsv8i16
163579000U, // VMAXsv8i8
165151864U, // VMAXuv16i8
164103288U, // VMAXuv2i32
164627576U, // VMAXuv4i16
164103288U, // VMAXuv4i32
164627576U, // VMAXuv8i16
165151864U, // VMAXuv8i8
152142973U, // VMINfd
152142973U, // VMINfq
163579005U, // VMINsv16i8
162530429U, // VMINsv2i32
163054717U, // VMINsv4i16
162530429U, // VMINsv4i32
163054717U, // VMINsv8i16
163579005U, // VMINsv8i8
165151869U, // VMINuv16i8
164103293U, // VMINuv2i32
164627581U, // VMINuv4i16
164103293U, // VMINuv4i32
164627581U, // VMINuv8i16
165151869U, // VMINuv8i8
822707330U, // VMLAD
229672071U, // VMLALslsv2i32
230196359U, // VMLALslsv4i16
231244935U, // VMLALsluv2i32
231769223U, // VMLALsluv4i16
833651847U, // VMLALsv2i64
834176135U, // VMLALsv4i32
834700423U, // VMLALsv8i16
835224711U, // VMLALuv2i64
835748999U, // VMLALuv4i32
836273287U, // VMLALuv8i16
823231618U, // VMLAS
823231618U, // VMLAfd
823231618U, // VMLAfq
219251842U, // VMLAslfd
219251842U, // VMLAslfq
233342082U, // VMLAslv2i32
233866370U, // VMLAslv4i16
233342082U, // VMLAslv4i32
233866370U, // VMLAslv8i16
838370434U, // VMLAv16i8
837321858U, // VMLAv2i32
837846146U, // VMLAv4i16
837321858U, // VMLAv4i32
837846146U, // VMLAv8i16
838370434U, // VMLAv8i8
822707341U, // VMLSD
229672082U, // VMLSLslsv2i32
230196370U, // VMLSLslsv4i16
231244946U, // VMLSLsluv2i32
231769234U, // VMLSLsluv4i16
833651858U, // VMLSLsv2i64
834176146U, // VMLSLsv4i32
834700434U, // VMLSLsv8i16
835224722U, // VMLSLuv2i64
835749010U, // VMLSLuv4i32
836273298U, // VMLSLuv8i16
823231629U, // VMLSS
823231629U, // VMLSfd
823231629U, // VMLSfq
219251853U, // VMLSslfd
219251853U, // VMLSslfq
233342093U, // VMLSslv2i32
233866381U, // VMLSslv4i16
233342093U, // VMLSslv4i32
233866381U, // VMLSslv8i16
838370445U, // VMLSv16i8
837321869U, // VMLSv2i32
837846157U, // VMLSv4i16
837321869U, // VMLSv4i32
837846157U, // VMLSv8i16
838370445U, // VMLSv8i8
755597504U, // VMOVD
135839936U, // VMOVDRR
151617728U, // VMOVDcc
739819712U, // VMOVDneon
766510232U, // VMOVLsv2i64
767034520U, // VMOVLsv4i32
767558808U, // VMOVLsv8i16
768083096U, // VMOVLuv2i64
768607384U, // VMOVLuv4i32
769131672U, // VMOVLuv8i16
769655966U, // VMOVNv2i32
770180254U, // VMOVNv4i16
770704542U, // VMOVNv8i8
739819712U, // VMOVQ
135839936U, // VMOVRRD
806928576U, // VMOVRRS
739819712U, // VMOVRS
756121792U, // VMOVS
739819712U, // VMOVSR
806928576U, // VMOVSRR
152142016U, // VMOVScc
771457216U, // VMOVv16i8
769900736U, // VMOVv1i64
770441408U, // VMOVv2i32
769900736U, // VMOVv2i64
770982080U, // VMOVv4i16
770441408U, // VMOVv4i32
770982080U, // VMOVv8i16
771457216U, // VMOVv8i8
337166533U, // VMRS
377488548U, // VMSR
151618729U, // VMULD
176686254U, // VMULLp
833619118U, // VMULLslsv2i32
834143406U, // VMULLslsv4i16
835191982U, // VMULLsluv2i32
835716270U, // VMULLsluv4i16
162530478U, // VMULLsv2i64
163054766U, // VMULLsv4i32
163579054U, // VMULLsv8i16
164103342U, // VMULLuv2i64
164627630U, // VMULLuv4i32
165151918U, // VMULLuv8i16
152143017U, // VMULS
152143017U, // VMULfd
152143017U, // VMULfd_sfp
152143017U, // VMULfq
176686249U, // VMULpd
176686249U, // VMULpq
823231657U, // VMULslfd
823231657U, // VMULslfq
837289129U, // VMULslv2i32
837813417U, // VMULslv4i16
837289129U, // VMULslv4i32
837813417U, // VMULslv8i16
167249065U, // VMULv16i8
166200489U, // VMULv2i32
166724777U, // VMULv4i16
166200489U, // VMULv4i32
166724777U, // VMULv8i16
167249065U, // VMULv8i8
739820724U, // VMVNd
739820724U, // VMVNq
755598521U, // VNEGD
151618745U, // VNEGDcc
756122809U, // VNEGS
152143033U, // VNEGScc
756122809U, // VNEGf32d
756122809U, // VNEGf32d_sfp
756122809U, // VNEGf32q
767034553U, // VNEGs16d
767034553U, // VNEGs16q
766510265U, // VNEGs32d
766510265U, // VNEGs32q
767558841U, // VNEGs8d
767558841U, // VNEGs8q
822707390U, // VNMLAD
823231678U, // VNMLAS
822707396U, // VNMLSD
823231684U, // VNMLSS
151618762U, // VNMULD
152143050U, // VNMULS
135840976U, // VORNd
135840976U, // VORNq
135840981U, // VORRd
135840981U, // VORRq
163611866U, // VPADALsv16i8
162563290U, // VPADALsv2i32
163087578U, // VPADALsv4i16
162563290U, // VPADALsv4i32
163087578U, // VPADALsv8i16
163611866U, // VPADALsv8i8
165184730U, // VPADALuv16i8
164136154U, // VPADALuv2i32
164660442U, // VPADALuv4i16
164136154U, // VPADALuv4i32
164660442U, // VPADALuv8i16
165184730U, // VPADALuv8i8
767558881U, // VPADDLsv16i8
766510305U, // VPADDLsv2i32
767034593U, // VPADDLsv4i16
766510305U, // VPADDLsv4i32
767034593U, // VPADDLsv8i16
767558881U, // VPADDLsv8i8
769131745U, // VPADDLuv16i8
768083169U, // VPADDLuv2i32
768607457U, // VPADDLuv4i16
768083169U, // VPADDLuv4i32
768607457U, // VPADDLuv8i16
769131745U, // VPADDLuv8i8
152143080U, // VPADDf
166724840U, // VPADDi16
166200552U, // VPADDi32
167249128U, // VPADDi8
152143086U, // VPMAXf
163054830U, // VPMAXs16
162530542U, // VPMAXs32
163579118U, // VPMAXs8
164627694U, // VPMAXu16
164103406U, // VPMAXu32
165151982U, // VPMAXu8
152143092U, // VPMINf
163054836U, // VPMINs16
162530548U, // VPMINs32
163579124U, // VPMINs8
164627700U, // VPMINu16
164103412U, // VPMINu32
165151988U, // VPMINu8
767558906U, // VQABSv16i8
766510330U, // VQABSv2i32
767034618U, // VQABSv4i16
766510330U, // VQABSv4i32
767034618U, // VQABSv8i16
767558906U, // VQABSv8i8
163579136U, // VQADDsv16i8
177210624U, // VQADDsv1i64
162530560U, // VQADDsv2i32
177210624U, // VQADDsv2i64
163054848U, // VQADDsv4i16
162530560U, // VQADDsv4i32
163054848U, // VQADDsv8i16
163579136U, // VQADDsv8i8
165152000U, // VQADDuv16i8
177734912U, // VQADDuv1i64
164103424U, // VQADDuv2i32
177734912U, // VQADDuv2i64
164627712U, // VQADDuv4i16
164103424U, // VQADDuv4i32
164627712U, // VQADDuv8i16
165152000U, // VQADDuv8i8
229672198U, // VQDMLALslv2i32
230196486U, // VQDMLALslv4i16
833651974U, // VQDMLALv2i64
834176262U, // VQDMLALv4i32
229672206U, // VQDMLSLslv2i32
230196494U, // VQDMLSLslv4i16
833651982U, // VQDMLSLv2i64
834176270U, // VQDMLSLv4i32
833619222U, // VQDMULHslv2i32
834143510U, // VQDMULHslv4i16
833619222U, // VQDMULHslv4i32
834143510U, // VQDMULHslv8i16
162530582U, // VQDMULHv2i32
163054870U, // VQDMULHv4i16
162530582U, // VQDMULHv4i32
163054870U, // VQDMULHv8i16
833619230U, // VQDMULLslv2i32
834143518U, // VQDMULLslv4i16
162530590U, // VQDMULLv2i64
163054878U, // VQDMULLv4i32
781190438U, // VQMOVNsuv2i32
766510374U, // VQMOVNsuv4i16
767034662U, // VQMOVNsuv8i8
781190446U, // VQMOVNsv2i32
766510382U, // VQMOVNsv4i16
767034670U, // VQMOVNsv8i8
781714734U, // VQMOVNuv2i32
768083246U, // VQMOVNuv4i16
768607534U, // VQMOVNuv8i8
767558965U, // VQNEGv16i8
766510389U, // VQNEGv2i32
767034677U, // VQNEGv4i16
766510389U, // VQNEGv4i32
767034677U, // VQNEGv8i16
767558965U, // VQNEGv8i8
833619259U, // VQRDMULHslv2i32
834143547U, // VQRDMULHslv4i16
833619259U, // VQRDMULHslv4i32
834143547U, // VQRDMULHslv8i16
162530619U, // VQRDMULHv2i32
163054907U, // VQRDMULHv4i16
162530619U, // VQRDMULHv4i32
163054907U, // VQRDMULHv8i16
163579204U, // VQRSHLsv16i8
177210692U, // VQRSHLsv1i64
162530628U, // VQRSHLsv2i32
177210692U, // VQRSHLsv2i64
163054916U, // VQRSHLsv4i16
162530628U, // VQRSHLsv4i32
163054916U, // VQRSHLsv8i16
163579204U, // VQRSHLsv8i8
165152068U, // VQRSHLuv16i8
177734980U, // VQRSHLuv1i64
164103492U, // VQRSHLuv2i32
177734980U, // VQRSHLuv2i64
164627780U, // VQRSHLuv4i16
164103492U, // VQRSHLuv4i32
164627780U, // VQRSHLuv8i16
165152068U, // VQRSHLuv8i8
177210699U, // VQRSHRNsv2i32
162530635U, // VQRSHRNsv4i16
163054923U, // VQRSHRNsv8i8
177734987U, // VQRSHRNuv2i32
164103499U, // VQRSHRNuv4i16
164627787U, // VQRSHRNuv8i8
177210707U, // VQRSHRUNv2i32
162530643U, // VQRSHRUNv4i16
163054931U, // VQRSHRUNv8i8
163579228U, // VQSHLsiv16i8
177210716U, // VQSHLsiv1i64
162530652U, // VQSHLsiv2i32
177210716U, // VQSHLsiv2i64
163054940U, // VQSHLsiv4i16
162530652U, // VQSHLsiv4i32
163054940U, // VQSHLsiv8i16
163579228U, // VQSHLsiv8i8
163579234U, // VQSHLsuv16i8
177210722U, // VQSHLsuv1i64
162530658U, // VQSHLsuv2i32
177210722U, // VQSHLsuv2i64
163054946U, // VQSHLsuv4i16
162530658U, // VQSHLsuv4i32
163054946U, // VQSHLsuv8i16
163579234U, // VQSHLsuv8i8
163579228U, // VQSHLsv16i8
177210716U, // VQSHLsv1i64
162530652U, // VQSHLsv2i32
177210716U, // VQSHLsv2i64
163054940U, // VQSHLsv4i16
162530652U, // VQSHLsv4i32
163054940U, // VQSHLsv8i16
163579228U, // VQSHLsv8i8
165152092U, // VQSHLuiv16i8
177735004U, // VQSHLuiv1i64
164103516U, // VQSHLuiv2i32
177735004U, // VQSHLuiv2i64
164627804U, // VQSHLuiv4i16
164103516U, // VQSHLuiv4i32
164627804U, // VQSHLuiv8i16
165152092U, // VQSHLuiv8i8
165152092U, // VQSHLuv16i8
177735004U, // VQSHLuv1i64
164103516U, // VQSHLuv2i32
177735004U, // VQSHLuv2i64
164627804U, // VQSHLuv4i16
164103516U, // VQSHLuv4i32
164627804U, // VQSHLuv8i16
165152092U, // VQSHLuv8i8
177210729U, // VQSHRNsv2i32
162530665U, // VQSHRNsv4i16
163054953U, // VQSHRNsv8i8
177735017U, // VQSHRNuv2i32
164103529U, // VQSHRNuv4i16
164627817U, // VQSHRNuv8i8
177210736U, // VQSHRUNv2i32
162530672U, // VQSHRUNv4i16
163054960U, // VQSHRUNv8i8
163579256U, // VQSUBsv16i8
177210744U, // VQSUBsv1i64
162530680U, // VQSUBsv2i32
177210744U, // VQSUBsv2i64
163054968U, // VQSUBsv4i16
162530680U, // VQSUBsv4i32
163054968U, // VQSUBsv8i16
163579256U, // VQSUBsv8i8
165152120U, // VQSUBuv16i8
177735032U, // VQSUBuv1i64
164103544U, // VQSUBuv2i32
177735032U, // VQSUBuv2i64
164627832U, // VQSUBuv4i16
164103544U, // VQSUBuv4i32
164627832U, // VQSUBuv8i16
165152120U, // VQSUBuv8i8
165676414U, // VRADDHNv2i32
166200702U, // VRADDHNv4i16
166724990U, // VRADDHNv8i8
768083334U, // VRECPEd
756123014U, // VRECPEfd
756123014U, // VRECPEfq
768083334U, // VRECPEq
152143245U, // VRECPSfd
152143245U, // VRECPSfq
771802516U, // VREV16d8
771802516U, // VREV16q8
776521115U, // VREV32d16
771802523U, // VREV32d8
776521115U, // VREV32q16
771802523U, // VREV32q8
776521122U, // VREV64d16
777045410U, // VREV64d32
771802530U, // VREV64d8
777045410U, // VREV64df
776521122U, // VREV64q16
777045410U, // VREV64q32
771802530U, // VREV64q8
777045410U, // VREV64qf
163579305U, // VRHADDsv16i8
162530729U, // VRHADDsv2i32
163055017U, // VRHADDsv4i16
162530729U, // VRHADDsv4i32
163055017U, // VRHADDsv8i16
163579305U, // VRHADDsv8i8
165152169U, // VRHADDuv16i8
164103593U, // VRHADDuv2i32
164627881U, // VRHADDuv4i16
164103593U, // VRHADDuv4i32
164627881U, // VRHADDuv8i16
165152169U, // VRHADDuv8i8
163579312U, // VRSHLsv16i8
177210800U, // VRSHLsv1i64
162530736U, // VRSHLsv2i32
177210800U, // VRSHLsv2i64
163055024U, // VRSHLsv4i16
162530736U, // VRSHLsv4i32
163055024U, // VRSHLsv8i16
163579312U, // VRSHLsv8i8
165152176U, // VRSHLuv16i8
177735088U, // VRSHLuv1i64
164103600U, // VRSHLuv2i32
177735088U, // VRSHLuv2i64
164627888U, // VRSHLuv4i16
164103600U, // VRSHLuv4i32
164627888U, // VRSHLuv8i16
165152176U, // VRSHLuv8i8
165676470U, // VRSHRNv2i32
166200758U, // VRSHRNv4i16
166725046U, // VRSHRNv8i8
163579325U, // VRSHRsv16i8
177210813U, // VRSHRsv1i64
162530749U, // VRSHRsv2i32
177210813U, // VRSHRsv2i64
163055037U, // VRSHRsv4i16
162530749U, // VRSHRsv4i32
163055037U, // VRSHRsv8i16
163579325U, // VRSHRsv8i8
165152189U, // VRSHRuv16i8
177735101U, // VRSHRuv1i64
164103613U, // VRSHRuv2i32
177735101U, // VRSHRuv2i64
164627901U, // VRSHRuv4i16
164103613U, // VRSHRuv4i32
164627901U, // VRSHRuv8i16
165152189U, // VRSHRuv8i8
768083395U, // VRSQRTEd
756123075U, // VRSQRTEfd
756123075U, // VRSQRTEfq
768083395U, // VRSQRTEq
152143307U, // VRSQRTSfd
152143307U, // VRSQRTSfq
834700755U, // VRSRAsv16i8
848332243U, // VRSRAsv1i64
833652179U, // VRSRAsv2i32
848332243U, // VRSRAsv2i64
834176467U, // VRSRAsv4i16
833652179U, // VRSRAsv4i32
834176467U, // VRSRAsv8i16
834700755U, // VRSRAsv8i8
836273619U, // VRSRAuv16i8
848856531U, // VRSRAuv1i64
835225043U, // VRSRAuv2i32
848856531U, // VRSRAuv2i64
835749331U, // VRSRAuv4i16
835225043U, // VRSRAuv4i32
835749331U, // VRSRAuv8i16
836273619U, // VRSRAuv8i8
165676505U, // VRSUBHNv2i32
166200793U, // VRSUBHNv4i16
166725081U, // VRSUBHNv8i8
843628736U, // VSETLNi16
844153024U, // VSETLNi32
838910144U, // VSETLNi8
166725089U, // VSHLLi16
166200801U, // VSHLLi32
167249377U, // VSHLLi8
162530785U, // VSHLLsv2i64
163055073U, // VSHLLsv4i32
163579361U, // VSHLLsv8i16
164103649U, // VSHLLuv2i64
164627937U, // VSHLLuv4i32
165152225U, // VSHLLuv8i16
167249383U, // VSHLiv16i8
165676519U, // VSHLiv1i64
166200807U, // VSHLiv2i32
165676519U, // VSHLiv2i64
166725095U, // VSHLiv4i16
166200807U, // VSHLiv4i32
166725095U, // VSHLiv8i16
167249383U, // VSHLiv8i8
163579367U, // VSHLsv16i8
177210855U, // VSHLsv1i64
162530791U, // VSHLsv2i32
177210855U, // VSHLsv2i64
163055079U, // VSHLsv4i16
162530791U, // VSHLsv4i32
163055079U, // VSHLsv8i16
163579367U, // VSHLsv8i8
165152231U, // VSHLuv16i8
177735143U, // VSHLuv1i64
164103655U, // VSHLuv2i32
177735143U, // VSHLuv2i64
164627943U, // VSHLuv4i16
164103655U, // VSHLuv4i32
164627943U, // VSHLuv8i16
165152231U, // VSHLuv8i8
165676524U, // VSHRNv2i32
166200812U, // VSHRNv4i16
166725100U, // VSHRNv8i8
163579378U, // VSHRsv16i8
177210866U, // VSHRsv1i64
162530802U, // VSHRsv2i32
177210866U, // VSHRsv2i64
163055090U, // VSHRsv4i16
162530802U, // VSHRsv4i32
163055090U, // VSHRsv8i16
163579378U, // VSHRsv8i8
165152242U, // VSHRuv16i8
177735154U, // VSHRuv1i64
164103666U, // VSHRuv2i32
177735154U, // VSHRuv2i64
164627954U, // VSHRuv4i16
164103666U, // VSHRuv4i32
164627954U, // VSHRuv8i16
165152242U, // VSHRuv8i8
178258984U, // VSHTOD
178783272U, // VSHTOS
783467560U, // VSITOD
775603240U, // VSITOS
838911479U, // VSLIv16i8
846775799U, // VSLIv1i64
844154359U, // VSLIv2i32
846775799U, // VSLIv2i64
843630071U, // VSLIv4i16
844154359U, // VSLIv4i32
843630071U, // VSLIv8i16
838911479U, // VSLIv8i8
179405864U, // VSLTOD
171541544U, // VSLTOS
755598844U, // VSQRTD
756123132U, // VSQRTS
834700802U, // VSRAsv16i8
848332290U, // VSRAsv1i64
833652226U, // VSRAsv2i32
848332290U, // VSRAsv2i64
834176514U, // VSRAsv4i16
833652226U, // VSRAsv4i32
834176514U, // VSRAsv8i16
834700802U, // VSRAsv8i8
836273666U, // VSRAuv16i8
848856578U, // VSRAuv1i64
835225090U, // VSRAuv2i32
848856578U, // VSRAuv2i64
835749378U, // VSRAuv4i16
835225090U, // VSRAuv4i32
835749378U, // VSRAuv8i16
836273666U, // VSRAuv8i8
838911495U, // VSRIv16i8
846775815U, // VSRIv1i64
844154375U, // VSRIv2i32
846775815U, // VSRIv2i64
843630087U, // VSRIv4i16
844154375U, // VSRIv4i32
843630087U, // VSRIv8i16
838911495U, // VSRIv8i8
240944652U, // VST1d16
241468940U, // VST1d32
241993228U, // VST1d64
242517516U, // VST1d8
241468940U, // VST1df
239912460U, // VST1q16
240436748U, // VST1q32
243058188U, // VST1q64
235193868U, // VST1q8
240436748U, // VST1qf
1516013073U, // VST2LNd16
1516537361U, // VST2LNd32
1517585937U, // VST2LNd8
1516013073U, // VST2LNq16a
1516013073U, // VST2LNq16b
1516537361U, // VST2LNq32a
1516537361U, // VST2LNq32b
643597841U, // VST2d16
644122129U, // VST2d32
644646412U, // VST2d64
645170705U, // VST2d8
1381795345U, // VST2q16
1382319633U, // VST2q32
1383368209U, // VST2q8
1381795350U, // VST3LNd16
1382319638U, // VST3LNd32
1383368214U, // VST3LNd8
1381795350U, // VST3LNq16a
1381795350U, // VST3LNq16b
1382319638U, // VST3LNq32a
1382319638U, // VST3LNq32b
1516013078U, // VST3d16
1516537366U, // VST3d32
1517061644U, // VST3d64
1517585942U, // VST3d8
1381828118U, // VST3q16a
1381828118U, // VST3q16b
1382352406U, // VST3q32a
1382352406U, // VST3q32b
1383400982U, // VST3q8a
1383400982U, // VST3q8b
1314686491U, // VST4LNd16
1315210779U, // VST4LNd32
1316259355U, // VST4LNd8
1314686491U, // VST4LNq16a
1314686491U, // VST4LNq16b
1315210779U, // VST4LNq32a
1315210779U, // VST4LNq32b
1381795355U, // VST4d16
1382319643U, // VST4d32
1382843916U, // VST4d64
1383368219U, // VST4d8
1314719259U, // VST4q16a
1314719259U, // VST4q16b
1315243547U, // VST4q32a
1315243547U, // VST4q32b
1316292123U, // VST4q8a
1316292123U, // VST4q8b
1610614304U, // VSTMD
1610614304U, // VSTMS
175687205U, // VSTRD
136005162U, // VSTRQ
173065765U, // VSTRS
151619121U, // VSUBD
165676598U, // VSUBHNv2i32
166200886U, // VSUBHNv4i16
166725174U, // VSUBHNv8i8
162530877U, // VSUBLsv2i64
163055165U, // VSUBLsv4i32
163579453U, // VSUBLsv8i16
164103741U, // VSUBLuv2i64
164628029U, // VSUBLuv4i32
165152317U, // VSUBLuv8i16
152143409U, // VSUBS
162530883U, // VSUBWsv2i64
163055171U, // VSUBWsv4i32
163579459U, // VSUBWsv8i16
164103747U, // VSUBWuv2i64
164628035U, // VSUBWuv4i32
165152323U, // VSUBWuv8i16
152143409U, // VSUBfd
152143409U, // VSUBfd_sfp
152143409U, // VSUBfq
167249457U, // VSUBv16i8
165676593U, // VSUBv1i64
166200881U, // VSUBv2i32
165676593U, // VSUBv2i64
166725169U, // VSUBv4i16
166200881U, // VSUBv4i32
166725169U, // VSUBv8i16
167249457U, // VSUBv8i8
167822921U, // VTBL1
838911561U, // VTBL2
234931785U, // VTBL3
637584969U, // VTBL4
838911566U, // VTBX1
234931790U, // VTBX2
637584974U, // VTBX3
1510000206U, // VTBX4
179831848U, // VTOSHD
180356136U, // VTOSHS
785040979U, // VTOSIRD
774555219U, // VTOSIRS
785040424U, // VTOSIZD
774554664U, // VTOSIZS
180978728U, // VTOSLD
170492968U, // VTOSLS
181404712U, // VTOUHD
181929000U, // VTOUHS
786613843U, // VTOUIRD
775079507U, // VTOUIRS
786613288U, // VTOUIZD
775078952U, // VTOUIZS
182551592U, // VTOULD
171017256U, // VTOULS
843630169U, // VTRNd16
844154457U, // VTRNd32
838911577U, // VTRNd8
843630169U, // VTRNq16
844154457U, // VTRNq32
838911577U, // VTRNq8
167822942U, // VTSTv16i8
173065822U, // VTSTv2i32
172541534U, // VTSTv4i16
173065822U, // VTSTv4i32
172541534U, // VTSTv8i16
167822942U, // VTSTv8i8
182977576U, // VUHTOD
183501864U, // VUHTOS
788186152U, // VUITOD
776127528U, // VUITOS
184124456U, // VULTOD
172065832U, // VULTOS
843630179U, // VUZPd16
844154467U, // VUZPd32
838911587U, // VUZPd8
843630179U, // VUZPq16
844154467U, // VUZPq32
838911587U, // VUZPq8
843630184U, // VZIPd16
844154472U, // VZIPd32
838911592U, // VZIPd8
843630184U, // VZIPq16
844154472U, // VZIPq32
838911592U, // VZIPq8
538969709U, // WFE
538969713U, // WFI
538969717U, // YIELD
67108875U, // t2ADCSri
67110523U, // t2ADCSrr
67110523U, // t2ADCSrs
1679343633U, // t2ADCri
1728151569U, // t2ADCrr
1795260433U, // t2ADCrs
184647701U, // t2ADDSri
184647701U, // t2ADDSrr
855736341U, // t2ADDSrs
1728151578U, // t2ADDrSPi
135841411U, // t2ADDrSPi12
1795260442U, // t2ADDrSPs
1728151578U, // t2ADDri
1679345283U, // t2ADDri12
1728151578U, // t2ADDrr
1795260442U, // t2ADDrs
1679343684U, // t2ANDri
1728151620U, // t2ANDrr
1795260484U, // t2ANDrs
1728153224U, // t2ASRri
1728153224U, // t2ASRrr
69207692U, // t2B
135839820U, // t2BFC
806930065U, // t2BFI
1679343696U, // t2BICri
1728151632U, // t2BICrr
1795260496U, // t2BICrs
117964923U, // t2BR_JT
386056347U, // t2Bcc
739819688U, // t2CLZ
788627628U, // t2CMNzri
788627628U, // t2CMNzrr
184647852U, // t2CMNzrs
788627632U, // t2CMPri
788627632U, // t2CMPrr
184647856U, // t2CMPrs
788627632U, // t2CMPzri
788627632U, // t2CMPzrr
184647856U, // t2CMPzrs
1679343804U, // t2EORri
1728151740U, // t2EORrr
1795260604U, // t2EORrs
1811941013U, // t2IT
215U, // t2Int_MemBarrierV7
219U, // t2Int_SyncBarrierV7
1879049880U, // t2Int_eh_sjlj_setjmp
1058013417U, // t2LDM
1058013417U, // t2LDM_RET
806928625U, // t2LDRB_POST
806928625U, // t2LDRB_PRE
184647921U, // t2LDRBi12
135839985U, // t2LDRBi8
788627697U, // t2LDRBpci
855736561U, // t2LDRBs
806928630U, // t2LDRDi8
135839990U, // t2LDRDpci
739819771U, // t2LDREX
739819777U, // t2LDREXB
135840008U, // t2LDREXD
739819791U, // t2LDREXH
806928662U, // t2LDRH_POST
806928662U, // t2LDRH_PRE
184647958U, // t2LDRHi12
135840022U, // t2LDRHi8
788627734U, // t2LDRHpci
855736598U, // t2LDRHs
806928667U, // t2LDRSB_POST
806928667U, // t2LDRSB_PRE
184647963U, // t2LDRSBi12
135840027U, // t2LDRSBi8
788627739U, // t2LDRSBpci
855736603U, // t2LDRSBs
806928673U, // t2LDRSH_POST
806928673U, // t2LDRSH_PRE
184647969U, // t2LDRSHi12
135840033U, // t2LDRSHi8
788627745U, // t2LDRSHpci
855736609U, // t2LDRSHs
806928621U, // t2LDR_POST
806928621U, // t2LDR_PRE
184647917U, // t2LDRi12
135839981U, // t2LDRi8
788627693U, // t2LDRpci
67110557U, // t2LDRpci_pic
855736557U, // t2LDRs
788874918U, // t2LEApcrel
184895142U, // t2LEApcrelJT
1728153258U, // t2LSLri
1728153258U, // t2LSLrr
1728153262U, // t2LSRri
1728153262U, // t2LSRrr
806928714U, // t2MLA
806928718U, // t2MLS
855737992U, // t2MOVCCasr
184648018U, // t2MOVCCi
855738026U, // t2MOVCClsl
855738030U, // t2MOVCClsr
184648018U, // t2MOVCCr
855738034U, // t2MOVCCror
135840086U, // t2MOVTi16
1998422354U, // t2MOVi
739819867U, // t2MOVi16
739819867U, // t2MOVi32imm
1998422354U, // t2MOVr
1998440118U, // t2MOVrx
67110586U, // t2MOVsra_flag
67110594U, // t2MOVsrl_flag
135840129U, // t2MUL
1998438789U, // t2MVNi
788627845U, // t2MVNr
184648069U, // t2MVNs
1679345354U, // t2ORNri
1679345354U, // t2ORNrr
1746454218U, // t2ORNrs
1679344013U, // t2ORRri
1728151949U, // t2ORRrr
1795260813U, // t2ORRrs
806928787U, // t2PKHBT
806928793U, // t2PKHTB
739819993U, // t2RBIT
788627934U, // t2REV
788627938U, // t2REV16
788627944U, // t2REVSH
1728153266U, // t2RORri
1728153266U, // t2RORrr
2013266419U, // t2RSBSri
1947779571U, // t2RSBSrs
184648179U, // t2RSBri
806928883U, // t2RSBrs
67109377U, // t2SBCSri
67110606U, // t2SBCSrr
67110606U, // t2SBCSrs
1679344135U, // t2SBCri
1728152071U, // t2SBCrr
1795260935U, // t2SBCrs
806928907U, // t2SBFX
806928936U, // t2SMLABB
806928943U, // t2SMLABT
806928950U, // t2SMLAL
806928988U, // t2SMLATB
806928995U, // t2SMLATT
806929002U, // t2SMLAWB
806929009U, // t2SMLAWT
806929016U, // t2SMMLA
806929022U, // t2SMMLS
135840388U, // t2SMMUL
135840394U, // t2SMULBB
135840401U, // t2SMULBT
806929048U, // t2SMULL
135840414U, // t2SMULTB
135840421U, // t2SMULTT
135840428U, // t2SMULWB
135840435U, // t2SMULWT
1058013882U, // t2STM
806879938U, // t2STRB_POST
806879938U, // t2STRB_PRE
184648386U, // t2STRBi12
135840450U, // t2STRBi8
855737026U, // t2STRBs
806929101U, // t2STRDi8
135840466U, // t2STREX
135840472U, // t2STREXB
806929119U, // t2STREXD
135840486U, // t2STREXH
806879981U, // t2STRH_POST
806879981U, // t2STRH_PRE
184648429U, // t2STRHi12
135840493U, // t2STRHi8
855737069U, // t2STRHs
806879934U, // t2STR_POST
806879934U, // t2STR_PRE
184648382U, // t2STRi12
135840446U, // t2STRi8
855737022U, // t2STRs
184648439U, // t2SUBSri
184648439U, // t2SUBSrr
855737079U, // t2SUBSrs
1728152316U, // t2SUBrSPi
135841494U, // t2SUBrSPi12
67110619U, // t2SUBrSPi12_
67110627U, // t2SUBrSPi_
1746453244U, // t2SUBrSPs
67110636U, // t2SUBrSPs_
1728152316U, // t2SUBri
1679345366U, // t2SUBri12
1728152316U, // t2SUBrr
1795261180U, // t2SUBrs
135840525U, // t2SXTABrr
806929165U, // t2SXTABrr_rot
135840531U, // t2SXTAHrr
806929171U, // t2SXTAHrr_rot
788628249U, // t2SXTBr
184648473U, // t2SXTBr_rot
788628254U, // t2SXTHr
184648478U, // t2SXTHr_rot
2080376563U, // t2TBB
2080376568U, // t2TBH
788628259U, // t2TEQri
788628259U, // t2TEQrr
184648483U, // t2TEQrs
807U, // t2TPsoft
788628287U, // t2TSTri
788628287U, // t2TSTrr
184648511U, // t2TSTrs
806929219U, // t2UBFX
806929224U, // t2UMAAL
806929230U, // t2UMLAL
806929236U, // t2UMULL
135840644U, // t2UXTABrr
806929284U, // t2UXTABrr_rot
135840650U, // t2UXTAHrr
806929290U, // t2UXTAHrr_rot
788628368U, // t2UXTB16r
184648592U, // t2UXTB16r_rot
788628375U, // t2UXTBr
184648599U, // t2UXTBr_rot
788628380U, // t2UXTHr
184648604U, // t2UXTHr_rot
2200305681U, // tADC
135839770U, // tADDhirr
2199945242U, // tADDi3
2200305690U, // tADDi8
120063741U, // tADDrPCi
67143421U, // tADDrSP
67110653U, // tADDrSPi
2199945242U, // tADDrr
67520253U, // tADDspi
67143421U, // tADDspr
67143426U, // tADDspr_
69207817U, // tADJCALLSTACKDOWN
69207838U, // tADJCALLSTACKUP
2200305732U, // tAND
67143473U, // tANDsp
2199946888U, // tASRri
2200307336U, // tASRrr
69206089U, // tB
2200305744U, // tBIC
69207864U, // tBKPT
402653273U, // tBL
402653277U, // tBLXi
402653277U, // tBLXi_r9
69206109U, // tBLXr
69206109U, // tBLXr_r9
402653273U, // tBLr9
69206139U, // tBRIND
120586363U, // tBR_JTr
69206148U, // tBX
1854U, // tBX_RET
69206117U, // tBX_RET_vararg
69206148U, // tBXr9
337166491U, // tBcc
121110617U, // tBfar
67110724U, // tCBNZ
67110730U, // tCBZ
739819692U, // tCMNz
739819696U, // tCMPhir
739819696U, // tCMPi8
739819696U, // tCMPr
739819696U, // tCMPzhir
739819696U, // tCMPzi8
739819696U, // tCMPzr
2200305852U, // tEOR
1879049880U, // tInt_eh_sjlj_setjmp
1008320745U, // tLDM
806928621U, // tLDR
806928625U, // tLDRB
806928625U, // tLDRBi
806928662U, // tLDRH
806928662U, // tLDRHi
135840027U, // tLDRSB
135840033U, // tLDRSH
739819757U, // tLDRcp
806928621U, // tLDRi
792723693U, // tLDRpci
67110735U, // tLDRpci_pic
135839981U, // tLDRspi
739821222U, // tLEApcrel
135841446U, // tLEApcrelJT
2199946922U, // tLSLri
2200307370U, // tLSLrr
2199946926U, // tLSRri
2200307374U, // tLSRrr
135840082U, // tMOVCCi
135840082U, // tMOVCCr
136316760U, // tMOVCCr_pseudo
67110755U, // tMOVSr
67110761U, // tMOVgpr2gpr
67110761U, // tMOVgpr2tgpr
2202714450U, // tMOVi8
67110761U, // tMOVr
67110761U, // tMOVtgpr2gpr
2200306049U, // tMUL
2202714501U, // tMVN
2200306061U, // tORR
1196425617U, // tPICADD
538871662U, // tPOP
538871662U, // tPOP_RET
538871666U, // tPUSH
739819998U, // tREV
739820002U, // tREV16
739820008U, // tREVSH
2200307378U, // tROR
2202698227U, // tRSB
135839981U, // tRestore
2200306183U, // tSBC
1008321210U, // tSTM
806929086U, // tSTR
806929090U, // tSTRB
806929090U, // tSTRBi
806929133U, // tSTRH
806929133U, // tSTRHi
806929086U, // tSTRi
135840446U, // tSTRspi
2199945980U, // tSUBi3
2200306428U, // tSUBi8
2199945980U, // tSUBrr
67520375U, // tSUBspi
67520236U, // tSUBspi_
739820313U, // tSXTB
739820318U, // tSXTH
135840446U, // tSpill
807U, // tTPsoft
739820351U, // tTST
739820439U, // tUXTB
739820444U, // tUXTH
0U
};
const char *AsmStrs =
"DBG_VALUE\000adcs\t\000adc\000adds\000add\000@ ADJCALLSTACKDOWN \000@ A"
"DJCALLSTACKUP \000and\000\000b\t\000bfc\000bic\000bkpt\000bl\t\000blx\t"
"\000bl\000bx\t\000add\tpc, \000ldr\tpc, \000mov\tpc, \000mov\tlr, pc\n\t"
"bx\t\000bxj\000bx\000b\000cdp\000cdp2\tp\000clz\000cmn\000cmp\000cps\000"
"dbg\000eor\000vmov\000vmrs\000mcr\tp15, 0, \000dmb\000dsb\000str\tsp, ["
"\000ldm\000ldr\000ldrb\000ldrd\000ldrex\000ldrexb\000ldrexd\000ldrexh\000"
"ldrh\000ldrsb\000ldrsh\000ldrt\000.set \000mcr\000mcr2\tp\000mcrr\000mc"
"rr2\tp\000mla\000mls\000mov\000movt\000movw\000movs\000mrc\000mrc2\tp\000"
"mrrc\000mrrc2\tp\000mrs\000mul\000mvn\000nop\000orr\000\n\000pkhbt\000p"
"khtb\000qadd\000qadd16\000qadd8\000qasx\000qdadd\000qdsub\000qsax\000qs"
"ub\000qsub16\000qsub8\000rbit\000rev\000rev16\000revsh\000rsbs\000rsb\000"
"rscs\t\000rsc\000sbcs\t\000sbc\000sbfx\000setend\tbe\000setend\tle\000s"
"ev\000smlabb\000smlabt\000smlal\000smlalbb\000smlalbt\000smlaltb\000sml"
"altt\000smlatb\000smlatt\000smlawb\000smlawt\000smmla\000smmls\000smmul"
"\000smulbb\000smulbt\000smull\000smultb\000smultt\000smulwb\000smulwt\000"
"stm\000str\000strb\000strbt\000strd\000strex\000strexb\000strexd\000str"
"exh\000strh\000strt\000subs\000sub\000svc\000swp\000swpb\000sxtab\000sx"
"tah\000sxtb\000sxth\000teq\000bl\t__aeabi_read_tp\000trap\000tst\000ubf"
"x\000umaal\000umlal\000umull\000uqadd16\000uqadd8\000uqasx\000uqsax\000"
"uqsub16\000uqsub8\000uxtab\000uxtah\000uxtb16\000uxtb\000uxth\000vabal\000"
"vaba\000vabdl\000vabd\000vabs\000vacge\000vacgt\000vadd\000vaddhn\000va"
"ddl\000vaddw\000vand\000vbic\000vbif\000vbit\000vbsl\000vceq\000vcge\000"
"vcgt\000vcls\000vclz\000vcmp\000vcmpe\000vcnt\000vcvtb\000vcvt\000vcvtt"
"\000vdiv\000vdup\000veor\000vext\000vhadd\000vhsub\000vld1\000vld2\000v"
"ld3\000vld4\000vldm\000vldr\000vldmia\000vmax\000vmin\000vmla\000vmlal\000"
"vmls\000vmlsl\000vmovl\000vmovn\000vmsr\000vmul\000vmull\000vmvn\000vne"
"g\000vnmla\000vnmls\000vnmul\000vorn\000vorr\000vpadal\000vpaddl\000vpa"
"dd\000vpmax\000vpmin\000vqabs\000vqadd\000vqdmlal\000vqdmlsl\000vqdmulh"
"\000vqdmull\000vqmovun\000vqmovn\000vqneg\000vqrdmulh\000vqrshl\000vqrs"
"hrn\000vqrshrun\000vqshl\000vqshlu\000vqshrn\000vqshrun\000vqsub\000vra"
"ddhn\000vrecpe\000vrecps\000vrev16\000vrev32\000vrev64\000vrhadd\000vrs"
"hl\000vrshrn\000vrshr\000vrsqrte\000vrsqrts\000vrsra\000vrsubhn\000vshl"
"l\000vshl\000vshrn\000vshr\000vsli\000vsqrt\000vsra\000vsri\000vst1\000"
"vst2\000vst3\000vst4\000vstm\000vstr\000vstmia\000vsub\000vsubhn\000vsu"
"bl\000vsubw\000vtbl\000vtbx\000vcvtr\000vtrn\000vtst\000vuzp\000vzip\000"
"wfe\000wfi\000yield\000adcs.w\t\000addw\000asr\000b.w\t\000bfi\000it\000"
"str\t\000@ ldr.w\t\000adr\000lsl\000lsr\000ror\000rrx\000asrs.w\t\000ls"
"rs.w\t\000orn\000sbcs.w\t\000subw\000@ subw\t\000@ sub.w\t\000@ sub\t\000"
"tbb\t\000tbh\t\000add\t\000@ add\t\000@ tADJCALLSTACKDOWN \000@ tADJCAL"
"LSTACKUP \000@ and\t\000bkpt\t\000bx\tlr\000cbnz\t\000cbz\t\000@ ldr.n\t"
"\000@ tMOVCCr \000movs\t\000mov\t\000pop\000push\000sub\t\000";
O << "\t";
// Emit the opcode for the instruction.
unsigned Bits = OpInfo[MI->getOpcode()];
assert(Bits != 0 && "Cannot print this instruction.");
O << AsmStrs+(Bits & 2047)-1;
// Fragment 0 encoded into 6 bits for 33 unique commands.
switch ((Bits >> 26) & 63) {
default: // unreachable.
case 0:
// DBG_VALUE, Int_MemBarrierV7, Int_SyncBarrierV7, SETENDBE, SETENDLE, TP...
return;
break;
case 1:
// ADCSSri, ADCSSrr, ADCSSrs, ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, B...
printOperand(MI, 0);
break;
case 2:
// ADCri, ADCrr, ADDSri, ADDSrr, ADDri, ADDrr, ANDri, ANDrr, BFC, BICri, ...
printPredicateOperand(MI, 3);
break;
case 3:
// ADCrs, ADDSrs, ADDrs, ANDrs, BICrs, EORrs, LDRBT, LDRB_POST, LDRB_PRE,...
printPredicateOperand(MI, 5);
break;
case 4:
// ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, ATOMIC_CMP_SWAP_I8, ATOMIC_L...
PrintSpecial(MI, "comment");
break;
case 5:
// BKPT, BL_pred, BLr9_pred, BXJ, Bcc, DBG, MRS, MRSsys, MSR, MSRsys, SVC...
printPredicateOperand(MI, 1);
break;
case 6:
// BL, BLr9, tBL, tBLXi, tBLXi_r9, tBLr9
printOperand(MI, 0, "call");
return;
break;
case 7:
// BR_JTm
printAddrMode2Operand(MI, 0);
O << " \n";
printJTBlockOperand(MI, 3);
return;
break;
case 8:
// BX_RET, FMSTAT, NOP, SEV, TRAP, WFE, WFI, YIELD, tPOP, tPOP_RET, tPUSH
printPredicateOperand(MI, 0);
break;
case 9:
// CDP, MCR, MRC, VLD2d16, VLD2d32, VLD2d64, VLD2d8, VST2d16, VST2d32, VS...
printPredicateOperand(MI, 6);
break;
case 10:
// CDP2, MCR2, MCRR2, MRC2, MRRC2
printNoHashImmediate(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 11:
// CLZ, CMNzri, CMNzrr, CMPri, CMPrr, CMPzri, CMPzrr, FCONSTD, FCONSTS, L...
printPredicateOperand(MI, 2);
break;
case 12:
// CMNzrs, CMPrs, CMPzrs, LDR, LDRB, LDRH, LDRSB, LDRSH, LDRcp, MLA, MLS,...
printPredicateOperand(MI, 4);
break;
case 13:
// CONSTPOOL_ENTRY
printCPInstOperand(MI, 0, "label");
O << ' ';
printCPInstOperand(MI, 1, "cpentry");
return;
break;
case 14:
// CPS
printOperand(MI, 0, "cps");
return;
break;
case 15:
// LDM, LDM_RET, STM, t2LDM, t2LDM_RET, t2STM, tLDM, tSTM
printAddrMode4Operand(MI, 0, "submode");
printPredicateOperand(MI, 2);
break;
case 16:
// LEApcrel, LEApcrelJT
PrintSpecial(MI, "private");
O << "PCRELV";
PrintSpecial(MI, "uid");
O << ", (";
printOperand(MI, 1);
break;
case 17:
// PICADD, tPICADD
printPCLabel(MI, 2);
break;
case 18:
// PICLDR, PICLDRB, PICLDRH, PICLDRSB, PICLDRSH, PICSTR, PICSTRB, PICSTRH
printAddrModePCOperand(MI, 1, "label");
break;
case 19:
// VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16a, VLD2LNq16b, VLD2LNq32a, VL...
printPredicateOperand(MI, 9);
break;
case 20:
// VLD2q16, VLD2q32, VLD2q8, VLD3q16a, VLD3q16b, VLD3q32a, VLD3q32b, VLD3...
printPredicateOperand(MI, 8);
break;
case 21:
// VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16a, VLD3LNq16b, VLD3LNq32a, VL...
printPredicateOperand(MI, 11);
break;
case 22:
// VLD3d16, VLD3d32, VLD3d64, VLD3d8, VST2LNd16, VST2LNd32, VST2LNd8, VST...
printPredicateOperand(MI, 7);
break;
case 23:
// VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16a, VLD4LNq16b, VLD4LNq32a, VL...
printPredicateOperand(MI, 13);
break;
case 24:
// VLDMD, VLDMS, VSTMD, VSTMS
printAddrMode5Operand(MI, 0, "submode");
printPredicateOperand(MI, 2);
O << "\t";
printAddrMode5Operand(MI, 0, "base");
O << ", ";
printRegisterList(MI, 4);
return;
break;
case 25:
// t2ADCri, t2ADCrr, t2ADDrSPi, t2ADDri, t2ADDri12, t2ADDrr, t2ANDri, t2A...
printSBitModifierOperand(MI, 5);
printPredicateOperand(MI, 3);
break;
case 26:
// t2ADCrs, t2ADDrSPs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORR...
printSBitModifierOperand(MI, 6);
printPredicateOperand(MI, 4);
break;
case 27:
// t2IT
printThumbITMask(MI, 1);
O << "\t";
printPredicateOperand(MI, 0);
return;
break;
case 28:
// t2Int_eh_sjlj_setjmp, tInt_eh_sjlj_setjmp
printOperand(MI, 1);
O << ", [";
printOperand(MI, 0);
O << ", #8]\t@ begin eh.setjmp\n\tmov\t";
printOperand(MI, 1);
O << ", pc\n\tadds\t";
printOperand(MI, 1);
O << ", #9\n\tstr\t";
printOperand(MI, 1);
O << ", [";
printOperand(MI, 0);
O << ", #4]\n\tmovs\tr0, #0\n\tb\t1f\n\tmovs\tr0, #1\t@ end eh.setjmp\n1:";
return;
break;
case 29:
// t2MOVi, t2MOVr, t2MOVrx, t2MVNi, t2RSBSrs
printSBitModifierOperand(MI, 4);
break;
case 30:
// t2RSBSri
printSBitModifierOperand(MI, 3);
O << ".w\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 31:
// t2TBB, t2TBH
printTBAddrMode(MI, 0);
O << "\n";
printJT2BlockOperand(MI, 1);
return;
break;
case 32:
// tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
printSBitModifierOperand(MI, 1);
break;
}
// Fragment 1 encoded into 7 bits for 107 unique commands.
switch ((Bits >> 19) & 127) {
default: // unreachable.
case 0:
// ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MCR2, MCRR2, MRC2, MRRC2, RSCSri,...
O << ", ";
break;
case 1:
// ADCri, ADCrr, ADDri, ADDrr, ANDri, ANDrr, BICri, BICrr, EORri, EORrr, ...
printSBitModifierOperand(MI, 5);
O << "\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
break;
case 2:
// ADCrs, ADDrs, ANDrs, BICrs, EORrs, ORRrs, RSBrs, RSCrs, SBCrs, SUBrs
printSBitModifierOperand(MI, 7);
O << "\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printSORegOperand(MI, 2);
return;
break;
case 3:
// ADDSri, ADDSrr, ADDSrs, BFC, BKPT, BL_pred, BLr9_pred, BXJ, Bcc, CLZ, ...
O << "\t";
break;
case 4:
// ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, BLXr9, BRIND, BX, BXr9, NOP,...
return;
break;
case 5:
// ATOMIC_CMP_SWAP_I16
O << " ATOMIC_CMP_SWAP_I16 PSEUDO!";
return;
break;
case 6:
// ATOMIC_CMP_SWAP_I32
O << " ATOMIC_CMP_SWAP_I32 PSEUDO!";
return;
break;
case 7:
// ATOMIC_CMP_SWAP_I8
O << " ATOMIC_CMP_SWAP_I8 PSEUDO!";
return;
break;
case 8:
// ATOMIC_LOAD_ADD_I16
O << " ATOMIC_LOAD_ADD_I16 PSEUDO!";
return;
break;
case 9:
// ATOMIC_LOAD_ADD_I32
O << " ATOMIC_LOAD_ADD_I32 PSEUDO!";
return;
break;
case 10:
// ATOMIC_LOAD_ADD_I8
O << " ATOMIC_LOAD_ADD_I8 PSEUDO!";
return;
break;
case 11:
// ATOMIC_LOAD_AND_I16
O << " ATOMIC_LOAD_AND_I16 PSEUDO!";
return;
break;
case 12:
// ATOMIC_LOAD_AND_I32
O << " ATOMIC_LOAD_AND_I32 PSEUDO!";
return;
break;
case 13:
// ATOMIC_LOAD_AND_I8
O << " ATOMIC_LOAD_AND_I8 PSEUDO!";
return;
break;
case 14:
// ATOMIC_LOAD_NAND_I16
O << " ATOMIC_LOAD_NAND_I16 PSEUDO!";
return;
break;
case 15:
// ATOMIC_LOAD_NAND_I32
O << " ATOMIC_LOAD_NAND_I32 PSEUDO!";
return;
break;
case 16:
// ATOMIC_LOAD_NAND_I8
O << " ATOMIC_LOAD_NAND_I8 PSEUDO!";
return;
break;
case 17:
// ATOMIC_LOAD_OR_I16
O << " ATOMIC_LOAD_OR_I16 PSEUDO!";
return;
break;
case 18:
// ATOMIC_LOAD_OR_I32
O << " ATOMIC_LOAD_OR_I32 PSEUDO!";
return;
break;
case 19:
// ATOMIC_LOAD_OR_I8
O << " ATOMIC_LOAD_OR_I8 PSEUDO!";
return;
break;
case 20:
// ATOMIC_LOAD_SUB_I16
O << " ATOMIC_LOAD_SUB_I16 PSEUDO!";
return;
break;
case 21:
// ATOMIC_LOAD_SUB_I32
O << " ATOMIC_LOAD_SUB_I32 PSEUDO!";
return;
break;
case 22:
// ATOMIC_LOAD_SUB_I8
O << " ATOMIC_LOAD_SUB_I8 PSEUDO!";
return;
break;
case 23:
// ATOMIC_LOAD_XOR_I16
O << " ATOMIC_LOAD_XOR_I16 PSEUDO!";
return;
break;
case 24:
// ATOMIC_LOAD_XOR_I32
O << " ATOMIC_LOAD_XOR_I32 PSEUDO!";
return;
break;
case 25:
// ATOMIC_LOAD_XOR_I8
O << " ATOMIC_LOAD_XOR_I8 PSEUDO!";
return;
break;
case 26:
// ATOMIC_SWAP_I16
O << " ATOMIC_SWAP_I16 PSEUDO!";
return;
break;
case 27:
// ATOMIC_SWAP_I32
O << " ATOMIC_SWAP_I32 PSEUDO!";
return;
break;
case 28:
// ATOMIC_SWAP_I8
O << " ATOMIC_SWAP_I8 PSEUDO!";
return;
break;
case 29:
// BR_JTr
O << " \n";
printJTBlockOperand(MI, 1);
return;
break;
case 30:
// BX_RET
O << "\tlr";
return;
break;
case 31:
// CDP, MCR, MCRR, MRC, MRRC
O << "\tp";
printNoHashImmediate(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 32:
// CDP2
O << ", cr";
printNoHashImmediate(MI, 2);
O << ", cr";
printNoHashImmediate(MI, 3);
O << ", cr";
printNoHashImmediate(MI, 4);
O << ", ";
printOperand(MI, 5);
return;
break;
case 33:
// FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VMLAD, V...
O << ".f64\t";
printOperand(MI, 0);
break;
case 34:
// FCONSTS, VABDfd, VABDfq, VABSS, VABSfd, VABSfd_sfp, VABSfq, VACGEd, VA...
O << ".f32\t";
printOperand(MI, 0);
break;
case 35:
// FMSTAT
O << "\tapsr_nzcv, fpscr";
return;
break;
case 36:
// Int_MemBarrierV6
O << ", c7, c10, 5";
return;
break;
case 37:
// Int_SyncBarrierV6
O << ", c7, c10, 4";
return;
break;
case 38:
// Int_eh_sjlj_setjmp
O << ", #+8] @ eh_setjmp begin\n\tadd\t";
printOperand(MI, 1);
O << ", pc, #8\n\tstr\t";
printOperand(MI, 1);
O << ", [";
printOperand(MI, 0);
O << ", #+4]\n\tmov\tr0, #0\n\tadd\tpc, pc, #0\n\tmov\tr0, #1 @ eh_setjmp end";
return;
break;
case 39:
// LEApcrel
O << "-(";
PrintSpecial(MI, "private");
O << "PCRELL";
PrintSpecial(MI, "uid");
O << "+8))\n";
PrintSpecial(MI, "private");
O << "PCRELL";
PrintSpecial(MI, "uid");
O << ":\n\tadd";
printPredicateOperand(MI, 2);
O << "\t";
printOperand(MI, 0);
O << ", pc, #";
PrintSpecial(MI, "private");
O << "PCRELV";
PrintSpecial(MI, "uid");
return;
break;
case 40:
// LEApcrelJT
O << '_';
printNoHashImmediate(MI, 2);
O << "-(";
PrintSpecial(MI, "private");
O << "PCRELL";
PrintSpecial(MI, "uid");
O << "+8))\n";
PrintSpecial(MI, "private");
O << "PCRELL";
PrintSpecial(MI, "uid");
O << ":\n\tadd";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", pc, #";
PrintSpecial(MI, "private");
O << "PCRELV";
PrintSpecial(MI, "uid");
return;
break;
case 41:
// MLA, MOVs, MVNs, SMLAL, SMULL, UMLAL, UMULL
printSBitModifierOperand(MI, 6);
O << "\t";
printOperand(MI, 0);
O << ", ";
break;
case 42:
// MOVi, MOVr, MOVrx, MVNi, MVNr
printSBitModifierOperand(MI, 4);
O << "\t";
printOperand(MI, 0);
O << ", ";
break;
case 43:
// MSR
O << "\tcpsr, ";
printOperand(MI, 0);
return;
break;
case 44:
// MSRsys
O << "\tspsr, ";
printOperand(MI, 0);
return;
break;
case 45:
// PICADD
O << ":\n\tadd";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", pc, ";
printOperand(MI, 1);
return;
break;
case 46:
// PICLDR
O << ":\n\tldr";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 47:
// PICLDRB
O << ":\n\tldrb";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 48:
// PICLDRH
O << ":\n\tldrh";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 49:
// PICLDRSB
O << ":\n\tldrsb";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 50:
// PICLDRSH
O << ":\n\tldrsh";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 51:
// PICSTR
O << ":\n\tstr";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 52:
// PICSTRB
O << ":\n\tstrb";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 53:
// PICSTRH
O << ":\n\tstrh";
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printAddrModePCOperand(MI, 1);
return;
break;
case 54:
// VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i...
O << ".s32\t";
printOperand(MI, 0);
O << ", ";
break;
case 55:
// VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i...
O << ".s16\t";
printOperand(MI, 0);
O << ", ";
break;
case 56:
// VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8...
O << ".s8\t";
printOperand(MI, 0);
O << ", ";
break;
case 57:
// VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i...
O << ".u32\t";
printOperand(MI, 0);
O << ", ";
break;
case 58:
// VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i...
O << ".u16\t";
printOperand(MI, 0);
O << ", ";
break;
case 59:
// VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8...
O << ".u8\t";
printOperand(MI, 0);
O << ", ";
break;
case 60:
// VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V...
O << ".i64\t";
printOperand(MI, 0);
O << ", ";
break;
case 61:
// VADDHNv4i16, VADDv2i32, VADDv4i32, VCEQv2i32, VCEQv4i32, VCLZv2i32, VC...
O << ".i32\t";
printOperand(MI, 0);
O << ", ";
break;
case 62:
// VADDHNv8i8, VADDv4i16, VADDv8i16, VCEQv4i16, VCEQv8i16, VCLZv4i16, VCL...
O << ".i16\t";
printOperand(MI, 0);
O << ", ";
break;
case 63:
// VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCLZv16i8, VCLZv8i8, VMLAv16...
O << ".i8\t";
printOperand(MI, 0);
O << ", ";
break;
case 64:
// VCNTd, VCNTq, VDUP8d, VDUP8q, VDUPLN8d, VDUPLN8q, VEXTd8, VEXTq8, VLD1...
O << ".8\t";
break;
case 65:
// VCVTBHS, VCVTTHS
O << ".f16.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
return;
break;
case 66:
// VCVTBSH, VCVTTSH
O << ".f32.f16\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
return;
break;
case 67:
// VCVTDS
O << ".f64.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
return;
break;
case 68:
// VCVTSD
O << ".f32.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
return;
break;
case 69:
// VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIRS, VTOSI...
O << ".s32.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 70:
// VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIRS, VTOUI...
O << ".u32.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 71:
// VCVTs2fd, VCVTs2fd_sfp, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS, VSLTOS
O << ".f32.s32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 72:
// VCVTu2fd, VCVTu2fd_sfp, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS, VULTOS
O << ".f32.u32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 73:
// VDUP16d, VDUP16q, VDUPLN16d, VDUPLN16q, VEXTd16, VEXTq16, VLD1q16, VRE...
O << ".16\t";
break;
case 74:
// VDUP32d, VDUP32q, VDUPLN32d, VDUPLN32q, VDUPLNfd, VDUPLNfq, VDUPfd, VD...
O << ".32\t";
break;
case 75:
// VLD1d16, VLD2LNd16, VLD2LNq16a, VLD2LNq16b, VLD2d16, VLD2q16, VLD3LNd1...
O << ".16\t{";
break;
case 76:
// VLD1d32, VLD1df, VLD2LNd32, VLD2LNq32a, VLD2LNq32b, VLD2d32, VLD2q32, ...
O << ".32\t{";
break;
case 77:
// VLD1d64, VLD2d64, VLD3d64, VLD4d64, VST1d64, VST2d64, VST3d64, VST4d64
O << ".64\t{";
break;
case 78:
// VLD1d8, VLD2LNd8, VLD2d8, VLD2q8, VLD3LNd8, VLD3d8, VLD3q8a, VLD3q8b, ...
O << ".8\t{";
break;
case 79:
// VLD1q64, VLDRD, VSLIv1i64, VSLIv2i64, VSRIv1i64, VSRIv2i64, VST1q64, V...
O << ".64\t";
break;
case 80:
// VMSR
O << "\tfpscr, ";
printOperand(MI, 0);
return;
break;
case 81:
// VMULLp, VMULpd, VMULpq
O << ".p8\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 82:
// VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V...
O << ".s64\t";
printOperand(MI, 0);
O << ", ";
break;
case 83:
// VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ...
O << ".u64\t";
printOperand(MI, 0);
O << ", ";
break;
case 84:
// VSHTOD
O << ".f64.s16\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 85:
// VSHTOS
O << ".f32.s16\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 86:
// VSITOD, VSLTOD
O << ".f64.s32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 87:
// VTOSHD
O << ".s16.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 88:
// VTOSHS
O << ".s16.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 89:
// VTOSIRD, VTOSIZD, VTOSLD
O << ".s32.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 90:
// VTOUHD
O << ".u16.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 91:
// VTOUHS
O << ".u16.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 92:
// VTOUIRD, VTOUIZD, VTOULD
O << ".u32.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 93:
// VUHTOD
O << ".f64.u16\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 94:
// VUHTOS
O << ".f32.u16\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
return;
break;
case 95:
// VUITOD, VULTOD
O << ".f64.u32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
case 96:
// t2ADCrr, t2ADCrs, t2ADDSri, t2ADDSrr, t2ADDSrs, t2ADDrSPi, t2ADDrSPs, ...
O << ".w\t";
printOperand(MI, 0);
break;
case 97:
// t2BR_JT
O << "\n";
printJT2BlockOperand(MI, 2);
return;
break;
case 98:
// t2LDM, t2LDM_RET, t2STM
printAddrMode4Operand(MI, 0, "wide");
O << "\t";
printAddrMode4Operand(MI, 0);
O << ", ";
printRegisterList(MI, 4);
return;
break;
case 99:
// t2MOVi, t2MOVr, t2MOVrx, t2MVNi
printPredicateOperand(MI, 2);
break;
case 100:
// tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
printPredicateOperand(MI, 4);
O << "\t";
printOperand(MI, 0);
O << ", ";
break;
case 101:
// tADDrPCi
O << ", pc, ";
printThumbS4ImmOperand(MI, 1);
return;
break;
case 102:
// tBR_JTr
O << "\n\t.align\t2\n";
printJTBlockOperand(MI, 1);
return;
break;
case 103:
// tBfar
O << "\t@ far jump";
return;
break;
case 104:
// tLDRpci
O << ".n\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
return;
break;
case 105:
// tMOVi8, tMVN, tRSB
printPredicateOperand(MI, 3);
O << "\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 2);
break;
case 106:
// tPICADD
O << ":\n\tadd\t";
printOperand(MI, 0);
O << ", pc";
return;
break;
}
// Fragment 2 encoded into 5 bits for 27 unique commands.
switch ((Bits >> 14) & 31) {
default: // unreachable.
case 0:
// ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MLA, MOVr, MOVrx, MVNr, RSCSri, R...
printOperand(MI, 1);
break;
case 1:
// ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri
printSOImmOperand(MI, 2);
return;
break;
case 2:
// ADCrr, ADDrr, ANDrr, BICrr, EORrr, MCR2, MCRR2, MRC2, MRRC2, MUL, ORRr...
printOperand(MI, 2);
break;
case 3:
// ADDSri, ADDSrr, ADDSrs, BFC, BKPT, BXJ, Bcc, CLZ, CMNzri, CMNzrr, CMNz...
printOperand(MI, 0);
break;
case 4:
// BL_pred, BLr9_pred
printOperand(MI, 0, "call");
return;
break;
case 5:
// CDP
O << ", cr";
printNoHashImmediate(MI, 2);
O << ", cr";
printNoHashImmediate(MI, 3);
O << ", cr";
printNoHashImmediate(MI, 4);
O << ", ";
printOperand(MI, 5);
return;
break;
case 6:
// FCONSTD, FCONSTS, MCR, MCRR, MRC, MRRC, VABDfd, VABDfq, VABSD, VABSS, ...
O << ", ";
break;
case 7:
// LDM, LDM_RET, STM, tLDM, tSTM
printAddrMode4Operand(MI, 0);
O << ", ";
printRegisterList(MI, 4);
return;
break;
case 8:
// MOVi, MVNi
printSOImmOperand(MI, 1);
return;
break;
case 9:
// MOVs, MVNs
printSORegOperand(MI, 1);
return;
break;
case 10:
// VCMPEZD, VCMPEZS, VCMPZD, VCMPZS, tRSB
O << ", #0";
return;
break;
case 11:
// VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VC...
return;
break;
case 12:
// VLD1q16, VLD1q32, VLD1q64, VLD1q8, VLD1qf
printOperand(MI, 0, "dregpair");
O << ", ";
printAddrMode6Operand(MI, 1);
return;
break;
case 13:
// VLDRQ, VSTRQ
printAddrMode4Operand(MI, 1);
O << ", ";
printOperand(MI, 0, "dregpair");
return;
break;
case 14:
// VMOVv16i8, VMOVv8i8
printHex8ImmOperand(MI, 1);
return;
break;
case 15:
// VMOVv1i64, VMOVv2i64
printHex64ImmOperand(MI, 1);
return;
break;
case 16:
// VMOVv2i32, VMOVv4i32
printHex32ImmOperand(MI, 1);
return;
break;
case 17:
// VMOVv4i16, VMOVv8i16
printHex16ImmOperand(MI, 1);
return;
break;
case 18:
// VST1d16, VST1d32, VST1d64, VST1d8, VST1df, VST2LNd16, VST2LNd32, VST2L...
printOperand(MI, 4);
break;
case 19:
// VST1q16, VST1q32, VST1q64, VST1q8, VST1qf
printOperand(MI, 4, "dregpair");
O << ", ";
printAddrMode6Operand(MI, 0);
return;
break;
case 20:
// VST3q16a, VST3q16b, VST3q32a, VST3q32b, VST3q8a, VST3q8b, VST4q16a, VS...
printOperand(MI, 5);
O << ", ";
printOperand(MI, 6);
O << ", ";
printOperand(MI, 7);
break;
case 21:
// t2LEApcrel, t2LEApcrelJT
O << ", #";
printOperand(MI, 1);
break;
case 22:
// t2MOVi, t2MOVr
O << ".w\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
return;
break;
case 23:
// t2MOVrx, t2MVNi
O << "\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
return;
break;
case 24:
// tADC, tADDi8, tAND, tASRrr, tBIC, tEOR, tLSLrr, tLSRrr, tMUL, tORR, tR...
printOperand(MI, 3);
return;
break;
case 25:
// tADDspi, tSUBspi, tSUBspi_
printThumbS4ImmOperand(MI, 2);
return;
break;
case 26:
// tPOP, tPOP_RET, tPUSH
printRegisterList(MI, 2);
return;
break;
}
switch (MI->getOpcode()) {
case ARM::ADCSSri:
case ARM::ADCSSrr:
case ARM::ADCSSrs:
case ARM::BFC:
case ARM::CLZ:
case ARM::CMNzri:
case ARM::CMNzrr:
case ARM::CMNzrs:
case ARM::CMPri:
case ARM::CMPrr:
case ARM::CMPrs:
case ARM::CMPzri:
case ARM::CMPzrr:
case ARM::CMPzrs:
case ARM::LDR:
case ARM::LDRB:
case ARM::LDRD:
case ARM::LDRH:
case ARM::LDRSB:
case ARM::LDRSH:
case ARM::LDRcp:
case ARM::MOVCCi:
case ARM::MOVCCr:
case ARM::MOVCCs:
case ARM::MOVTi16:
case ARM::MOVi16:
case ARM::MOVi2pieces:
case ARM::RBIT:
case ARM::REV:
case ARM::REV16:
case ARM::REVSH:
case ARM::RSCSri:
case ARM::RSCSrs:
case ARM::SBCSSri:
case ARM::SBCSSrr:
case ARM::SBCSSrs:
case ARM::STR:
case ARM::STRB:
case ARM::STRD:
case ARM::STRH:
case ARM::SXTBr:
case ARM::SXTHr:
case ARM::TEQri:
case ARM::TEQrr:
case ARM::TEQrs:
case ARM::TSTri:
case ARM::TSTrr:
case ARM::TSTrs:
case ARM::UXTB16r:
case ARM::UXTBr:
case ARM::UXTHr:
case ARM::VABALsv2i64:
case ARM::VABALsv4i32:
case ARM::VABALsv8i16:
case ARM::VABALuv2i64:
case ARM::VABALuv4i32:
case ARM::VABALuv8i16:
case ARM::VABAsv16i8:
case ARM::VABAsv2i32:
case ARM::VABAsv4i16:
case ARM::VABAsv4i32:
case ARM::VABAsv8i16:
case ARM::VABAsv8i8:
case ARM::VABAuv16i8:
case ARM::VABAuv2i32:
case ARM::VABAuv4i16:
case ARM::VABAuv4i32:
case ARM::VABAuv8i16:
case ARM::VABAuv8i8:
case ARM::VABDLsv2i64:
case ARM::VABDLsv4i32:
case ARM::VABDLsv8i16:
case ARM::VABDLuv2i64:
case ARM::VABDLuv4i32:
case ARM::VABDLuv8i16:
case ARM::VABDsv16i8:
case ARM::VABDsv2i32:
case ARM::VABDsv4i16:
case ARM::VABDsv4i32:
case ARM::VABDsv8i16:
case ARM::VABDsv8i8:
case ARM::VABDuv16i8:
case ARM::VABDuv2i32:
case ARM::VABDuv4i16:
case ARM::VABDuv4i32:
case ARM::VABDuv8i16:
case ARM::VABDuv8i8:
case ARM::VADDHNv2i32:
case ARM::VADDHNv4i16:
case ARM::VADDHNv8i8:
case ARM::VADDLsv2i64:
case ARM::VADDLsv4i32:
case ARM::VADDLsv8i16:
case ARM::VADDLuv2i64:
case ARM::VADDLuv4i32:
case ARM::VADDLuv8i16:
case ARM::VADDWsv2i64:
case ARM::VADDWsv4i32:
case ARM::VADDWsv8i16:
case ARM::VADDWuv2i64:
case ARM::VADDWuv4i32:
case ARM::VADDWuv8i16:
case ARM::VADDv16i8:
case ARM::VADDv1i64:
case ARM::VADDv2i32:
case ARM::VADDv2i64:
case ARM::VADDv4i16:
case ARM::VADDv4i32:
case ARM::VADDv8i16:
case ARM::VADDv8i8:
case ARM::VCEQv16i8:
case ARM::VCEQv2i32:
case ARM::VCEQv4i16:
case ARM::VCEQv4i32:
case ARM::VCEQv8i16:
case ARM::VCEQv8i8:
case ARM::VCGEsv16i8:
case ARM::VCGEsv2i32:
case ARM::VCGEsv4i16:
case ARM::VCGEsv4i32:
case ARM::VCGEsv8i16:
case ARM::VCGEsv8i8:
case ARM::VCGEuv16i8:
case ARM::VCGEuv2i32:
case ARM::VCGEuv4i16:
case ARM::VCGEuv4i32:
case ARM::VCGEuv8i16:
case ARM::VCGEuv8i8:
case ARM::VCGTsv16i8:
case ARM::VCGTsv2i32:
case ARM::VCGTsv4i16:
case ARM::VCGTsv4i32:
case ARM::VCGTsv8i16:
case ARM::VCGTsv8i8:
case ARM::VCGTuv16i8:
case ARM::VCGTuv2i32:
case ARM::VCGTuv4i16:
case ARM::VCGTuv4i32:
case ARM::VCGTuv8i16:
case ARM::VCGTuv8i8:
case ARM::VCNTd:
case ARM::VCNTq:
case ARM::VDUP16d:
case ARM::VDUP16q:
case ARM::VDUP32d:
case ARM::VDUP32q:
case ARM::VDUP8d:
case ARM::VDUP8q:
case ARM::VDUPfd:
case ARM::VDUPfdf:
case ARM::VDUPfq:
case ARM::VDUPfqf:
case ARM::VHADDsv16i8:
case ARM::VHADDsv2i32:
case ARM::VHADDsv4i16:
case ARM::VHADDsv4i32:
case ARM::VHADDsv8i16:
case ARM::VHADDsv8i8:
case ARM::VHADDuv16i8:
case ARM::VHADDuv2i32:
case ARM::VHADDuv4i16:
case ARM::VHADDuv4i32:
case ARM::VHADDuv8i16:
case ARM::VHADDuv8i8:
case ARM::VHSUBsv16i8:
case ARM::VHSUBsv2i32:
case ARM::VHSUBsv4i16:
case ARM::VHSUBsv4i32:
case ARM::VHSUBsv8i16:
case ARM::VHSUBsv8i8:
case ARM::VHSUBuv16i8:
case ARM::VHSUBuv2i32:
case ARM::VHSUBuv4i16:
case ARM::VHSUBuv4i32:
case ARM::VHSUBuv8i16:
case ARM::VHSUBuv8i8:
case ARM::VLDRD:
case ARM::VLDRS:
case ARM::VMAXsv16i8:
case ARM::VMAXsv2i32:
case ARM::VMAXsv4i16:
case ARM::VMAXsv4i32:
case ARM::VMAXsv8i16:
case ARM::VMAXsv8i8:
case ARM::VMAXuv16i8:
case ARM::VMAXuv2i32:
case ARM::VMAXuv4i16:
case ARM::VMAXuv4i32:
case ARM::VMAXuv8i16:
case ARM::VMAXuv8i8:
case ARM::VMINsv16i8:
case ARM::VMINsv2i32:
case ARM::VMINsv4i16:
case ARM::VMINsv4i32:
case ARM::VMINsv8i16:
case ARM::VMINsv8i8:
case ARM::VMINuv16i8:
case ARM::VMINuv2i32:
case ARM::VMINuv4i16:
case ARM::VMINuv4i32:
case ARM::VMINuv8i16:
case ARM::VMINuv8i8:
case ARM::VMLALsv2i64:
case ARM::VMLALsv4i32:
case ARM::VMLALsv8i16:
case ARM::VMLALuv2i64:
case ARM::VMLALuv4i32:
case ARM::VMLALuv8i16:
case ARM::VMLAv16i8:
case ARM::VMLAv2i32:
case ARM::VMLAv4i16:
case ARM::VMLAv4i32:
case ARM::VMLAv8i16:
case ARM::VMLAv8i8:
case ARM::VMLSLsv2i64:
case ARM::VMLSLsv4i32:
case ARM::VMLSLsv8i16:
case ARM::VMLSLuv2i64:
case ARM::VMLSLuv4i32:
case ARM::VMLSLuv8i16:
case ARM::VMLSv16i8:
case ARM::VMLSv2i32:
case ARM::VMLSv4i16:
case ARM::VMLSv4i32:
case ARM::VMLSv8i16:
case ARM::VMLSv8i8:
case ARM::VMOVDneon:
case ARM::VMOVQ:
case ARM::VMOVRS:
case ARM::VMOVSR:
case ARM::VMULLsv2i64:
case ARM::VMULLsv4i32:
case ARM::VMULLsv8i16:
case ARM::VMULLuv2i64:
case ARM::VMULLuv4i32:
case ARM::VMULLuv8i16:
case ARM::VMULv16i8:
case ARM::VMULv2i32:
case ARM::VMULv4i16:
case ARM::VMULv4i32:
case ARM::VMULv8i16:
case ARM::VMULv8i8:
case ARM::VMVNd:
case ARM::VMVNq:
case ARM::VPADDi16:
case ARM::VPADDi32:
case ARM::VPADDi8:
case ARM::VPMAXs16:
case ARM::VPMAXs32:
case ARM::VPMAXs8:
case ARM::VPMAXu16:
case ARM::VPMAXu32:
case ARM::VPMAXu8:
case ARM::VPMINs16:
case ARM::VPMINs32:
case ARM::VPMINs8:
case ARM::VPMINu16:
case ARM::VPMINu32:
case ARM::VPMINu8:
case ARM::VQADDsv16i8:
case ARM::VQADDsv1i64:
case ARM::VQADDsv2i32:
case ARM::VQADDsv2i64:
case ARM::VQADDsv4i16:
case ARM::VQADDsv4i32:
case ARM::VQADDsv8i16:
case ARM::VQADDsv8i8:
case ARM::VQADDuv16i8:
case ARM::VQADDuv1i64:
case ARM::VQADDuv2i32:
case ARM::VQADDuv2i64:
case ARM::VQADDuv4i16:
case ARM::VQADDuv4i32:
case ARM::VQADDuv8i16:
case ARM::VQADDuv8i8:
case ARM::VQDMLALv2i64:
case ARM::VQDMLALv4i32:
case ARM::VQDMLSLv2i64:
case ARM::VQDMLSLv4i32:
case ARM::VQDMULHv2i32:
case ARM::VQDMULHv4i16:
case ARM::VQDMULHv4i32:
case ARM::VQDMULHv8i16:
case ARM::VQDMULLv2i64:
case ARM::VQDMULLv4i32:
case ARM::VQRDMULHv2i32:
case ARM::VQRDMULHv4i16:
case ARM::VQRDMULHv4i32:
case ARM::VQRDMULHv8i16:
case ARM::VQRSHLsv16i8:
case ARM::VQRSHLsv1i64:
case ARM::VQRSHLsv2i32:
case ARM::VQRSHLsv2i64:
case ARM::VQRSHLsv4i16:
case ARM::VQRSHLsv4i32:
case ARM::VQRSHLsv8i16:
case ARM::VQRSHLsv8i8:
case ARM::VQRSHLuv16i8:
case ARM::VQRSHLuv1i64:
case ARM::VQRSHLuv2i32:
case ARM::VQRSHLuv2i64:
case ARM::VQRSHLuv4i16:
case ARM::VQRSHLuv4i32:
case ARM::VQRSHLuv8i16:
case ARM::VQRSHLuv8i8:
case ARM::VQRSHRNsv2i32:
case ARM::VQRSHRNsv4i16:
case ARM::VQRSHRNsv8i8:
case ARM::VQRSHRNuv2i32:
case ARM::VQRSHRNuv4i16:
case ARM::VQRSHRNuv8i8:
case ARM::VQRSHRUNv2i32:
case ARM::VQRSHRUNv4i16:
case ARM::VQRSHRUNv8i8:
case ARM::VQSHLsiv16i8:
case ARM::VQSHLsiv1i64:
case ARM::VQSHLsiv2i32:
case ARM::VQSHLsiv2i64:
case ARM::VQSHLsiv4i16:
case ARM::VQSHLsiv4i32:
case ARM::VQSHLsiv8i16:
case ARM::VQSHLsiv8i8:
case ARM::VQSHLsuv16i8:
case ARM::VQSHLsuv1i64:
case ARM::VQSHLsuv2i32:
case ARM::VQSHLsuv2i64:
case ARM::VQSHLsuv4i16:
case ARM::VQSHLsuv4i32:
case ARM::VQSHLsuv8i16:
case ARM::VQSHLsuv8i8:
case ARM::VQSHLsv16i8:
case ARM::VQSHLsv1i64:
case ARM::VQSHLsv2i32:
case ARM::VQSHLsv2i64:
case ARM::VQSHLsv4i16:
case ARM::VQSHLsv4i32:
case ARM::VQSHLsv8i16:
case ARM::VQSHLsv8i8:
case ARM::VQSHLuiv16i8:
case ARM::VQSHLuiv1i64:
case ARM::VQSHLuiv2i32:
case ARM::VQSHLuiv2i64:
case ARM::VQSHLuiv4i16:
case ARM::VQSHLuiv4i32:
case ARM::VQSHLuiv8i16:
case ARM::VQSHLuiv8i8:
case ARM::VQSHLuv16i8:
case ARM::VQSHLuv1i64:
case ARM::VQSHLuv2i32:
case ARM::VQSHLuv2i64:
case ARM::VQSHLuv4i16:
case ARM::VQSHLuv4i32:
case ARM::VQSHLuv8i16:
case ARM::VQSHLuv8i8:
case ARM::VQSHRNsv2i32:
case ARM::VQSHRNsv4i16:
case ARM::VQSHRNsv8i8:
case ARM::VQSHRNuv2i32:
case ARM::VQSHRNuv4i16:
case ARM::VQSHRNuv8i8:
case ARM::VQSHRUNv2i32:
case ARM::VQSHRUNv4i16:
case ARM::VQSHRUNv8i8:
case ARM::VQSUBsv16i8:
case ARM::VQSUBsv1i64:
case ARM::VQSUBsv2i32:
case ARM::VQSUBsv2i64:
case ARM::VQSUBsv4i16:
case ARM::VQSUBsv4i32:
case ARM::VQSUBsv8i16:
case ARM::VQSUBsv8i8:
case ARM::VQSUBuv16i8:
case ARM::VQSUBuv1i64:
case ARM::VQSUBuv2i32:
case ARM::VQSUBuv2i64:
case ARM::VQSUBuv4i16:
case ARM::VQSUBuv4i32:
case ARM::VQSUBuv8i16:
case ARM::VQSUBuv8i8:
case ARM::VRADDHNv2i32:
case ARM::VRADDHNv4i16:
case ARM::VRADDHNv8i8:
case ARM::VREV16d8:
case ARM::VREV16q8:
case ARM::VREV32d16:
case ARM::VREV32d8:
case ARM::VREV32q16:
case ARM::VREV32q8:
case ARM::VREV64d16:
case ARM::VREV64d32:
case ARM::VREV64d8:
case ARM::VREV64df:
case ARM::VREV64q16:
case ARM::VREV64q32:
case ARM::VREV64q8:
case ARM::VREV64qf:
case ARM::VRHADDsv16i8:
case ARM::VRHADDsv2i32:
case ARM::VRHADDsv4i16:
case ARM::VRHADDsv4i32:
case ARM::VRHADDsv8i16:
case ARM::VRHADDsv8i8:
case ARM::VRHADDuv16i8:
case ARM::VRHADDuv2i32:
case ARM::VRHADDuv4i16:
case ARM::VRHADDuv4i32:
case ARM::VRHADDuv8i16:
case ARM::VRHADDuv8i8:
case ARM::VRSHLsv16i8:
case ARM::VRSHLsv1i64:
case ARM::VRSHLsv2i32:
case ARM::VRSHLsv2i64:
case ARM::VRSHLsv4i16:
case ARM::VRSHLsv4i32:
case ARM::VRSHLsv8i16:
case ARM::VRSHLsv8i8:
case ARM::VRSHLuv16i8:
case ARM::VRSHLuv1i64:
case ARM::VRSHLuv2i32:
case ARM::VRSHLuv2i64:
case ARM::VRSHLuv4i16:
case ARM::VRSHLuv4i32:
case ARM::VRSHLuv8i16:
case ARM::VRSHLuv8i8:
case ARM::VRSHRNv2i32:
case ARM::VRSHRNv4i16:
case ARM::VRSHRNv8i8:
case ARM::VRSHRsv16i8:
case ARM::VRSHRsv1i64:
case ARM::VRSHRsv2i32:
case ARM::VRSHRsv2i64:
case ARM::VRSHRsv4i16:
case ARM::VRSHRsv4i32:
case ARM::VRSHRsv8i16:
case ARM::VRSHRsv8i8:
case ARM::VRSHRuv16i8:
case ARM::VRSHRuv1i64:
case ARM::VRSHRuv2i32:
case ARM::VRSHRuv2i64:
case ARM::VRSHRuv4i16:
case ARM::VRSHRuv4i32:
case ARM::VRSHRuv8i16:
case ARM::VRSHRuv8i8:
case ARM::VRSRAsv16i8:
case ARM::VRSRAsv1i64:
case ARM::VRSRAsv2i32:
case ARM::VRSRAsv2i64:
case ARM::VRSRAsv4i16:
case ARM::VRSRAsv4i32:
case ARM::VRSRAsv8i16:
case ARM::VRSRAsv8i8:
case ARM::VRSRAuv16i8:
case ARM::VRSRAuv1i64:
case ARM::VRSRAuv2i32:
case ARM::VRSRAuv2i64:
case ARM::VRSRAuv4i16:
case ARM::VRSRAuv4i32:
case ARM::VRSRAuv8i16:
case ARM::VRSRAuv8i8:
case ARM::VRSUBHNv2i32:
case ARM::VRSUBHNv4i16:
case ARM::VRSUBHNv8i8:
case ARM::VSHLLi16:
case ARM::VSHLLi32:
case ARM::VSHLLi8:
case ARM::VSHLLsv2i64:
case ARM::VSHLLsv4i32:
case ARM::VSHLLsv8i16:
case ARM::VSHLLuv2i64:
case ARM::VSHLLuv4i32:
case ARM::VSHLLuv8i16:
case ARM::VSHLiv16i8:
case ARM::VSHLiv1i64:
case ARM::VSHLiv2i32:
case ARM::VSHLiv2i64:
case ARM::VSHLiv4i16:
case ARM::VSHLiv4i32:
case ARM::VSHLiv8i16:
case ARM::VSHLiv8i8:
case ARM::VSHLsv16i8:
case ARM::VSHLsv1i64:
case ARM::VSHLsv2i32:
case ARM::VSHLsv2i64:
case ARM::VSHLsv4i16:
case ARM::VSHLsv4i32:
case ARM::VSHLsv8i16:
case ARM::VSHLsv8i8:
case ARM::VSHLuv16i8:
case ARM::VSHLuv1i64:
case ARM::VSHLuv2i32:
case ARM::VSHLuv2i64:
case ARM::VSHLuv4i16:
case ARM::VSHLuv4i32:
case ARM::VSHLuv8i16:
case ARM::VSHLuv8i8:
case ARM::VSHRNv2i32:
case ARM::VSHRNv4i16:
case ARM::VSHRNv8i8:
case ARM::VSHRsv16i8:
case ARM::VSHRsv1i64:
case ARM::VSHRsv2i32:
case ARM::VSHRsv2i64:
case ARM::VSHRsv4i16:
case ARM::VSHRsv4i32:
case ARM::VSHRsv8i16:
case ARM::VSHRsv8i8:
case ARM::VSHRuv16i8:
case ARM::VSHRuv1i64:
case ARM::VSHRuv2i32:
case ARM::VSHRuv2i64:
case ARM::VSHRuv4i16:
case ARM::VSHRuv4i32:
case ARM::VSHRuv8i16:
case ARM::VSHRuv8i8:
case ARM::VSRAsv16i8:
case ARM::VSRAsv1i64:
case ARM::VSRAsv2i32:
case ARM::VSRAsv2i64:
case ARM::VSRAsv4i16:
case ARM::VSRAsv4i32:
case ARM::VSRAsv8i16:
case ARM::VSRAsv8i8:
case ARM::VSRAuv16i8:
case ARM::VSRAuv1i64:
case ARM::VSRAuv2i32:
case ARM::VSRAuv2i64:
case ARM::VSRAuv4i16:
case ARM::VSRAuv4i32:
case ARM::VSRAuv8i16:
case ARM::VSRAuv8i8:
case ARM::VSTRD:
case ARM::VSTRS:
case ARM::VSUBHNv2i32:
case ARM::VSUBHNv4i16:
case ARM::VSUBHNv8i8:
case ARM::VSUBLsv2i64:
case ARM::VSUBLsv4i32:
case ARM::VSUBLsv8i16:
case ARM::VSUBLuv2i64:
case ARM::VSUBLuv4i32:
case ARM::VSUBLuv8i16:
case ARM::VSUBWsv2i64:
case ARM::VSUBWsv4i32:
case ARM::VSUBWsv8i16:
case ARM::VSUBWuv2i64:
case ARM::VSUBWuv4i32:
case ARM::VSUBWuv8i16:
case ARM::VSUBv16i8:
case ARM::VSUBv1i64:
case ARM::VSUBv2i32:
case ARM::VSUBv2i64:
case ARM::VSUBv4i16:
case ARM::VSUBv4i32:
case ARM::VSUBv8i16:
case ARM::VSUBv8i8:
case ARM::VTRNd16:
case ARM::VTRNd32:
case ARM::VTRNd8:
case ARM::VTRNq16:
case ARM::VTRNq32:
case ARM::VTRNq8:
case ARM::VUZPd16:
case ARM::VUZPd32:
case ARM::VUZPd8:
case ARM::VUZPq16:
case ARM::VUZPq32:
case ARM::VUZPq8:
case ARM::VZIPd16:
case ARM::VZIPd32:
case ARM::VZIPd8:
case ARM::VZIPq16:
case ARM::VZIPq32:
case ARM::VZIPq8:
case ARM::t2ADCSri:
case ARM::t2ADCSrr:
case ARM::t2ADCSrs:
case ARM::t2BFC:
case ARM::t2CLZ:
case ARM::t2LDRBi8:
case ARM::t2LDRDi8:
case ARM::t2LDRDpci:
case ARM::t2LDRHi8:
case ARM::t2LDRSBi8:
case ARM::t2LDRSHi8:
case ARM::t2LDRi8:
case ARM::t2MOVTi16:
case ARM::t2MOVi16:
case ARM::t2RBIT:
case ARM::t2SBCSri:
case ARM::t2SBCSrr:
case ARM::t2SBCSrs:
case ARM::t2STRBi8:
case ARM::t2STRDi8:
case ARM::t2STRHi8:
case ARM::t2STRi8:
case ARM::t2SUBrSPi12_:
case ARM::t2SUBrSPi_:
case ARM::t2SUBrSPs_:
case ARM::tADDhirr:
case ARM::tADDi3:
case ARM::tADDrSPi:
case ARM::tADDrr:
case ARM::tASRri:
case ARM::tCMNz:
case ARM::tCMPhir:
case ARM::tCMPi8:
case ARM::tCMPr:
case ARM::tCMPzhir:
case ARM::tCMPzi8:
case ARM::tCMPzr:
case ARM::tLDR:
case ARM::tLDRB:
case ARM::tLDRBi:
case ARM::tLDRH:
case ARM::tLDRHi:
case ARM::tLDRSB:
case ARM::tLDRSH:
case ARM::tLDRcp:
case ARM::tLDRi:
case ARM::tLDRspi:
case ARM::tLSLri:
case ARM::tLSRri:
case ARM::tMOVCCi:
case ARM::tMOVCCr:
case ARM::tREV:
case ARM::tREV16:
case ARM::tREVSH:
case ARM::tRestore:
case ARM::tSTR:
case ARM::tSTRB:
case ARM::tSTRBi:
case ARM::tSTRH:
case ARM::tSTRHi:
case ARM::tSTRi:
case ARM::tSTRspi:
case ARM::tSUBi3:
case ARM::tSUBrr:
case ARM::tSXTB:
case ARM::tSXTH:
case ARM::tSpill:
case ARM::tTST:
case ARM::tUXTB:
case ARM::tUXTH:
O << ", ";
switch (MI->getOpcode()) {
case ARM::ADCSSri:
case ARM::MOVCCi:
case ARM::RSCSri:
case ARM::SBCSSri: printSOImmOperand(MI, 2); break;
case ARM::ADCSSrr:
case ARM::MOVCCr:
case ARM::MOVTi16:
case ARM::SBCSSrr:
case ARM::VABDLsv2i64:
case ARM::VABDLsv4i32:
case ARM::VABDLsv8i16:
case ARM::VABDLuv2i64:
case ARM::VABDLuv4i32:
case ARM::VABDLuv8i16:
case ARM::VABDsv16i8:
case ARM::VABDsv2i32:
case ARM::VABDsv4i16:
case ARM::VABDsv4i32:
case ARM::VABDsv8i16:
case ARM::VABDsv8i8:
case ARM::VABDuv16i8:
case ARM::VABDuv2i32:
case ARM::VABDuv4i16:
case ARM::VABDuv4i32:
case ARM::VABDuv8i16:
case ARM::VABDuv8i8:
case ARM::VADDHNv2i32:
case ARM::VADDHNv4i16:
case ARM::VADDHNv8i8:
case ARM::VADDLsv2i64:
case ARM::VADDLsv4i32:
case ARM::VADDLsv8i16:
case ARM::VADDLuv2i64:
case ARM::VADDLuv4i32:
case ARM::VADDLuv8i16:
case ARM::VADDWsv2i64:
case ARM::VADDWsv4i32:
case ARM::VADDWsv8i16:
case ARM::VADDWuv2i64:
case ARM::VADDWuv4i32:
case ARM::VADDWuv8i16:
case ARM::VADDv16i8:
case ARM::VADDv1i64:
case ARM::VADDv2i32:
case ARM::VADDv2i64:
case ARM::VADDv4i16:
case ARM::VADDv4i32:
case ARM::VADDv8i16:
case ARM::VADDv8i8:
case ARM::VCEQv16i8:
case ARM::VCEQv2i32:
case ARM::VCEQv4i16:
case ARM::VCEQv4i32:
case ARM::VCEQv8i16:
case ARM::VCEQv8i8:
case ARM::VCGEsv16i8:
case ARM::VCGEsv2i32:
case ARM::VCGEsv4i16:
case ARM::VCGEsv4i32:
case ARM::VCGEsv8i16:
case ARM::VCGEsv8i8:
case ARM::VCGEuv16i8:
case ARM::VCGEuv2i32:
case ARM::VCGEuv4i16:
case ARM::VCGEuv4i32:
case ARM::VCGEuv8i16:
case ARM::VCGEuv8i8:
case ARM::VCGTsv16i8:
case ARM::VCGTsv2i32:
case ARM::VCGTsv4i16:
case ARM::VCGTsv4i32:
case ARM::VCGTsv8i16:
case ARM::VCGTsv8i8:
case ARM::VCGTuv16i8:
case ARM::VCGTuv2i32:
case ARM::VCGTuv4i16:
case ARM::VCGTuv4i32:
case ARM::VCGTuv8i16:
case ARM::VCGTuv8i8:
case ARM::VHADDsv16i8:
case ARM::VHADDsv2i32:
case ARM::VHADDsv4i16:
case ARM::VHADDsv4i32:
case ARM::VHADDsv8i16:
case ARM::VHADDsv8i8:
case ARM::VHADDuv16i8:
case ARM::VHADDuv2i32:
case ARM::VHADDuv4i16:
case ARM::VHADDuv4i32:
case ARM::VHADDuv8i16:
case ARM::VHADDuv8i8:
case ARM::VHSUBsv16i8:
case ARM::VHSUBsv2i32:
case ARM::VHSUBsv4i16:
case ARM::VHSUBsv4i32:
case ARM::VHSUBsv8i16:
case ARM::VHSUBsv8i8:
case ARM::VHSUBuv16i8:
case ARM::VHSUBuv2i32:
case ARM::VHSUBuv4i16:
case ARM::VHSUBuv4i32:
case ARM::VHSUBuv8i16:
case ARM::VHSUBuv8i8:
case ARM::VMAXsv16i8:
case ARM::VMAXsv2i32:
case ARM::VMAXsv4i16:
case ARM::VMAXsv4i32:
case ARM::VMAXsv8i16:
case ARM::VMAXsv8i8:
case ARM::VMAXuv16i8:
case ARM::VMAXuv2i32:
case ARM::VMAXuv4i16:
case ARM::VMAXuv4i32:
case ARM::VMAXuv8i16:
case ARM::VMAXuv8i8:
case ARM::VMINsv16i8:
case ARM::VMINsv2i32:
case ARM::VMINsv4i16:
case ARM::VMINsv4i32:
case ARM::VMINsv8i16:
case ARM::VMINsv8i8:
case ARM::VMINuv16i8:
case ARM::VMINuv2i32:
case ARM::VMINuv4i16:
case ARM::VMINuv4i32:
case ARM::VMINuv8i16:
case ARM::VMINuv8i8:
case ARM::VMULLsv2i64:
case ARM::VMULLsv4i32:
case ARM::VMULLsv8i16:
case ARM::VMULLuv2i64:
case ARM::VMULLuv4i32:
case ARM::VMULLuv8i16:
case ARM::VMULv16i8:
case ARM::VMULv2i32:
case ARM::VMULv4i16:
case ARM::VMULv4i32:
case ARM::VMULv8i16:
case ARM::VMULv8i8:
case ARM::VPADDi16:
case ARM::VPADDi32:
case ARM::VPADDi8:
case ARM::VPMAXs16:
case ARM::VPMAXs32:
case ARM::VPMAXs8:
case ARM::VPMAXu16:
case ARM::VPMAXu32:
case ARM::VPMAXu8:
case ARM::VPMINs16:
case ARM::VPMINs32:
case ARM::VPMINs8:
case ARM::VPMINu16:
case ARM::VPMINu32:
case ARM::VPMINu8:
case ARM::VQADDsv16i8:
case ARM::VQADDsv1i64:
case ARM::VQADDsv2i32:
case ARM::VQADDsv2i64:
case ARM::VQADDsv4i16:
case ARM::VQADDsv4i32:
case ARM::VQADDsv8i16:
case ARM::VQADDsv8i8:
case ARM::VQADDuv16i8:
case ARM::VQADDuv1i64:
case ARM::VQADDuv2i32:
case ARM::VQADDuv2i64:
case ARM::VQADDuv4i16:
case ARM::VQADDuv4i32:
case ARM::VQADDuv8i16:
case ARM::VQADDuv8i8:
case ARM::VQDMULHv2i32:
case ARM::VQDMULHv4i16:
case ARM::VQDMULHv4i32:
case ARM::VQDMULHv8i16:
case ARM::VQDMULLv2i64:
case ARM::VQDMULLv4i32:
case ARM::VQRDMULHv2i32:
case ARM::VQRDMULHv4i16:
case ARM::VQRDMULHv4i32:
case ARM::VQRDMULHv8i16:
case ARM::VQRSHLsv16i8:
case ARM::VQRSHLsv1i64:
case ARM::VQRSHLsv2i32:
case ARM::VQRSHLsv2i64:
case ARM::VQRSHLsv4i16:
case ARM::VQRSHLsv4i32:
case ARM::VQRSHLsv8i16:
case ARM::VQRSHLsv8i8:
case ARM::VQRSHLuv16i8:
case ARM::VQRSHLuv1i64:
case ARM::VQRSHLuv2i32:
case ARM::VQRSHLuv2i64:
case ARM::VQRSHLuv4i16:
case ARM::VQRSHLuv4i32:
case ARM::VQRSHLuv8i16:
case ARM::VQRSHLuv8i8:
case ARM::VQRSHRNsv2i32:
case ARM::VQRSHRNsv4i16:
case ARM::VQRSHRNsv8i8:
case ARM::VQRSHRNuv2i32:
case ARM::VQRSHRNuv4i16:
case ARM::VQRSHRNuv8i8:
case ARM::VQRSHRUNv2i32:
case ARM::VQRSHRUNv4i16:
case ARM::VQRSHRUNv8i8:
case ARM::VQSHLsiv16i8:
case ARM::VQSHLsiv1i64:
case ARM::VQSHLsiv2i32:
case ARM::VQSHLsiv2i64:
case ARM::VQSHLsiv4i16:
case ARM::VQSHLsiv4i32:
case ARM::VQSHLsiv8i16:
case ARM::VQSHLsiv8i8:
case ARM::VQSHLsuv16i8:
case ARM::VQSHLsuv1i64:
case ARM::VQSHLsuv2i32:
case ARM::VQSHLsuv2i64:
case ARM::VQSHLsuv4i16:
case ARM::VQSHLsuv4i32:
case ARM::VQSHLsuv8i16:
case ARM::VQSHLsuv8i8:
case ARM::VQSHLsv16i8:
case ARM::VQSHLsv1i64:
case ARM::VQSHLsv2i32:
case ARM::VQSHLsv2i64:
case ARM::VQSHLsv4i16:
case ARM::VQSHLsv4i32:
case ARM::VQSHLsv8i16:
case ARM::VQSHLsv8i8:
case ARM::VQSHLuiv16i8:
case ARM::VQSHLuiv1i64:
case ARM::VQSHLuiv2i32:
case ARM::VQSHLuiv2i64:
case ARM::VQSHLuiv4i16:
case ARM::VQSHLuiv4i32:
case ARM::VQSHLuiv8i16:
case ARM::VQSHLuiv8i8:
case ARM::VQSHLuv16i8:
case ARM::VQSHLuv1i64:
case ARM::VQSHLuv2i32:
case ARM::VQSHLuv2i64:
case ARM::VQSHLuv4i16:
case ARM::VQSHLuv4i32:
case ARM::VQSHLuv8i16:
case ARM::VQSHLuv8i8:
case ARM::VQSHRNsv2i32:
case ARM::VQSHRNsv4i16:
case ARM::VQSHRNsv8i8:
case ARM::VQSHRNuv2i32:
case ARM::VQSHRNuv4i16:
case ARM::VQSHRNuv8i8:
case ARM::VQSHRUNv2i32:
case ARM::VQSHRUNv4i16:
case ARM::VQSHRUNv8i8:
case ARM::VQSUBsv16i8:
case ARM::VQSUBsv1i64:
case ARM::VQSUBsv2i32:
case ARM::VQSUBsv2i64:
case ARM::VQSUBsv4i16:
case ARM::VQSUBsv4i32:
case ARM::VQSUBsv8i16:
case ARM::VQSUBsv8i8:
case ARM::VQSUBuv16i8:
case ARM::VQSUBuv1i64:
case ARM::VQSUBuv2i32:
case ARM::VQSUBuv2i64:
case ARM::VQSUBuv4i16:
case ARM::VQSUBuv4i32:
case ARM::VQSUBuv8i16:
case ARM::VQSUBuv8i8:
case ARM::VRADDHNv2i32:
case ARM::VRADDHNv4i16:
case ARM::VRADDHNv8i8:
case ARM::VRHADDsv16i8:
case ARM::VRHADDsv2i32:
case ARM::VRHADDsv4i16:
case ARM::VRHADDsv4i32:
case ARM::VRHADDsv8i16:
case ARM::VRHADDsv8i8:
case ARM::VRHADDuv16i8:
case ARM::VRHADDuv2i32:
case ARM::VRHADDuv4i16:
case ARM::VRHADDuv4i32:
case ARM::VRHADDuv8i16:
case ARM::VRHADDuv8i8:
case ARM::VRSHLsv16i8:
case ARM::VRSHLsv1i64:
case ARM::VRSHLsv2i32:
case ARM::VRSHLsv2i64:
case ARM::VRSHLsv4i16:
case ARM::VRSHLsv4i32:
case ARM::VRSHLsv8i16:
case ARM::VRSHLsv8i8:
case ARM::VRSHLuv16i8:
case ARM::VRSHLuv1i64:
case ARM::VRSHLuv2i32:
case ARM::VRSHLuv2i64:
case ARM::VRSHLuv4i16:
case ARM::VRSHLuv4i32:
case ARM::VRSHLuv8i16:
case ARM::VRSHLuv8i8:
case ARM::VRSHRNv2i32:
case ARM::VRSHRNv4i16:
case ARM::VRSHRNv8i8:
case ARM::VRSHRsv16i8:
case ARM::VRSHRsv1i64:
case ARM::VRSHRsv2i32:
case ARM::VRSHRsv2i64:
case ARM::VRSHRsv4i16:
case ARM::VRSHRsv4i32:
case ARM::VRSHRsv8i16:
case ARM::VRSHRsv8i8:
case ARM::VRSHRuv16i8:
case ARM::VRSHRuv1i64:
case ARM::VRSHRuv2i32:
case ARM::VRSHRuv2i64:
case ARM::VRSHRuv4i16:
case ARM::VRSHRuv4i32:
case ARM::VRSHRuv8i16:
case ARM::VRSHRuv8i8:
case ARM::VRSUBHNv2i32:
case ARM::VRSUBHNv4i16:
case ARM::VRSUBHNv8i8:
case ARM::VSHLLi16:
case ARM::VSHLLi32:
case ARM::VSHLLi8:
case ARM::VSHLLsv2i64:
case ARM::VSHLLsv4i32:
case ARM::VSHLLsv8i16:
case ARM::VSHLLuv2i64:
case ARM::VSHLLuv4i32:
case ARM::VSHLLuv8i16:
case ARM::VSHLiv16i8:
case ARM::VSHLiv1i64:
case ARM::VSHLiv2i32:
case ARM::VSHLiv2i64:
case ARM::VSHLiv4i16:
case ARM::VSHLiv4i32:
case ARM::VSHLiv8i16:
case ARM::VSHLiv8i8:
case ARM::VSHLsv16i8:
case ARM::VSHLsv1i64:
case ARM::VSHLsv2i32:
case ARM::VSHLsv2i64:
case ARM::VSHLsv4i16:
case ARM::VSHLsv4i32:
case ARM::VSHLsv8i16:
case ARM::VSHLsv8i8:
case ARM::VSHLuv16i8:
case ARM::VSHLuv1i64:
case ARM::VSHLuv2i32:
case ARM::VSHLuv2i64:
case ARM::VSHLuv4i16:
case ARM::VSHLuv4i32:
case ARM::VSHLuv8i16:
case ARM::VSHLuv8i8:
case ARM::VSHRNv2i32:
case ARM::VSHRNv4i16:
case ARM::VSHRNv8i8:
case ARM::VSHRsv16i8:
case ARM::VSHRsv1i64:
case ARM::VSHRsv2i32:
case ARM::VSHRsv2i64:
case ARM::VSHRsv4i16:
case ARM::VSHRsv4i32:
case ARM::VSHRsv8i16:
case ARM::VSHRsv8i8:
case ARM::VSHRuv16i8:
case ARM::VSHRuv1i64:
case ARM::VSHRuv2i32:
case ARM::VSHRuv2i64:
case ARM::VSHRuv4i16:
case ARM::VSHRuv4i32:
case ARM::VSHRuv8i16:
case ARM::VSHRuv8i8:
case ARM::VSUBHNv2i32:
case ARM::VSUBHNv4i16:
case ARM::VSUBHNv8i8:
case ARM::VSUBLsv2i64:
case ARM::VSUBLsv4i32:
case ARM::VSUBLsv8i16:
case ARM::VSUBLuv2i64:
case ARM::VSUBLuv4i32:
case ARM::VSUBLuv8i16:
case ARM::VSUBWsv2i64:
case ARM::VSUBWsv4i32:
case ARM::VSUBWsv8i16:
case ARM::VSUBWuv2i64:
case ARM::VSUBWuv4i32:
case ARM::VSUBWuv8i16:
case ARM::VSUBv16i8:
case ARM::VSUBv1i64:
case ARM::VSUBv2i32:
case ARM::VSUBv2i64:
case ARM::VSUBv4i16:
case ARM::VSUBv4i32:
case ARM::VSUBv8i16:
case ARM::VSUBv8i8:
case ARM::t2ADCSri:
case ARM::t2ADCSrr:
case ARM::t2LDRDpci:
case ARM::t2MOVTi16:
case ARM::t2SBCSri:
case ARM::t2SBCSrr:
case ARM::t2SUBrSPi12_:
case ARM::t2SUBrSPi_:
case ARM::tADDhirr:
case ARM::tMOVCCi:
case ARM::tMOVCCr: printOperand(MI, 2); break;
case ARM::ADCSSrs:
case ARM::MOVCCs:
case ARM::RSCSrs:
case ARM::SBCSSrs: printSORegOperand(MI, 2); break;
case ARM::BFC:
case ARM::t2BFC: printBitfieldInvMaskImmOperand(MI, 2); break;
case ARM::CLZ:
case ARM::CMNzrr:
case ARM::CMPrr:
case ARM::CMPzrr:
case ARM::MOVi16:
case ARM::RBIT:
case ARM::REV:
case ARM::REV16:
case ARM::REVSH:
case ARM::SXTBr:
case ARM::SXTHr:
case ARM::TEQrr:
case ARM::TSTrr:
case ARM::UXTB16r:
case ARM::UXTBr:
case ARM::UXTHr:
case ARM::VCNTd:
case ARM::VCNTq:
case ARM::VDUP16d:
case ARM::VDUP16q:
case ARM::VDUP32d:
case ARM::VDUP32q:
case ARM::VDUP8d:
case ARM::VDUP8q:
case ARM::VDUPfd:
case ARM::VDUPfq:
case ARM::VMOVDneon:
case ARM::VMOVQ:
case ARM::VMOVRS:
case ARM::VMOVSR:
case ARM::VMVNd:
case ARM::VMVNq:
case ARM::VREV16d8:
case ARM::VREV16q8:
case ARM::VREV32d16:
case ARM::VREV32d8:
case ARM::VREV32q16:
case ARM::VREV32q8:
case ARM::VREV64d16:
case ARM::VREV64d32:
case ARM::VREV64d8:
case ARM::VREV64df:
case ARM::VREV64q16:
case ARM::VREV64q32:
case ARM::VREV64q8:
case ARM::VREV64qf:
case ARM::VTRNd16:
case ARM::VTRNd32:
case ARM::VTRNd8:
case ARM::VTRNq16:
case ARM::VTRNq32:
case ARM::VTRNq8:
case ARM::VUZPd16:
case ARM::VUZPd32:
case ARM::VUZPd8:
case ARM::VUZPq16:
case ARM::VUZPq32:
case ARM::VUZPq8:
case ARM::VZIPd16:
case ARM::VZIPd32:
case ARM::VZIPd8:
case ARM::VZIPq16:
case ARM::VZIPq32:
case ARM::VZIPq8:
case ARM::t2CLZ:
case ARM::t2MOVi16:
case ARM::t2RBIT:
case ARM::tCMNz:
case ARM::tCMPhir:
case ARM::tCMPi8:
case ARM::tCMPr:
case ARM::tCMPzhir:
case ARM::tCMPzi8:
case ARM::tCMPzr:
case ARM::tLDRcp:
case ARM::tREV:
case ARM::tREV16:
case ARM::tREVSH:
case ARM::tSXTB:
case ARM::tSXTH:
case ARM::tTST:
case ARM::tUXTB:
case ARM::tUXTH: printOperand(MI, 1); break;
case ARM::CMNzri:
case ARM::CMPri:
case ARM::CMPzri:
case ARM::TEQri:
case ARM::TSTri: printSOImmOperand(MI, 1); break;
case ARM::CMNzrs:
case ARM::CMPrs:
case ARM::CMPzrs:
case ARM::TEQrs:
case ARM::TSTrs: printSORegOperand(MI, 1); break;
case ARM::LDR:
case ARM::LDRB:
case ARM::LDRcp:
case ARM::STR:
case ARM::STRB: printAddrMode2Operand(MI, 1); break;
case ARM::LDRD:
case ARM::STRD: printAddrMode3Operand(MI, 2); break;
case ARM::LDRH:
case ARM::LDRSB:
case ARM::LDRSH:
case ARM::STRH: printAddrMode3Operand(MI, 1); break;
case ARM::MOVi2pieces: printSOImm2PartOperand(MI, 1); break;
case ARM::VABALsv2i64:
case ARM::VABALsv4i32:
case ARM::VABALsv8i16:
case ARM::VABALuv2i64:
case ARM::VABALuv4i32:
case ARM::VABALuv8i16:
case ARM::VABAsv16i8:
case ARM::VABAsv2i32:
case ARM::VABAsv4i16:
case ARM::VABAsv4i32:
case ARM::VABAsv8i16:
case ARM::VABAsv8i8:
case ARM::VABAuv16i8:
case ARM::VABAuv2i32:
case ARM::VABAuv4i16:
case ARM::VABAuv4i32:
case ARM::VABAuv8i16:
case ARM::VABAuv8i8:
case ARM::VMLALsv2i64:
case ARM::VMLALsv4i32:
case ARM::VMLALsv8i16:
case ARM::VMLALuv2i64:
case ARM::VMLALuv4i32:
case ARM::VMLALuv8i16:
case ARM::VMLAv16i8:
case ARM::VMLAv2i32:
case ARM::VMLAv4i16:
case ARM::VMLAv4i32:
case ARM::VMLAv8i16:
case ARM::VMLAv8i8:
case ARM::VMLSLsv2i64:
case ARM::VMLSLsv4i32:
case ARM::VMLSLsv8i16:
case ARM::VMLSLuv2i64:
case ARM::VMLSLuv4i32:
case ARM::VMLSLuv8i16:
case ARM::VMLSv16i8:
case ARM::VMLSv2i32:
case ARM::VMLSv4i16:
case ARM::VMLSv4i32:
case ARM::VMLSv8i16:
case ARM::VMLSv8i8:
case ARM::VQDMLALv2i64:
case ARM::VQDMLALv4i32:
case ARM::VQDMLSLv2i64:
case ARM::VQDMLSLv4i32:
case ARM::VRSRAsv16i8:
case ARM::VRSRAsv1i64:
case ARM::VRSRAsv2i32:
case ARM::VRSRAsv2i64:
case ARM::VRSRAsv4i16:
case ARM::VRSRAsv4i32:
case ARM::VRSRAsv8i16:
case ARM::VRSRAsv8i8:
case ARM::VRSRAuv16i8:
case ARM::VRSRAuv1i64:
case ARM::VRSRAuv2i32:
case ARM::VRSRAuv2i64:
case ARM::VRSRAuv4i16:
case ARM::VRSRAuv4i32:
case ARM::VRSRAuv8i16:
case ARM::VRSRAuv8i8:
case ARM::VSRAsv16i8:
case ARM::VSRAsv1i64:
case ARM::VSRAsv2i32:
case ARM::VSRAsv2i64:
case ARM::VSRAsv4i16:
case ARM::VSRAsv4i32:
case ARM::VSRAsv8i16:
case ARM::VSRAsv8i8:
case ARM::VSRAuv16i8:
case ARM::VSRAuv1i64:
case ARM::VSRAuv2i32:
case ARM::VSRAuv2i64:
case ARM::VSRAuv4i16:
case ARM::VSRAuv4i32:
case ARM::VSRAuv8i16:
case ARM::VSRAuv8i8:
case ARM::tADDi3:
case ARM::tADDrr:
case ARM::tASRri:
case ARM::tLSLri:
case ARM::tLSRri:
case ARM::tSUBi3:
case ARM::tSUBrr: printOperand(MI, 3); break;
case ARM::VDUPfdf:
case ARM::VDUPfqf: printOperand(MI, 1, "lane"); break;
case ARM::VLDRD:
case ARM::VLDRS:
case ARM::VSTRD:
case ARM::VSTRS: printAddrMode5Operand(MI, 1); break;
case ARM::t2ADCSrs:
case ARM::t2SBCSrs:
case ARM::t2SUBrSPs_: printT2SOOperand(MI, 2); break;
case ARM::t2LDRBi8:
case ARM::t2LDRHi8:
case ARM::t2LDRSBi8:
case ARM::t2LDRSHi8:
case ARM::t2LDRi8:
case ARM::t2STRBi8:
case ARM::t2STRHi8:
case ARM::t2STRi8: printT2AddrModeImm8Operand(MI, 1); break;
case ARM::t2LDRDi8:
case ARM::t2STRDi8: printT2AddrModeImm8s4Operand(MI, 2); break;
case ARM::tADDrSPi: printThumbS4ImmOperand(MI, 2); break;
case ARM::tLDR:
case ARM::tLDRi:
case ARM::tSTR:
case ARM::tSTRi: printThumbAddrModeS4Operand(MI, 1); break;
case ARM::tLDRB:
case ARM::tLDRBi:
case ARM::tSTRB:
case ARM::tSTRBi: printThumbAddrModeS1Operand(MI, 1); break;
case ARM::tLDRH:
case ARM::tLDRHi:
case ARM::tSTRH:
case ARM::tSTRHi: printThumbAddrModeS2Operand(MI, 1); break;
case ARM::tLDRSB:
case ARM::tLDRSH: printThumbAddrModeRROperand(MI, 1); break;
case ARM::tLDRspi:
case ARM::tRestore:
case ARM::tSTRspi:
case ARM::tSpill: printThumbAddrModeSPOperand(MI, 1); break;
}
return;
break;
case ARM::ADCrr:
case ARM::ADDrr:
case ARM::ANDrr:
case ARM::BICrr:
case ARM::BKPT:
case ARM::BXJ:
case ARM::Bcc:
case ARM::DBG:
case ARM::EORrr:
case ARM::MOVr:
case ARM::MUL:
case ARM::MVNr:
case ARM::ORRrr:
case ARM::SBCrr:
case ARM::SUBrr:
case ARM::SVC:
case ARM::VABSv16i8:
case ARM::VABSv2i32:
case ARM::VABSv4i16:
case ARM::VABSv4i32:
case ARM::VABSv8i16:
case ARM::VABSv8i8:
case ARM::VCLSv16i8:
case ARM::VCLSv2i32:
case ARM::VCLSv4i16:
case ARM::VCLSv4i32:
case ARM::VCLSv8i16:
case ARM::VCLSv8i8:
case ARM::VCLZv16i8:
case ARM::VCLZv2i32:
case ARM::VCLZv4i16:
case ARM::VCLZv4i32:
case ARM::VCLZv8i16:
case ARM::VCLZv8i8:
case ARM::VMOVLsv2i64:
case ARM::VMOVLsv4i32:
case ARM::VMOVLsv8i16:
case ARM::VMOVLuv2i64:
case ARM::VMOVLuv4i32:
case ARM::VMOVLuv8i16:
case ARM::VMOVNv2i32:
case ARM::VMOVNv4i16:
case ARM::VMOVNv8i8:
case ARM::VNEGs16d:
case ARM::VNEGs16q:
case ARM::VNEGs32d:
case ARM::VNEGs32q:
case ARM::VNEGs8d:
case ARM::VNEGs8q:
case ARM::VPADALsv16i8:
case ARM::VPADALsv2i32:
case ARM::VPADALsv4i16:
case ARM::VPADALsv4i32:
case ARM::VPADALsv8i16:
case ARM::VPADALsv8i8:
case ARM::VPADALuv16i8:
case ARM::VPADALuv2i32:
case ARM::VPADALuv4i16:
case ARM::VPADALuv4i32:
case ARM::VPADALuv8i16:
case ARM::VPADALuv8i8:
case ARM::VPADDLsv16i8:
case ARM::VPADDLsv2i32:
case ARM::VPADDLsv4i16:
case ARM::VPADDLsv4i32:
case ARM::VPADDLsv8i16:
case ARM::VPADDLsv8i8:
case ARM::VPADDLuv16i8:
case ARM::VPADDLuv2i32:
case ARM::VPADDLuv4i16:
case ARM::VPADDLuv4i32:
case ARM::VPADDLuv8i16:
case ARM::VPADDLuv8i8:
case ARM::VQABSv16i8:
case ARM::VQABSv2i32:
case ARM::VQABSv4i16:
case ARM::VQABSv4i32:
case ARM::VQABSv8i16:
case ARM::VQABSv8i8:
case ARM::VQMOVNsuv2i32:
case ARM::VQMOVNsuv4i16:
case ARM::VQMOVNsuv8i8:
case ARM::VQMOVNsv2i32:
case ARM::VQMOVNsv4i16:
case ARM::VQMOVNsv8i8:
case ARM::VQMOVNuv2i32:
case ARM::VQMOVNuv4i16:
case ARM::VQMOVNuv8i8:
case ARM::VQNEGv16i8:
case ARM::VQNEGv2i32:
case ARM::VQNEGv4i16:
case ARM::VQNEGv4i32:
case ARM::VQNEGv8i16:
case ARM::VQNEGv8i8:
case ARM::VRECPEd:
case ARM::VRECPEq:
case ARM::VRSQRTEd:
case ARM::VRSQRTEq:
case ARM::t2LEApcrel:
case ARM::tADDrSP:
case ARM::tADDspr:
case ARM::tADDspr_:
case ARM::tANDsp:
case ARM::tBcc:
case ARM::tCBNZ:
case ARM::tCBZ:
case ARM::tMOVSr:
case ARM::tMOVgpr2gpr:
case ARM::tMOVgpr2tgpr:
case ARM::tMOVr:
case ARM::tMOVtgpr2gpr:
return;
break;
case ARM::ADDSri:
case ARM::ADDSrr:
case ARM::ADDSrs:
case ARM::QADD:
case ARM::QADD16:
case ARM::QADD8:
case ARM::QASX:
case ARM::QDADD:
case ARM::QDSUB:
case ARM::QSAX:
case ARM::QSUB:
case ARM::QSUB16:
case ARM::QSUB8:
case ARM::RSBSri:
case ARM::RSBSrs:
case ARM::SMMUL:
case ARM::SMULBB:
case ARM::SMULBT:
case ARM::SMULTB:
case ARM::SMULTT:
case ARM::SMULWB:
case ARM::SMULWT:
case ARM::SUBSri:
case ARM::SUBSrr:
case ARM::SUBSrs:
case ARM::SXTABrr:
case ARM::SXTAHrr:
case ARM::UQADD16:
case ARM::UQADD8:
case ARM::UQASX:
case ARM::UQSAX:
case ARM::UQSUB16:
case ARM::UQSUB8:
case ARM::UXTABrr:
case ARM::UXTAHrr:
case ARM::VANDd:
case ARM::VANDq:
case ARM::VBICd:
case ARM::VBICq:
case ARM::VEORd:
case ARM::VEORq:
case ARM::VMOVDRR:
case ARM::VMOVRRD:
case ARM::VORNd:
case ARM::VORNq:
case ARM::VORRd:
case ARM::VORRq:
case ARM::VTSTv16i8:
case ARM::VTSTv2i32:
case ARM::VTSTv4i16:
case ARM::VTSTv4i32:
case ARM::VTSTv8i16:
case ARM::VTSTv8i8:
case ARM::t2ADCri:
case ARM::t2ADDrSPi12:
case ARM::t2ADDri12:
case ARM::t2ANDri:
case ARM::t2BICri:
case ARM::t2EORri:
case ARM::t2MUL:
case ARM::t2ORNri:
case ARM::t2ORNrr:
case ARM::t2ORNrs:
case ARM::t2ORRri:
case ARM::t2RSBSrs:
case ARM::t2RSBrs:
case ARM::t2SBCri:
case ARM::t2SMMUL:
case ARM::t2SMULBB:
case ARM::t2SMULBT:
case ARM::t2SMULTB:
case ARM::t2SMULTT:
case ARM::t2SMULWB:
case ARM::t2SMULWT:
case ARM::t2SUBrSPi12:
case ARM::t2SUBrSPs:
case ARM::t2SUBri12:
case ARM::t2SXTABrr:
case ARM::t2SXTAHrr:
case ARM::t2UXTABrr:
case ARM::t2UXTAHrr:
O << ", ";
printOperand(MI, 1);
O << ", ";
switch (MI->getOpcode()) {
case ARM::ADDSri:
case ARM::RSBSri:
case ARM::SUBSri: printSOImmOperand(MI, 2); break;
case ARM::ADDSrr:
case ARM::QADD:
case ARM::QADD16:
case ARM::QADD8:
case ARM::QASX:
case ARM::QDADD:
case ARM::QDSUB:
case ARM::QSAX:
case ARM::QSUB:
case ARM::QSUB16:
case ARM::QSUB8:
case ARM::SMMUL:
case ARM::SMULBB:
case ARM::SMULBT:
case ARM::SMULTB:
case ARM::SMULTT:
case ARM::SMULWB:
case ARM::SMULWT:
case ARM::SUBSrr:
case ARM::SXTABrr:
case ARM::SXTAHrr:
case ARM::UQADD16:
case ARM::UQADD8:
case ARM::UQASX:
case ARM::UQSAX:
case ARM::UQSUB16:
case ARM::UQSUB8:
case ARM::UXTABrr:
case ARM::UXTAHrr:
case ARM::VANDd:
case ARM::VANDq:
case ARM::VBICd:
case ARM::VBICq:
case ARM::VEORd:
case ARM::VEORq:
case ARM::VMOVDRR:
case ARM::VMOVRRD:
case ARM::VORNd:
case ARM::VORNq:
case ARM::VORRd:
case ARM::VORRq:
case ARM::VTSTv16i8:
case ARM::VTSTv2i32:
case ARM::VTSTv4i16:
case ARM::VTSTv4i32:
case ARM::VTSTv8i16:
case ARM::VTSTv8i8:
case ARM::t2ADCri:
case ARM::t2ADDrSPi12:
case ARM::t2ADDri12:
case ARM::t2ANDri:
case ARM::t2BICri:
case ARM::t2EORri:
case ARM::t2MUL:
case ARM::t2ORNri:
case ARM::t2ORNrr:
case ARM::t2ORRri:
case ARM::t2SBCri:
case ARM::t2SMMUL:
case ARM::t2SMULBB:
case ARM::t2SMULBT:
case ARM::t2SMULTB:
case ARM::t2SMULTT:
case ARM::t2SMULWB:
case ARM::t2SMULWT:
case ARM::t2SUBrSPi12:
case ARM::t2SUBri12:
case ARM::t2SXTABrr:
case ARM::t2SXTAHrr:
case ARM::t2UXTABrr:
case ARM::t2UXTAHrr: printOperand(MI, 2); break;
case ARM::ADDSrs:
case ARM::RSBSrs:
case ARM::SUBSrs: printSORegOperand(MI, 2); break;
case ARM::t2ORNrs:
case ARM::t2RSBSrs:
case ARM::t2RSBrs:
case ARM::t2SUBrSPs: printT2SOOperand(MI, 2); break;
}
return;
break;
case ARM::BR_JTadd:
O << " \n";
printJTBlockOperand(MI, 2);
return;
break;
case ARM::FCONSTD:
case ARM::FCONSTS:
case ARM::MOVrx:
case ARM::MRS:
case ARM::MRSsys:
case ARM::VABSD:
case ARM::VABSS:
case ARM::VABSfd:
case ARM::VABSfd_sfp:
case ARM::VABSfq:
case ARM::VCMPD:
case ARM::VCMPED:
case ARM::VCMPES:
case ARM::VCMPS:
case ARM::VCVTf2xsd:
case ARM::VCVTf2xsq:
case ARM::VCVTf2xud:
case ARM::VCVTf2xuq:
case ARM::VCVTxs2fd:
case ARM::VCVTxs2fq:
case ARM::VCVTxu2fd:
case ARM::VCVTxu2fq:
case ARM::VMOVD:
case ARM::VMOVDcc:
case ARM::VMOVS:
case ARM::VMOVScc:
case ARM::VMRS:
case ARM::VNEGD:
case ARM::VNEGDcc:
case ARM::VNEGS:
case ARM::VNEGScc:
case ARM::VNEGf32d:
case ARM::VNEGf32d_sfp:
case ARM::VNEGf32q:
case ARM::VRECPEfd:
case ARM::VRECPEfq:
case ARM::VRSQRTEfd:
case ARM::VRSQRTEfq:
case ARM::VSLTOD:
case ARM::VSLTOS:
case ARM::VSQRTD:
case ARM::VSQRTS:
case ARM::VTOSLD:
case ARM::VTOSLS:
case ARM::VTOULD:
case ARM::VTOULS:
case ARM::VULTOD:
case ARM::VULTOS:
case ARM::t2CMNzri:
case ARM::t2CMNzrr:
case ARM::t2CMNzrs:
case ARM::t2CMPri:
case ARM::t2CMPrr:
case ARM::t2CMPrs:
case ARM::t2CMPzri:
case ARM::t2CMPzrr:
case ARM::t2CMPzrs:
case ARM::t2LDRBi12:
case ARM::t2LDRBpci:
case ARM::t2LDRBs:
case ARM::t2LDRHi12:
case ARM::t2LDRHpci:
case ARM::t2LDRHs:
case ARM::t2LDRSBi12:
case ARM::t2LDRSBpci:
case ARM::t2LDRSBs:
case ARM::t2LDRSHi12:
case ARM::t2LDRSHpci:
case ARM::t2LDRSHs:
case ARM::t2LDRi12:
case ARM::t2LDRpci:
case ARM::t2LDRs:
case ARM::t2MOVCCi:
case ARM::t2MOVCCr:
case ARM::t2MOVsra_flag:
case ARM::t2MOVsrl_flag:
case ARM::t2MVNr:
case ARM::t2MVNs:
case ARM::t2REV:
case ARM::t2REV16:
case ARM::t2REVSH:
case ARM::t2STRBi12:
case ARM::t2STRBs:
case ARM::t2STRHi12:
case ARM::t2STRHs:
case ARM::t2STRi12:
case ARM::t2STRs:
case ARM::t2SXTBr:
case ARM::t2SXTHr:
case ARM::t2TEQri:
case ARM::t2TEQrr:
case ARM::t2TEQrs:
case ARM::t2TSTri:
case ARM::t2TSTrr:
case ARM::t2TSTrs:
case ARM::t2UXTB16r:
case ARM::t2UXTBr:
case ARM::t2UXTHr:
switch (MI->getOpcode()) {
case ARM::FCONSTD: printVFPf64ImmOperand(MI, 1); break;
case ARM::FCONSTS: printVFPf32ImmOperand(MI, 1); break;
case ARM::MOVrx: O << ", rrx"; break;
case ARM::MRS: O << ", cpsr"; break;
case ARM::MRSsys: O << ", spsr"; break;
case ARM::VABSD:
case ARM::VABSS:
case ARM::VABSfd:
case ARM::VABSfd_sfp:
case ARM::VABSfq:
case ARM::VCMPD:
case ARM::VCMPED:
case ARM::VCMPES:
case ARM::VCMPS:
case ARM::VMOVD:
case ARM::VMOVS:
case ARM::VNEGD:
case ARM::VNEGS:
case ARM::VNEGf32d:
case ARM::VNEGf32d_sfp:
case ARM::VNEGf32q:
case ARM::VRECPEfd:
case ARM::VRECPEfq:
case ARM::VRSQRTEfd:
case ARM::VRSQRTEfq:
case ARM::VSQRTD:
case ARM::VSQRTS:
case ARM::t2CMNzri:
case ARM::t2CMNzrr:
case ARM::t2CMPri:
case ARM::t2CMPrr:
case ARM::t2CMPzri:
case ARM::t2CMPzrr:
case ARM::t2LDRBpci:
case ARM::t2LDRHpci:
case ARM::t2LDRSBpci:
case ARM::t2LDRSHpci:
case ARM::t2LDRpci:
case ARM::t2MVNr:
case ARM::t2REV:
case ARM::t2REV16:
case ARM::t2REVSH:
case ARM::t2SXTBr:
case ARM::t2SXTHr:
case ARM::t2TEQri:
case ARM::t2TEQrr:
case ARM::t2TSTri:
case ARM::t2TSTrr:
case ARM::t2UXTB16r:
case ARM::t2UXTBr:
case ARM::t2UXTHr: printOperand(MI, 1); break;
case ARM::VCVTf2xsd:
case ARM::VCVTf2xsq:
case ARM::VCVTf2xud:
case ARM::VCVTf2xuq:
case ARM::VCVTxs2fd:
case ARM::VCVTxs2fq:
case ARM::VCVTxu2fd:
case ARM::VCVTxu2fq:
case ARM::VMOVDcc:
case ARM::VMOVScc:
case ARM::VNEGDcc:
case ARM::VNEGScc:
case ARM::VSLTOD:
case ARM::VSLTOS:
case ARM::VTOSLD:
case ARM::VTOSLS:
case ARM::VTOULD:
case ARM::VTOULS:
case ARM::VULTOD:
case ARM::VULTOS:
case ARM::t2MOVCCi:
case ARM::t2MOVCCr: printOperand(MI, 2); break;
case ARM::VMRS: O << ", fpscr"; break;
case ARM::t2CMNzrs:
case ARM::t2CMPrs:
case ARM::t2CMPzrs:
case ARM::t2MVNs:
case ARM::t2TEQrs:
case ARM::t2TSTrs: printT2SOOperand(MI, 1); break;
case ARM::t2LDRBi12:
case ARM::t2LDRHi12:
case ARM::t2LDRSBi12:
case ARM::t2LDRSHi12:
case ARM::t2LDRi12:
case ARM::t2STRBi12:
case ARM::t2STRHi12:
case ARM::t2STRi12: printT2AddrModeImm12Operand(MI, 1); break;
case ARM::t2LDRBs:
case ARM::t2LDRHs:
case ARM::t2LDRSBs:
case ARM::t2LDRSHs:
case ARM::t2LDRs:
case ARM::t2STRBs:
case ARM::t2STRHs:
case ARM::t2STRs: printT2AddrModeSoRegOperand(MI, 1); break;
case ARM::t2MOVsra_flag:
case ARM::t2MOVsrl_flag: O << ", #1"; break;
}
return;
break;
case ARM::LDRBT:
case ARM::LDRB_POST:
case ARM::LDRH_POST:
case ARM::LDRSB_POST:
case ARM::LDRSH_POST:
case ARM::LDRT:
case ARM::LDR_POST:
case ARM::STRBT:
case ARM::STRB_POST:
case ARM::STRH_POST:
case ARM::STRT:
case ARM::STR_POST:
case ARM::t2LDRB_POST:
case ARM::t2LDRH_POST:
case ARM::t2LDRSB_POST:
case ARM::t2LDRSH_POST:
case ARM::t2LDR_POST:
case ARM::t2STRB_POST:
case ARM::t2STRH_POST:
case ARM::t2STR_POST:
O << ", [";
printOperand(MI, 2);
O << "], ";
switch (MI->getOpcode()) {
case ARM::LDRBT:
case ARM::LDRB_POST:
case ARM::LDRT:
case ARM::LDR_POST:
case ARM::STRBT:
case ARM::STRB_POST:
case ARM::STRT:
case ARM::STR_POST: printAddrMode2OffsetOperand(MI, 3); break;
case ARM::LDRH_POST:
case ARM::LDRSB_POST:
case ARM::LDRSH_POST:
case ARM::STRH_POST: printAddrMode3OffsetOperand(MI, 3); break;
case ARM::t2LDRB_POST:
case ARM::t2LDRH_POST:
case ARM::t2LDRSB_POST:
case ARM::t2LDRSH_POST:
case ARM::t2LDR_POST:
case ARM::t2STRB_POST:
case ARM::t2STRH_POST:
case ARM::t2STR_POST: printT2AddrModeImm8OffsetOperand(MI, 3); break;
}
return;
break;
case ARM::LDRB_PRE:
case ARM::LDRH_PRE:
case ARM::LDRSB_PRE:
case ARM::LDRSH_PRE:
case ARM::LDR_PRE:
case ARM::t2LDRB_PRE:
case ARM::t2LDRH_PRE:
case ARM::t2LDRSB_PRE:
case ARM::t2LDRSH_PRE:
case ARM::t2LDR_PRE:
O << ", ";
switch (MI->getOpcode()) {
case ARM::LDRB_PRE:
case ARM::LDR_PRE: printAddrMode2Operand(MI, 2); break;
case ARM::LDRH_PRE:
case ARM::LDRSB_PRE:
case ARM::LDRSH_PRE: printAddrMode3Operand(MI, 2); break;
case ARM::t2LDRB_PRE:
case ARM::t2LDRH_PRE:
case ARM::t2LDRSB_PRE:
case ARM::t2LDRSH_PRE:
case ARM::t2LDR_PRE: printT2AddrModeImm8Operand(MI, 2); break;
}
O << '!';
return;
break;
case ARM::LDREX:
case ARM::LDREXB:
case ARM::LDREXH:
case ARM::t2LDREX:
case ARM::t2LDREXB:
case ARM::t2LDREXH:
O << ", [";
printOperand(MI, 1);
O << ']';
return;
break;
case ARM::LDREXD:
case ARM::STREX:
case ARM::STREXB:
case ARM::STREXH:
case ARM::SWP:
case ARM::SWPB:
case ARM::t2LDREXD:
case ARM::t2STREX:
case ARM::t2STREXB:
case ARM::t2STREXH:
O << ", ";
printOperand(MI, 1);
O << ", [";
printOperand(MI, 2);
O << ']';
return;
break;
case ARM::MCR:
case ARM::MRC:
printOperand(MI, 2);
O << ", cr";
printNoHashImmediate(MI, 3);
O << ", cr";
printNoHashImmediate(MI, 4);
O << ", ";
printOperand(MI, 5);
return;
break;
case ARM::MCR2:
case ARM::MRC2:
O << ", cr";
printNoHashImmediate(MI, 3);
O << ", cr";
printNoHashImmediate(MI, 4);
O << ", ";
printOperand(MI, 5);
return;
break;
case ARM::MCRR:
case ARM::MRRC:
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << ", cr";
printNoHashImmediate(MI, 4);
return;
break;
case ARM::MCRR2:
case ARM::MRRC2:
O << ", ";
printOperand(MI, 3);
O << ", cr";
printNoHashImmediate(MI, 4);
return;
break;
case ARM::MLA:
case ARM::SMLAL:
case ARM::SMULL:
case ARM::UMLAL:
case ARM::UMULL:
case ARM::VBIFd:
case ARM::VBIFq:
case ARM::VBITd:
case ARM::VBITq:
case ARM::VBSLd:
case ARM::VBSLq:
case ARM::VSLIv16i8:
case ARM::VSLIv1i64:
case ARM::VSLIv2i32:
case ARM::VSLIv2i64:
case ARM::VSLIv4i16:
case ARM::VSLIv4i32:
case ARM::VSLIv8i16:
case ARM::VSLIv8i8:
case ARM::VSRIv16i8:
case ARM::VSRIv1i64:
case ARM::VSRIv2i32:
case ARM::VSRIv2i64:
case ARM::VSRIv4i16:
case ARM::VSRIv4i32:
case ARM::VSRIv8i16:
case ARM::VSRIv8i8:
O << ", ";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
return;
break;
case ARM::MLS:
case ARM::PKHBT:
case ARM::PKHTB:
case ARM::SBFX:
case ARM::SMLABB:
case ARM::SMLABT:
case ARM::SMLALBB:
case ARM::SMLALBT:
case ARM::SMLALTB:
case ARM::SMLALTT:
case ARM::SMLATB:
case ARM::SMLATT:
case ARM::SMLAWB:
case ARM::SMLAWT:
case ARM::SMMLA:
case ARM::SMMLS:
case ARM::SXTABrr_rot:
case ARM::SXTAHrr_rot:
case ARM::UBFX:
case ARM::UMAAL:
case ARM::UXTABrr_rot:
case ARM::UXTAHrr_rot:
case ARM::VEXTd16:
case ARM::VEXTd32:
case ARM::VEXTd8:
case ARM::VEXTdf:
case ARM::VEXTq16:
case ARM::VEXTq32:
case ARM::VEXTq8:
case ARM::VEXTqf:
case ARM::VMOVRRS:
case ARM::VMOVSRR:
case ARM::t2BFI:
case ARM::t2MLA:
case ARM::t2MLS:
case ARM::t2PKHBT:
case ARM::t2PKHTB:
case ARM::t2SBFX:
case ARM::t2SMLABB:
case ARM::t2SMLABT:
case ARM::t2SMLAL:
case ARM::t2SMLATB:
case ARM::t2SMLATT:
case ARM::t2SMLAWB:
case ARM::t2SMLAWT:
case ARM::t2SMMLA:
case ARM::t2SMMLS:
case ARM::t2SMULL:
case ARM::t2SXTABrr_rot:
case ARM::t2SXTAHrr_rot:
case ARM::t2UBFX:
case ARM::t2UMAAL:
case ARM::t2UMLAL:
case ARM::t2UMULL:
case ARM::t2UXTABrr_rot:
case ARM::t2UXTAHrr_rot:
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
switch (MI->getOpcode()) {
case ARM::MLS:
case ARM::SBFX:
case ARM::SMLABB:
case ARM::SMLABT:
case ARM::SMLALBB:
case ARM::SMLALBT:
case ARM::SMLALTB:
case ARM::SMLALTT:
case ARM::SMLATB:
case ARM::SMLATT:
case ARM::SMLAWB:
case ARM::SMLAWT:
case ARM::SMMLA:
case ARM::SMMLS:
case ARM::UBFX:
case ARM::UMAAL:
case ARM::VEXTd16:
case ARM::VEXTd32:
case ARM::VEXTd8:
case ARM::VEXTdf:
case ARM::VEXTq16:
case ARM::VEXTq32:
case ARM::VEXTq8:
case ARM::VEXTqf:
case ARM::VMOVRRS:
case ARM::VMOVSRR:
case ARM::t2BFI:
case ARM::t2MLA:
case ARM::t2MLS:
case ARM::t2SBFX:
case ARM::t2SMLABB:
case ARM::t2SMLABT:
case ARM::t2SMLAL:
case ARM::t2SMLATB:
case ARM::t2SMLATT:
case ARM::t2SMLAWB:
case ARM::t2SMLAWT:
case ARM::t2SMMLA:
case ARM::t2SMMLS:
case ARM::t2SMULL:
case ARM::t2UBFX:
case ARM::t2UMAAL:
case ARM::t2UMLAL:
case ARM::t2UMULL: O << ", "; break;
case ARM::PKHBT:
case ARM::t2PKHBT: O << ", LSL "; break;
case ARM::PKHTB:
case ARM::t2PKHTB: O << ", ASR "; break;
case ARM::SXTABrr_rot:
case ARM::SXTAHrr_rot:
case ARM::UXTABrr_rot:
case ARM::UXTAHrr_rot:
case ARM::t2SXTABrr_rot:
case ARM::t2SXTAHrr_rot:
case ARM::t2UXTABrr_rot:
case ARM::t2UXTAHrr_rot: O << ", ror "; break;
}
printOperand(MI, 3);
return;
break;
case ARM::MOVi32imm:
case ARM::t2MOVi32imm:
O << ", ";
printOperand(MI, 1, "lo16");
O << "\n\tmovt";
printPredicateOperand(MI, 2);
O << "\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1, "hi16");
return;
break;
case ARM::MOVsra_flag:
case ARM::MOVsrl_flag:
O << ", ";
printOperand(MI, 1);
switch (MI->getOpcode()) {
case ARM::MOVsra_flag: O << ", asr #1"; break;
case ARM::MOVsrl_flag: O << ", lsr #1"; break;
}
return;
break;
case ARM::STRB_PRE:
case ARM::STRH_PRE:
case ARM::STR_PRE:
case ARM::t2STRB_PRE:
case ARM::t2STRH_PRE:
case ARM::t2STR_PRE:
O << ", [";
printOperand(MI, 2);
O << ", ";
switch (MI->getOpcode()) {
case ARM::STRB_PRE:
case ARM::STR_PRE: printAddrMode2OffsetOperand(MI, 3); break;
case ARM::STRH_PRE: printAddrMode3OffsetOperand(MI, 3); break;
case ARM::t2STRB_PRE:
case ARM::t2STRH_PRE:
case ARM::t2STR_PRE: printT2AddrModeImm8OffsetOperand(MI, 3); break;
}
O << "]!";
return;
break;
case ARM::STREXD:
case ARM::t2STREXD:
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << ", [";
printOperand(MI, 3);
O << ']';
return;
break;
case ARM::SXTBr_rot:
case ARM::SXTHr_rot:
case ARM::UXTB16r_rot:
case ARM::UXTBr_rot:
case ARM::UXTHr_rot:
O << ", ";
printOperand(MI, 1);
O << ", ror ";
printOperand(MI, 2);
return;
break;
case ARM::VABDfd:
case ARM::VABDfq:
case ARM::VACGEd:
case ARM::VACGEq:
case ARM::VACGTd:
case ARM::VACGTq:
case ARM::VADDD:
case ARM::VADDS:
case ARM::VADDfd:
case ARM::VADDfd_sfp:
case ARM::VADDfq:
case ARM::VCEQfd:
case ARM::VCEQfq:
case ARM::VCGEfd:
case ARM::VCGEfq:
case ARM::VCGTfd:
case ARM::VCGTfq:
case ARM::VDIVD:
case ARM::VDIVS:
case ARM::VMAXfd:
case ARM::VMAXfq:
case ARM::VMINfd:
case ARM::VMINfq:
case ARM::VMULD:
case ARM::VMULS:
case ARM::VMULfd:
case ARM::VMULfd_sfp:
case ARM::VMULfq:
case ARM::VNMULD:
case ARM::VNMULS:
case ARM::VPADDf:
case ARM::VPMAXf:
case ARM::VPMINf:
case ARM::VRECPSfd:
case ARM::VRECPSfq:
case ARM::VRSQRTSfd:
case ARM::VRSQRTSfq:
case ARM::VSUBD:
case ARM::VSUBS:
case ARM::VSUBfd:
case ARM::VSUBfd_sfp:
case ARM::VSUBfq:
case ARM::t2ADCrr:
case ARM::t2ADCrs:
case ARM::t2ADDSri:
case ARM::t2ADDSrr:
case ARM::t2ADDSrs:
case ARM::t2ADDrSPi:
case ARM::t2ADDrSPs:
case ARM::t2ADDri:
case ARM::t2ADDrr:
case ARM::t2ADDrs:
case ARM::t2ANDrr:
case ARM::t2ANDrs:
case ARM::t2ASRri:
case ARM::t2ASRrr:
case ARM::t2BICrr:
case ARM::t2BICrs:
case ARM::t2EORrr:
case ARM::t2EORrs:
case ARM::t2LSLri:
case ARM::t2LSLrr:
case ARM::t2LSRri:
case ARM::t2LSRrr:
case ARM::t2ORRrr:
case ARM::t2ORRrs:
case ARM::t2RORri:
case ARM::t2RORrr:
case ARM::t2RSBri:
case ARM::t2SBCrr:
case ARM::t2SBCrs:
case ARM::t2SUBSri:
case ARM::t2SUBSrr:
case ARM::t2SUBSrs:
case ARM::t2SUBrSPi:
case ARM::t2SUBri:
case ARM::t2SUBrr:
case ARM::t2SUBrs:
printOperand(MI, 1);
O << ", ";
switch (MI->getOpcode()) {
case ARM::VABDfd:
case ARM::VABDfq:
case ARM::VACGEd:
case ARM::VACGEq:
case ARM::VACGTd:
case ARM::VACGTq:
case ARM::VADDD:
case ARM::VADDS:
case ARM::VADDfd:
case ARM::VADDfd_sfp:
case ARM::VADDfq:
case ARM::VCEQfd:
case ARM::VCEQfq:
case ARM::VCGEfd:
case ARM::VCGEfq:
case ARM::VCGTfd:
case ARM::VCGTfq:
case ARM::VDIVD:
case ARM::VDIVS:
case ARM::VMAXfd:
case ARM::VMAXfq:
case ARM::VMINfd:
case ARM::VMINfq:
case ARM::VMULD:
case ARM::VMULS:
case ARM::VMULfd:
case ARM::VMULfd_sfp:
case ARM::VMULfq:
case ARM::VNMULD:
case ARM::VNMULS:
case ARM::VPADDf:
case ARM::VPMAXf:
case ARM::VPMINf:
case ARM::VRECPSfd:
case ARM::VRECPSfq:
case ARM::VRSQRTSfd:
case ARM::VRSQRTSfq:
case ARM::VSUBD:
case ARM::VSUBS:
case ARM::VSUBfd:
case ARM::VSUBfd_sfp:
case ARM::VSUBfq:
case ARM::t2ADCrr:
case ARM::t2ADDSri:
case ARM::t2ADDSrr:
case ARM::t2ADDrSPi:
case ARM::t2ADDri:
case ARM::t2ADDrr:
case ARM::t2ANDrr:
case ARM::t2ASRri:
case ARM::t2ASRrr:
case ARM::t2BICrr:
case ARM::t2EORrr:
case ARM::t2LSLri:
case ARM::t2LSLrr:
case ARM::t2LSRri:
case ARM::t2LSRrr:
case ARM::t2ORRrr:
case ARM::t2RORri:
case ARM::t2RORrr:
case ARM::t2RSBri:
case ARM::t2SBCrr:
case ARM::t2SUBSri:
case ARM::t2SUBSrr:
case ARM::t2SUBrSPi:
case ARM::t2SUBri:
case ARM::t2SUBrr: printOperand(MI, 2); break;
case ARM::t2ADCrs:
case ARM::t2ADDSrs:
case ARM::t2ADDrSPs:
case ARM::t2ADDrs:
case ARM::t2ANDrs:
case ARM::t2BICrs:
case ARM::t2EORrs:
case ARM::t2ORRrs:
case ARM::t2SBCrs:
case ARM::t2SUBSrs:
case ARM::t2SUBrs: printT2SOOperand(MI, 2); break;
}
return;
break;
case ARM::VDUPLN16d:
case ARM::VDUPLN16q:
case ARM::VDUPLN32d:
case ARM::VDUPLN32q:
case ARM::VDUPLN8d:
case ARM::VDUPLN8q:
case ARM::VDUPLNfd:
case ARM::VDUPLNfq:
case ARM::VGETLNi32:
O << ", ";
printOperand(MI, 1);
O << '[';
printNoHashImmediate(MI, 2);
O << ']';
return;
break;
case ARM::VGETLNs16:
case ARM::VGETLNs8:
case ARM::VGETLNu16:
case ARM::VGETLNu8:
O << '[';
printNoHashImmediate(MI, 2);
O << ']';
return;
break;
case ARM::VLD1d16:
case ARM::VLD1d32:
case ARM::VLD1d64:
case ARM::VLD1d8:
case ARM::VLD1df:
case ARM::VST1d16:
case ARM::VST1d32:
case ARM::VST1d64:
case ARM::VST1d8:
case ARM::VST1df:
case ARM::VST3q16a:
case ARM::VST3q16b:
case ARM::VST3q32a:
case ARM::VST3q32b:
case ARM::VST3q8a:
case ARM::VST3q8b:
O << "}, ";
switch (MI->getOpcode()) {
case ARM::VLD1d16:
case ARM::VLD1d32:
case ARM::VLD1d64:
case ARM::VLD1d8:
case ARM::VLD1df:
case ARM::VST3q16a:
case ARM::VST3q16b:
case ARM::VST3q32a:
case ARM::VST3q32b:
case ARM::VST3q8a:
case ARM::VST3q8b: printAddrMode6Operand(MI, 1); break;
case ARM::VST1d16:
case ARM::VST1d32:
case ARM::VST1d64:
case ARM::VST1d8:
case ARM::VST1df: printAddrMode6Operand(MI, 0); break;
}
return;
break;
case ARM::VLD2LNd16:
case ARM::VLD2LNd32:
case ARM::VLD2LNd8:
case ARM::VLD2LNq16a:
case ARM::VLD2LNq16b:
case ARM::VLD2LNq32a:
case ARM::VLD2LNq32b:
O << '[';
printNoHashImmediate(MI, 8);
O << "], ";
printOperand(MI, 1);
O << '[';
printNoHashImmediate(MI, 8);
O << "]}, ";
printAddrMode6Operand(MI, 2);
return;
break;
case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d64:
case ARM::VLD2d8:
O << ", ";
printOperand(MI, 1);
O << "}, ";
printAddrMode6Operand(MI, 2);
return;
break;
case ARM::VLD2q16:
case ARM::VLD2q32:
case ARM::VLD2q8:
case ARM::VLD4d16:
case ARM::VLD4d32:
case ARM::VLD4d64:
case ARM::VLD4d8:
case ARM::VLD4q16a:
case ARM::VLD4q16b:
case ARM::VLD4q32a:
case ARM::VLD4q32b:
case ARM::VLD4q8a:
case ARM::VLD4q8b:
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << "}, ";
switch (MI->getOpcode()) {
case ARM::VLD2q16:
case ARM::VLD2q32:
case ARM::VLD2q8:
case ARM::VLD4d16:
case ARM::VLD4d32:
case ARM::VLD4d64:
case ARM::VLD4d8: printAddrMode6Operand(MI, 4); break;
case ARM::VLD4q16a:
case ARM::VLD4q16b:
case ARM::VLD4q32a:
case ARM::VLD4q32b:
case ARM::VLD4q8a:
case ARM::VLD4q8b: printAddrMode6Operand(MI, 5); break;
}
return;
break;
case ARM::VLD3LNd16:
case ARM::VLD3LNd32:
case ARM::VLD3LNd8:
case ARM::VLD3LNq16a:
case ARM::VLD3LNq16b:
case ARM::VLD3LNq32a:
case ARM::VLD3LNq32b:
O << '[';
printNoHashImmediate(MI, 10);
O << "], ";
printOperand(MI, 1);
O << '[';
printNoHashImmediate(MI, 10);
O << "], ";
printOperand(MI, 2);
O << '[';
printNoHashImmediate(MI, 10);
O << "]}, ";
printAddrMode6Operand(MI, 3);
return;
break;
case ARM::VLD3d16:
case ARM::VLD3d32:
case ARM::VLD3d64:
case ARM::VLD3d8:
case ARM::VLD3q16a:
case ARM::VLD3q16b:
case ARM::VLD3q32a:
case ARM::VLD3q32b:
case ARM::VLD3q8a:
case ARM::VLD3q8b:
O << ", ";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << "}, ";
switch (MI->getOpcode()) {
case ARM::VLD3d16:
case ARM::VLD3d32:
case ARM::VLD3d64:
case ARM::VLD3d8: printAddrMode6Operand(MI, 3); break;
case ARM::VLD3q16a:
case ARM::VLD3q16b:
case ARM::VLD3q32a:
case ARM::VLD3q32b:
case ARM::VLD3q8a:
case ARM::VLD3q8b: printAddrMode6Operand(MI, 4); break;
}
return;
break;
case ARM::VLD4LNd16:
case ARM::VLD4LNd32:
case ARM::VLD4LNd8:
case ARM::VLD4LNq16a:
case ARM::VLD4LNq16b:
case ARM::VLD4LNq32a:
case ARM::VLD4LNq32b:
O << '[';
printNoHashImmediate(MI, 12);
O << "], ";
printOperand(MI, 1);
O << '[';
printNoHashImmediate(MI, 12);
O << "], ";
printOperand(MI, 2);
O << '[';
printNoHashImmediate(MI, 12);
O << "], ";
printOperand(MI, 3);
O << '[';
printNoHashImmediate(MI, 12);
O << "]}, ";
printAddrMode6Operand(MI, 4);
return;
break;
case ARM::VMLAD:
case ARM::VMLAS:
case ARM::VMLAfd:
case ARM::VMLAfq:
case ARM::VMLSD:
case ARM::VMLSS:
case ARM::VMLSfd:
case ARM::VMLSfq:
case ARM::VNMLAD:
case ARM::VNMLAS:
case ARM::VNMLSD:
case ARM::VNMLSS:
case ARM::t2MOVCCasr:
case ARM::t2MOVCClsl:
case ARM::t2MOVCClsr:
case ARM::t2MOVCCror:
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
return;
break;
case ARM::VMLALslsv2i32:
case ARM::VMLALslsv4i16:
case ARM::VMLALsluv2i32:
case ARM::VMLALsluv4i16:
case ARM::VMLAslv2i32:
case ARM::VMLAslv4i16:
case ARM::VMLAslv4i32:
case ARM::VMLAslv8i16:
case ARM::VMLSLslsv2i32:
case ARM::VMLSLslsv4i16:
case ARM::VMLSLsluv2i32:
case ARM::VMLSLsluv4i16:
case ARM::VMLSslv2i32:
case ARM::VMLSslv4i16:
case ARM::VMLSslv4i32:
case ARM::VMLSslv8i16:
case ARM::VQDMLALslv2i32:
case ARM::VQDMLALslv4i16:
case ARM::VQDMLSLslv2i32:
case ARM::VQDMLSLslv4i16:
O << ", ";
printOperand(MI, 3);
O << '[';
printNoHashImmediate(MI, 4);
O << ']';
return;
break;
case ARM::VMLAslfd:
case ARM::VMLAslfq:
case ARM::VMLSslfd:
case ARM::VMLSslfq:
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << '[';
printNoHashImmediate(MI, 4);
O << ']';
return;
break;
case ARM::VMULLslsv2i32:
case ARM::VMULLslsv4i16:
case ARM::VMULLsluv2i32:
case ARM::VMULLsluv4i16:
case ARM::VMULslv2i32:
case ARM::VMULslv4i16:
case ARM::VMULslv4i32:
case ARM::VMULslv8i16:
case ARM::VQDMULHslv2i32:
case ARM::VQDMULHslv4i16:
case ARM::VQDMULHslv4i32:
case ARM::VQDMULHslv8i16:
case ARM::VQDMULLslv2i32:
case ARM::VQDMULLslv4i16:
case ARM::VQRDMULHslv2i32:
case ARM::VQRDMULHslv4i16:
case ARM::VQRDMULHslv4i32:
case ARM::VQRDMULHslv8i16:
O << ", ";
printOperand(MI, 2);
O << '[';
printNoHashImmediate(MI, 3);
O << ']';
return;
break;
case ARM::VMULslfd:
case ARM::VMULslfq:
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << '[';
printNoHashImmediate(MI, 3);
O << ']';
return;
break;
case ARM::VSETLNi16:
case ARM::VSETLNi32:
case ARM::VSETLNi8:
O << '[';
printNoHashImmediate(MI, 3);
O << "], ";
printOperand(MI, 2);
return;
break;
case ARM::VST2LNd16:
case ARM::VST2LNd32:
case ARM::VST2LNd8:
case ARM::VST2LNq16a:
case ARM::VST2LNq16b:
case ARM::VST2LNq32a:
case ARM::VST2LNq32b:
O << '[';
printNoHashImmediate(MI, 6);
O << "], ";
printOperand(MI, 5);
O << '[';
printNoHashImmediate(MI, 6);
O << "]}, ";
printAddrMode6Operand(MI, 0);
return;
break;
case ARM::VST2d16:
case ARM::VST2d32:
case ARM::VST2d64:
case ARM::VST2d8:
O << ", ";
printOperand(MI, 5);
O << "}, ";
printAddrMode6Operand(MI, 0);
return;
break;
case ARM::VST2q16:
case ARM::VST2q32:
case ARM::VST2q8:
case ARM::VST4d16:
case ARM::VST4d32:
case ARM::VST4d64:
case ARM::VST4d8:
O << ", ";
printOperand(MI, 5);
O << ", ";
printOperand(MI, 6);
O << ", ";
printOperand(MI, 7);
O << "}, ";
printAddrMode6Operand(MI, 0);
return;
break;
case ARM::VST3LNd16:
case ARM::VST3LNd32:
case ARM::VST3LNd8:
case ARM::VST3LNq16a:
case ARM::VST3LNq16b:
case ARM::VST3LNq32a:
case ARM::VST3LNq32b:
O << '[';
printNoHashImmediate(MI, 7);
O << "], ";
printOperand(MI, 5);
O << '[';
printNoHashImmediate(MI, 7);
O << "], ";
printOperand(MI, 6);
O << '[';
printNoHashImmediate(MI, 7);
O << "]}, ";
printAddrMode6Operand(MI, 0);
return;
break;
case ARM::VST3d16:
case ARM::VST3d32:
case ARM::VST3d64:
case ARM::VST3d8:
O << ", ";
printOperand(MI, 5);
O << ", ";
printOperand(MI, 6);
O << "}, ";
printAddrMode6Operand(MI, 0);
return;
break;
case ARM::VST4LNd16:
case ARM::VST4LNd32:
case ARM::VST4LNd8:
case ARM::VST4LNq16a:
case ARM::VST4LNq16b:
case ARM::VST4LNq32a:
case ARM::VST4LNq32b:
O << '[';
printNoHashImmediate(MI, 8);
O << "], ";
printOperand(MI, 5);
O << '[';
printNoHashImmediate(MI, 8);
O << "], ";
printOperand(MI, 6);
O << '[';
printNoHashImmediate(MI, 8);
O << "], ";
printOperand(MI, 7);
O << '[';
printNoHashImmediate(MI, 8);
O << "]}, ";
printAddrMode6Operand(MI, 0);
return;
break;
case ARM::VST4q16a:
case ARM::VST4q16b:
case ARM::VST4q32a:
case ARM::VST4q32b:
case ARM::VST4q8a:
case ARM::VST4q8b:
O << ", ";
printOperand(MI, 8);
O << "}, ";
printAddrMode6Operand(MI, 1);
return;
break;
case ARM::VTBL1:
O << ", {";
printOperand(MI, 1);
O << "}, ";
printOperand(MI, 2);
return;
break;
case ARM::VTBL2:
O << ", {";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << "}, ";
printOperand(MI, 3);
return;
break;
case ARM::VTBL3:
O << ", {";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << "}, ";
printOperand(MI, 4);
return;
break;
case ARM::VTBL4:
O << ", {";
printOperand(MI, 1);
O << ", ";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << ", ";
printOperand(MI, 4);
O << "}, ";
printOperand(MI, 5);
return;
break;
case ARM::VTBX1:
O << ", {";
printOperand(MI, 2);
O << "}, ";
printOperand(MI, 3);
return;
break;
case ARM::VTBX2:
O << ", {";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << "}, ";
printOperand(MI, 4);
return;
break;
case ARM::VTBX3:
O << ", {";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << ", ";
printOperand(MI, 4);
O << "}, ";
printOperand(MI, 5);
return;
break;
case ARM::VTBX4:
O << ", {";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
O << ", ";
printOperand(MI, 4);
O << ", ";
printOperand(MI, 5);
O << "}, ";
printOperand(MI, 6);
return;
break;
case ARM::t2LDRpci_pic:
case ARM::tLDRpci_pic:
O << "\n";
printPCLabel(MI, 2);
O << ":\n\tadd\t";
printOperand(MI, 0);
O << ", pc";
return;
break;
case ARM::t2LEApcrelJT:
O << '_';
printNoHashImmediate(MI, 2);
return;
break;
case ARM::t2SXTBr_rot:
case ARM::t2SXTHr_rot:
case ARM::t2UXTB16r_rot:
case ARM::t2UXTBr_rot:
case ARM::t2UXTHr_rot:
printOperand(MI, 1);
O << ", ror ";
printOperand(MI, 2);
return;
break;
case ARM::tLEApcrel:
O << ", #";
printOperand(MI, 1);
return;
break;
case ARM::tLEApcrelJT:
O << ", #";
printOperand(MI, 1);
O << '_';
printNoHashImmediate(MI, 2);
return;
break;
}
return;
}
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
const char *ARMAsmPrinter::getRegisterName(unsigned RegNo) {
assert(RegNo && RegNo < 100 && "Invalid register number!");
static const unsigned RegAsmOffset[] = {
0, 5, 8, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51,
54, 58, 62, 66, 70, 74, 78, 82, 86, 90, 94, 97, 101, 105,
108, 111, 114, 117, 120, 123, 129, 132, 135, 138, 141, 145, 149, 153,
157, 161, 165, 168, 171, 174, 177, 180, 183, 186, 189, 192, 195, 199,
203, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237, 241, 245,
249, 253, 257, 261, 265, 269, 273, 277, 280, 284, 288, 292, 296, 300,
304, 308, 312, 316, 320, 323, 327, 331, 334, 337, 340, 343, 346, 349,
358, 0
};
const char *AsmStrs =
"cpsr\000d0\000d1\000d10\000d11\000d12\000d13\000d14\000d15\000d16\000d1"
"7\000d18\000d19\000d2\000d20\000d21\000d22\000d23\000d24\000d25\000d26\000"
"d27\000d28\000d29\000d3\000d30\000d31\000d4\000d5\000d6\000d7\000d8\000"
"d9\000fpscr\000lr\000pc\000q0\000q1\000q10\000q11\000q12\000q13\000q14\000"
"q15\000q2\000q3\000q4\000q5\000q6\000q7\000q8\000q9\000r0\000r1\000r10\000"
"r11\000r12\000r2\000r3\000r4\000r5\000r6\000r7\000r8\000r9\000s0\000s1\000"
"s10\000s11\000s12\000s13\000s14\000s15\000s16\000s17\000s18\000s19\000s"
"2\000s20\000s21\000s22\000s23\000s24\000s25\000s26\000s27\000s28\000s29"
"\000s3\000s30\000s31\000s4\000s5\000s6\000s7\000s8\000s9\000sINVALID\000"
"sp\000";
return AsmStrs+RegAsmOffset[RegNo-1];
}
#ifdef GET_INSTRUCTION_NAME
#undef GET_INSTRUCTION_NAME
/// getInstructionName: This method is automatically generated by tblgen
/// from the instruction set description. This returns the enum name of the
/// specified instruction.
const char *ARMAsmPrinter::getInstructionName(unsigned Opcode) {
assert(Opcode < 1611 && "Invalid instruction number!");
static const unsigned InstAsmOffset[] = {
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 138,
146, 154, 160, 166, 172, 179, 186, 193, 199, 205, 211, 228, 243, 249,
255, 261, 281, 301, 320, 340, 360, 379, 399, 419, 438, 459, 480, 500,
519, 538, 556, 576, 596, 615, 635, 655, 674, 690, 706, 721, 723, 727,
733, 739, 745, 750, 753, 757, 763, 771, 776, 786, 792, 801, 808, 815,
818, 822, 829, 834, 838, 842, 847, 851, 858, 865, 872, 878, 884, 890,
897, 904, 911, 927, 931, 935, 941, 947, 953, 961, 969, 976, 993, 1010,
1028, 1046, 1065, 1069, 1077, 1081, 1086, 1092, 1102, 1111, 1116, 1122, 1129, 1136,
1143, 1148, 1158, 1167, 1173, 1184, 1194, 1200, 1211, 1221, 1226, 1235, 1243, 1249,
1258, 1269, 1273, 1278, 1283, 1289, 1293, 1297, 1304, 1311, 1318, 1326, 1331, 1338,
1350, 1360, 1365, 1371, 1376, 1388, 1400, 1404, 1409, 1414, 1420, 1424, 1431, 1435,
1442, 1446, 1451, 1456, 1461, 1465, 1471, 1477, 1483, 1490, 1497, 1505, 1513, 1522,
1531, 1538, 1546, 1554, 1560, 1566, 1571, 1578, 1584, 1589, 1595, 1601, 1606, 1611,
1618, 1624, 1629, 1633, 1639, 1645, 1652, 1659, 1665, 1671, 1678, 1685, 1691, 1697,
1705, 1713, 1721, 1727, 1733, 1739, 1744, 1753, 1762, 1766, 1773, 1780, 1786, 1794,
1802, 1810, 1818, 1825, 1832, 1839, 1846, 1852, 1858, 1864, 1871, 1878, 1884, 1891,
1898, 1905, 1912, 1916, 1920, 1925, 1931, 1941, 1950, 1955, 1961, 1968, 1975, 1982,
1987, 1997, 2006, 2011, 2020, 2028, 2035, 2042, 2049, 2055, 2061, 2067, 2071, 2075,
2080, 2088, 2100, 2108, 2120, 2126, 2136, 2142, 2152, 2158, 2164, 2170, 2177, 2182,
2188, 2194, 2200, 2205, 2211, 2217, 2223, 2231, 2238, 2244, 2250, 2258, 2265, 2273,
2285, 2293, 2305, 2313, 2325, 2331, 2341, 2347, 2357, 2369, 2381, 2393, 2405, 2417,
2429, 2440, 2451, 2462, 2473, 2484, 2494, 2505, 2516, 2527, 2538, 2549, 2559, 2571,
2583, 2595, 2607, 2619, 2631, 2638, 2645, 2656, 2667, 2678, 2689, 2700, 2710, 2721,
2732, 2743, 2754, 2765, 2775, 2781, 2787, 2794, 2805, 2812, 2822, 2832, 2842, 2852,
2862, 2871, 2878, 2885, 2892, 2899, 2905, 2917, 2929, 2940, 2952, 2964, 2976, 2988,
3000, 3012, 3018, 3030, 3042, 3054, 3066, 3078, 3090, 3097, 3108, 3115, 3125, 3135,
3145, 3155, 3165, 3175, 3185, 3194, 3200, 3206, 3212, 3218, 3224, 3230, 3236, 3242,
3248, 3254, 3261, 3268, 3278, 3288, 3298, 3308, 3318, 3327, 3334, 3341, 3352, 3363,
3374, 3385, 3396, 3406, 3417, 3428, 3439, 3450, 3461, 3471, 3478, 3485, 3496, 3507,
3518, 3529, 3540, 3550, 3561, 3572, 3583, 3594, 3605, 3615, 3625, 3635, 3645, 3655,
3665, 3674, 3684, 3694, 3704, 3714, 3724, 3733, 3739, 3746, 3753, 3761, 3769, 3775,
3782, 3789, 3795, 3801, 3809, 3817, 3824, 3831, 3839, 3847, 3856, 3869, 3878, 3887,
3900, 3909, 3919, 3929, 3939, 3949, 3958, 3971, 3980, 3989, 4002, 4011, 4021, 4031,
4041, 4051, 4057, 4063, 4071, 4079, 4087, 4095, 4102, 4109, 4119, 4129, 4139, 4149,
4158, 4167, 4176, 4185, 4192, 4200, 4207, 4215, 4221, 4227, 4235, 4243, 4250, 4257,
4265, 4273, 4280, 4287, 4297, 4307, 4316, 4326, 4335, 4347, 4359, 4371, 4383, 4395,
4406, 4418, 4430, 4442, 4454, 4466, 4477, 4489, 4501, 4513, 4525, 4537, 4548, 4560,
4572, 4584, 4596, 4608, 4619, 4627, 4635, 4643, 4650, 4657, 4665, 4673, 4681, 4688,
4695, 4705, 4715, 4724, 4735, 4746, 4757, 4768, 4776, 4784, 4792, 4799, 4807, 4815,
4822, 4832, 4842, 4851, 4862, 4873, 4884, 4895, 4903, 4911, 4919, 4926, 4935, 4944,
4953, 4962, 4970, 4978, 4988, 4998, 5007, 5018, 5029, 5040, 5051, 5059, 5067, 5075,
5082, 5091, 5100, 5109, 5118, 5126, 5134, 5140, 5146, 5152, 5158, 5164, 5171, 5178,
5189, 5200, 5211, 5222, 5233, 5243, 5254, 5265, 5276, 5287, 5298, 5308, 5315, 5322,
5333, 5344, 5355, 5366, 5377, 5387, 5398, 5409, 5420, 5431, 5442, 5452, 5458, 5472,
5486, 5500, 5514, 5526, 5538, 5550, 5562, 5574, 5586, 5592, 5599, 5606, 5615, 5624,
5636, 5648, 5660, 5672, 5682, 5692, 5702, 5712, 5722, 5731, 5737, 5751, 5765, 5779,
5793, 5805, 5817, 5829, 5841, 5853, 5865, 5871, 5878, 5885, 5894, 5903, 5915, 5927,
5939, 5951, 5961, 5971, 5981, 5991, 6001, 6010, 6016, 6024, 6032, 6042, 6054, 6066,
6078, 6090, 6102, 6114, 6125, 6136, 6146, 6152, 6160, 6168, 6175, 6181, 6188, 6196,
6204, 6214, 6224, 6234, 6244, 6254, 6264, 6274, 6283, 6288, 6293, 6299, 6306, 6320,
6334, 6348, 6362, 6374, 6386, 6398, 6410, 6422, 6434, 6440, 6447, 6458, 6465, 6472,
6479, 6488, 6497, 6509, 6521, 6533, 6545, 6555, 6565, 6575, 6585, 6595, 6604, 6610,
6616, 6622, 6630, 6636, 6644, 6653, 6666, 6675, 6684, 6693, 6702, 6711, 6719, 6727,
6734, 6741, 6748, 6755, 6762, 6769, 6775, 6781, 6787, 6793, 6806, 6819, 6832, 6845,
6858, 6870, 6883, 6896, 6909, 6922, 6935, 6947, 6960, 6973, 6986, 6999, 7012, 7024,
7037, 7050, 7063, 7076, 7089, 7101, 7108, 7117, 7126, 7134, 7141, 7150, 7159, 7167,
7176, 7185, 7193, 7200, 7209, 7218, 7226, 7235, 7244, 7252, 7263, 7274, 7285, 7296,
7307, 7317, 7329, 7341, 7353, 7365, 7377, 7389, 7401, 7412, 7424, 7436, 7448, 7460,
7472, 7484, 7496, 7507, 7522, 7537, 7550, 7563, 7578, 7593, 7606, 7619, 7634, 7649,
7664, 7679, 7692, 7705, 7718, 7731, 7746, 7761, 7774, 7787, 7801, 7815, 7828, 7841,
7854, 7866, 7879, 7892, 7904, 7915, 7926, 7937, 7948, 7959, 7969, 7985, 8001, 8017,
8033, 8047, 8061, 8075, 8089, 8102, 8115, 8128, 8141, 8154, 8167, 8180, 8192, 8205,
8218, 8231, 8244, 8257, 8270, 8283, 8295, 8309, 8323, 8336, 8350, 8364, 8377, 8391,
8405, 8418, 8431, 8444, 8457, 8470, 8483, 8496, 8509, 8521, 8534, 8547, 8560, 8573,
8586, 8599, 8612, 8624, 8636, 8648, 8660, 8672, 8684, 8696, 8708, 8719, 8732, 8745,
8758, 8771, 8784, 8797, 8810, 8822, 8834, 8846, 8858, 8870, 8882, 8894, 8906, 8917,
8930, 8943, 8955, 8968, 8981, 8993, 9006, 9019, 9031, 9043, 9055, 9067, 9079, 9091,
9103, 9115, 9126, 9138, 9150, 9162, 9174, 9186, 9198, 9210, 9221, 9234, 9247, 9259,
9267, 9276, 9285, 9293, 9302, 9311, 9320, 9329, 9339, 9348, 9358, 9367, 9377, 9387,
9396, 9405, 9415, 9425, 9434, 9443, 9456, 9469, 9482, 9495, 9508, 9520, 9533, 9546,
9559, 9572, 9585, 9597, 9609, 9621, 9633, 9645, 9657, 9669, 9681, 9692, 9704, 9716,
9728, 9740, 9752, 9764, 9776, 9787, 9799, 9811, 9822, 9834, 9846, 9858, 9870, 9882,
9894, 9906, 9917, 9929, 9941, 9953, 9965, 9977, 9989, 10001, 10012, 10021, 10031, 10041,
10050, 10060, 10070, 10082, 10094, 10106, 10118, 10130, 10142, 10154, 10165, 10177, 10189, 10201,
10213, 10225, 10237, 10249, 10260, 10273, 10286, 10298, 10308, 10318, 10327, 10336, 10345, 10353,
10365, 10377, 10389, 10401, 10413, 10425, 10436, 10447, 10458, 10469, 10480, 10491, 10502, 10512,
10523, 10534, 10545, 10556, 10567, 10578, 10589, 10599, 10610, 10621, 10632, 10643, 10654, 10665,
10676, 10686, 10697, 10708, 10718, 10729, 10740, 10751, 10762, 10773, 10784, 10795, 10805, 10816,
10827, 10838, 10849, 10860, 10871, 10882, 10892, 10899, 10906, 10913, 10920, 10930, 10940, 10950,
10960, 10970, 10980, 10990, 10999, 11006, 11013, 11020, 11027, 11038, 11049, 11060, 11071, 11082,
11093, 11104, 11114, 11125, 11136, 11147, 11158, 11169, 11180, 11191, 11201, 11211, 11221, 11231,
11241, 11251, 11261, 11271, 11280, 11288, 11296, 11304, 11311, 11318, 11326, 11334, 11342, 11349,
11356, 11366, 11376, 11385, 11396, 11407, 11418, 11429, 11437, 11445, 11453, 11460, 11468, 11476,
11483, 11493, 11503, 11512, 11523, 11534, 11545, 11556, 11564, 11572, 11580, 11587, 11596, 11605,
11614, 11623, 11631, 11639, 11649, 11659, 11668, 11679, 11690, 11701, 11712, 11720, 11728, 11736,
11743, 11752, 11761, 11770, 11779, 11787, 11795, 11801, 11807, 11813, 11819, 11825, 11831, 11843,
11855, 11866, 11878, 11890, 11902, 11914, 11926, 11938, 11944, 11956, 11968, 11980, 11992, 12004,
12016, 12023, 12034, 12041, 12051, 12061, 12071, 12081, 12091, 12101, 12111, 12120, 12126, 12132,
12138, 12144, 12150, 12156, 12162, 12168, 12175, 12182, 12190, 12198, 12206, 12214, 12221, 12228,
12235, 12242, 12250, 12258, 12266, 12274, 12281, 12288, 12296, 12304, 12311, 12319, 12327, 12334,
12344, 12354, 12364, 12374, 12384, 12393, 12400, 12407, 12414, 12421, 12428, 12435, 12443, 12451,
12458, 12466, 12474, 12481, 12489, 12497, 12504, 12512, 12520, 12527, 12531, 12535, 12541, 12550,
12559, 12568, 12576, 12584, 12592, 12601, 12610, 12619, 12629, 12641, 12651, 12659, 12669, 12677,
12685, 12693, 12701, 12709, 12717, 12725, 12729, 12735, 12741, 12749, 12757, 12765, 12773, 12779,
12785, 12794, 12803, 12812, 12820, 12828, 12836, 12845, 12854, 12863, 12871, 12879, 12887, 12892,
12911, 12931, 12952, 12958, 12968, 12980, 12991, 13001, 13010, 13020, 13028, 13037, 13047, 13055,
13064, 13073, 13082, 13094, 13105, 13115, 13124, 13134, 13142, 13155, 13167, 13178, 13188, 13199,
13208, 13221, 13233, 13244, 13254, 13265, 13274, 13285, 13295, 13304, 13312, 13321, 13334, 13341,
13352, 13365, 13373, 13381, 13389, 13397, 13403, 13409, 13420, 13429, 13440, 13451, 13460, 13471,
13481, 13488, 13497, 13509, 13516, 13524, 13538, 13552, 13558, 13565, 13572, 13579, 13587, 13595,
13603, 13611, 13619, 13627, 13635, 13643, 13650, 13656, 13664, 13672, 13680, 13688, 13697, 13706,
13714, 13722, 13731, 13740, 13749, 13757, 13765, 13773, 13780, 13789, 13798, 13806, 13815, 13824,
13833, 13842, 13850, 13858, 13866, 13875, 13884, 13892, 13901, 13910, 13919, 13928, 13934, 13946,
13957, 13967, 13976, 13984, 13993, 14001, 14010, 14019, 14028, 14040, 14051, 14061, 14070, 14078,
14089, 14099, 14108, 14116, 14123, 14132, 14141, 14150, 14160, 14172, 14185, 14196, 14206, 14217,
14225, 14235, 14243, 14251, 14261, 14275, 14285, 14299, 14307, 14319, 14327, 14339, 14345, 14351,
14359, 14367, 14375, 14384, 14392, 14400, 14408, 14415, 14423, 14431, 14439, 14449, 14463, 14473,
14487, 14497, 14511, 14519, 14531, 14539, 14551, 14556, 14565, 14572, 14579, 14588, 14596, 14605,
14612, 14620, 14628, 14637, 14655, 14671, 14676, 14683, 14690, 14697, 14700, 14705, 14711, 14715,
14721, 14730, 14736, 14745, 14751, 14758, 14766, 14770, 14778, 14793, 14799, 14804, 14810, 14816,
14821, 14827, 14835, 14842, 14848, 14857, 14865, 14872, 14877, 14897, 14902, 14907, 14913, 14920,
14926, 14933, 14940, 14947, 14954, 14960, 14968, 14980, 14988, 14998, 15010, 15017, 15024, 15031,
15038, 15046, 15054, 15069, 15076, 15088, 15101, 15108, 15114, 15127, 15132, 15137, 15142, 15150,
15155, 15164, 15170, 15175, 15182, 15189, 15194, 15199, 15208, 15213, 15218, 15223, 15229, 15236,
15242, 15249, 15255, 15263, 15270, 15277, 15284, 15292, 15301, 15307, 15313, 15320, 15328, 15333,
15339, 0
};
const char *Strs =
"PHI\000INLINEASM\000DBG_LABEL\000EH_LABEL\000GC_LABEL\000KILL\000EXTRAC"
"T_SUBREG\000INSERT_SUBREG\000IMPLICIT_DEF\000SUBREG_TO_REG\000COPY_TO_R"
"EGCLASS\000DBG_VALUE\000ADCSSri\000ADCSSrr\000ADCSSrs\000ADCri\000ADCrr"
"\000ADCrs\000ADDSri\000ADDSrr\000ADDSrs\000ADDri\000ADDrr\000ADDrs\000A"
"DJCALLSTACKDOWN\000ADJCALLSTACKUP\000ANDri\000ANDrr\000ANDrs\000ATOMIC_"
"CMP_SWAP_I16\000ATOMIC_CMP_SWAP_I32\000ATOMIC_CMP_SWAP_I8\000ATOMIC_LOA"
"D_ADD_I16\000ATOMIC_LOAD_ADD_I32\000ATOMIC_LOAD_ADD_I8\000ATOMIC_LOAD_A"
"ND_I16\000ATOMIC_LOAD_AND_I32\000ATOMIC_LOAD_AND_I8\000ATOMIC_LOAD_NAND"
"_I16\000ATOMIC_LOAD_NAND_I32\000ATOMIC_LOAD_NAND_I8\000ATOMIC_LOAD_OR_I"
"16\000ATOMIC_LOAD_OR_I32\000ATOMIC_LOAD_OR_I8\000ATOMIC_LOAD_SUB_I16\000"
"ATOMIC_LOAD_SUB_I32\000ATOMIC_LOAD_SUB_I8\000ATOMIC_LOAD_XOR_I16\000ATO"
"MIC_LOAD_XOR_I32\000ATOMIC_LOAD_XOR_I8\000ATOMIC_SWAP_I16\000ATOMIC_SWA"
"P_I32\000ATOMIC_SWAP_I8\000B\000BFC\000BICri\000BICrr\000BICrs\000BKPT\000"
"BL\000BLX\000BLXr9\000BL_pred\000BLr9\000BLr9_pred\000BRIND\000BR_JTadd"
"\000BR_JTm\000BR_JTr\000BX\000BXJ\000BX_RET\000BXr9\000Bcc\000CDP\000CD"
"P2\000CLZ\000CMNzri\000CMNzrr\000CMNzrs\000CMPri\000CMPrr\000CMPrs\000C"
"MPzri\000CMPzrr\000CMPzrs\000CONSTPOOL_ENTRY\000CPS\000DBG\000EORri\000"
"EORrr\000EORrs\000FCONSTD\000FCONSTS\000FMSTAT\000Int_MemBarrierV6\000I"
"nt_MemBarrierV7\000Int_SyncBarrierV6\000Int_SyncBarrierV7\000Int_eh_sjl"
"j_setjmp\000LDM\000LDM_RET\000LDR\000LDRB\000LDRBT\000LDRB_POST\000LDRB"
"_PRE\000LDRD\000LDREX\000LDREXB\000LDREXD\000LDREXH\000LDRH\000LDRH_POS"
"T\000LDRH_PRE\000LDRSB\000LDRSB_POST\000LDRSB_PRE\000LDRSH\000LDRSH_POS"
"T\000LDRSH_PRE\000LDRT\000LDR_POST\000LDR_PRE\000LDRcp\000LEApcrel\000L"
"EApcrelJT\000MCR\000MCR2\000MCRR\000MCRR2\000MLA\000MLS\000MOVCCi\000MO"
"VCCr\000MOVCCs\000MOVTi16\000MOVi\000MOVi16\000MOVi2pieces\000MOVi32imm"
"\000MOVr\000MOVrx\000MOVs\000MOVsra_flag\000MOVsrl_flag\000MRC\000MRC2\000"
"MRRC\000MRRC2\000MRS\000MRSsys\000MSR\000MSRsys\000MUL\000MVNi\000MVNr\000"
"MVNs\000NOP\000ORRri\000ORRrr\000ORRrs\000PICADD\000PICLDR\000PICLDRB\000"
"PICLDRH\000PICLDRSB\000PICLDRSH\000PICSTR\000PICSTRB\000PICSTRH\000PKHB"
"T\000PKHTB\000QADD\000QADD16\000QADD8\000QASX\000QDADD\000QDSUB\000QSAX"
"\000QSUB\000QSUB16\000QSUB8\000RBIT\000REV\000REV16\000REVSH\000RSBSri\000"
"RSBSrs\000RSBri\000RSBrs\000RSCSri\000RSCSrs\000RSCri\000RSCrs\000SBCSS"
"ri\000SBCSSrr\000SBCSSrs\000SBCri\000SBCrr\000SBCrs\000SBFX\000SETENDBE"
"\000SETENDLE\000SEV\000SMLABB\000SMLABT\000SMLAL\000SMLALBB\000SMLALBT\000"
"SMLALTB\000SMLALTT\000SMLATB\000SMLATT\000SMLAWB\000SMLAWT\000SMMLA\000"
"SMMLS\000SMMUL\000SMULBB\000SMULBT\000SMULL\000SMULTB\000SMULTT\000SMUL"
"WB\000SMULWT\000STM\000STR\000STRB\000STRBT\000STRB_POST\000STRB_PRE\000"
"STRD\000STREX\000STREXB\000STREXD\000STREXH\000STRH\000STRH_POST\000STR"
"H_PRE\000STRT\000STR_POST\000STR_PRE\000SUBSri\000SUBSrr\000SUBSrs\000S"
"UBri\000SUBrr\000SUBrs\000SVC\000SWP\000SWPB\000SXTABrr\000SXTABrr_rot\000"
"SXTAHrr\000SXTAHrr_rot\000SXTBr\000SXTBr_rot\000SXTHr\000SXTHr_rot\000T"
"EQri\000TEQrr\000TEQrs\000TPsoft\000TRAP\000TSTri\000TSTrr\000TSTrs\000"
"UBFX\000UMAAL\000UMLAL\000UMULL\000UQADD16\000UQADD8\000UQASX\000UQSAX\000"
"UQSUB16\000UQSUB8\000UXTABrr\000UXTABrr_rot\000UXTAHrr\000UXTAHrr_rot\000"
"UXTB16r\000UXTB16r_rot\000UXTBr\000UXTBr_rot\000UXTHr\000UXTHr_rot\000V"
"ABALsv2i64\000VABALsv4i32\000VABALsv8i16\000VABALuv2i64\000VABALuv4i32\000"
"VABALuv8i16\000VABAsv16i8\000VABAsv2i32\000VABAsv4i16\000VABAsv4i32\000"
"VABAsv8i16\000VABAsv8i8\000VABAuv16i8\000VABAuv2i32\000VABAuv4i16\000VA"
"BAuv4i32\000VABAuv8i16\000VABAuv8i8\000VABDLsv2i64\000VABDLsv4i32\000VA"
"BDLsv8i16\000VABDLuv2i64\000VABDLuv4i32\000VABDLuv8i16\000VABDfd\000VAB"
"Dfq\000VABDsv16i8\000VABDsv2i32\000VABDsv4i16\000VABDsv4i32\000VABDsv8i"
"16\000VABDsv8i8\000VABDuv16i8\000VABDuv2i32\000VABDuv4i16\000VABDuv4i32"
"\000VABDuv8i16\000VABDuv8i8\000VABSD\000VABSS\000VABSfd\000VABSfd_sfp\000"
"VABSfq\000VABSv16i8\000VABSv2i32\000VABSv4i16\000VABSv4i32\000VABSv8i16"
"\000VABSv8i8\000VACGEd\000VACGEq\000VACGTd\000VACGTq\000VADDD\000VADDHN"
"v2i32\000VADDHNv4i16\000VADDHNv8i8\000VADDLsv2i64\000VADDLsv4i32\000VAD"
"DLsv8i16\000VADDLuv2i64\000VADDLuv4i32\000VADDLuv8i16\000VADDS\000VADDW"
"sv2i64\000VADDWsv4i32\000VADDWsv8i16\000VADDWuv2i64\000VADDWuv4i32\000V"
"ADDWuv8i16\000VADDfd\000VADDfd_sfp\000VADDfq\000VADDv16i8\000VADDv1i64\000"
"VADDv2i32\000VADDv2i64\000VADDv4i16\000VADDv4i32\000VADDv8i16\000VADDv8"
"i8\000VANDd\000VANDq\000VBICd\000VBICq\000VBIFd\000VBIFq\000VBITd\000VB"
"ITq\000VBSLd\000VBSLq\000VCEQfd\000VCEQfq\000VCEQv16i8\000VCEQv2i32\000"
"VCEQv4i16\000VCEQv4i32\000VCEQv8i16\000VCEQv8i8\000VCGEfd\000VCGEfq\000"
"VCGEsv16i8\000VCGEsv2i32\000VCGEsv4i16\000VCGEsv4i32\000VCGEsv8i16\000V"
"CGEsv8i8\000VCGEuv16i8\000VCGEuv2i32\000VCGEuv4i16\000VCGEuv4i32\000VCG"
"Euv8i16\000VCGEuv8i8\000VCGTfd\000VCGTfq\000VCGTsv16i8\000VCGTsv2i32\000"
"VCGTsv4i16\000VCGTsv4i32\000VCGTsv8i16\000VCGTsv8i8\000VCGTuv16i8\000VC"
"GTuv2i32\000VCGTuv4i16\000VCGTuv4i32\000VCGTuv8i16\000VCGTuv8i8\000VCLS"
"v16i8\000VCLSv2i32\000VCLSv4i16\000VCLSv4i32\000VCLSv8i16\000VCLSv8i8\000"
"VCLZv16i8\000VCLZv2i32\000VCLZv4i16\000VCLZv4i32\000VCLZv8i16\000VCLZv8"
"i8\000VCMPD\000VCMPED\000VCMPES\000VCMPEZD\000VCMPEZS\000VCMPS\000VCMPZ"
"D\000VCMPZS\000VCNTd\000VCNTq\000VCVTBHS\000VCVTBSH\000VCVTDS\000VCVTSD"
"\000VCVTTHS\000VCVTTSH\000VCVTf2sd\000VCVTf2sd_sfp\000VCVTf2sq\000VCVTf"
"2ud\000VCVTf2ud_sfp\000VCVTf2uq\000VCVTf2xsd\000VCVTf2xsq\000VCVTf2xud\000"
"VCVTf2xuq\000VCVTs2fd\000VCVTs2fd_sfp\000VCVTs2fq\000VCVTu2fd\000VCVTu2"
"fd_sfp\000VCVTu2fq\000VCVTxs2fd\000VCVTxs2fq\000VCVTxu2fd\000VCVTxu2fq\000"
"VDIVD\000VDIVS\000VDUP16d\000VDUP16q\000VDUP32d\000VDUP32q\000VDUP8d\000"
"VDUP8q\000VDUPLN16d\000VDUPLN16q\000VDUPLN32d\000VDUPLN32q\000VDUPLN8d\000"
"VDUPLN8q\000VDUPLNfd\000VDUPLNfq\000VDUPfd\000VDUPfdf\000VDUPfq\000VDUP"
"fqf\000VEORd\000VEORq\000VEXTd16\000VEXTd32\000VEXTd8\000VEXTdf\000VEXT"
"q16\000VEXTq32\000VEXTq8\000VEXTqf\000VGETLNi32\000VGETLNs16\000VGETLNs"
"8\000VGETLNu16\000VGETLNu8\000VHADDsv16i8\000VHADDsv2i32\000VHADDsv4i16"
"\000VHADDsv4i32\000VHADDsv8i16\000VHADDsv8i8\000VHADDuv16i8\000VHADDuv2"
"i32\000VHADDuv4i16\000VHADDuv4i32\000VHADDuv8i16\000VHADDuv8i8\000VHSUB"
"sv16i8\000VHSUBsv2i32\000VHSUBsv4i16\000VHSUBsv4i32\000VHSUBsv8i16\000V"
"HSUBsv8i8\000VHSUBuv16i8\000VHSUBuv2i32\000VHSUBuv4i16\000VHSUBuv4i32\000"
"VHSUBuv8i16\000VHSUBuv8i8\000VLD1d16\000VLD1d32\000VLD1d64\000VLD1d8\000"
"VLD1df\000VLD1q16\000VLD1q32\000VLD1q64\000VLD1q8\000VLD1qf\000VLD2LNd1"
"6\000VLD2LNd32\000VLD2LNd8\000VLD2LNq16a\000VLD2LNq16b\000VLD2LNq32a\000"
"VLD2LNq32b\000VLD2d16\000VLD2d32\000VLD2d64\000VLD2d8\000VLD2q16\000VLD"
"2q32\000VLD2q8\000VLD3LNd16\000VLD3LNd32\000VLD3LNd8\000VLD3LNq16a\000V"
"LD3LNq16b\000VLD3LNq32a\000VLD3LNq32b\000VLD3d16\000VLD3d32\000VLD3d64\000"
"VLD3d8\000VLD3q16a\000VLD3q16b\000VLD3q32a\000VLD3q32b\000VLD3q8a\000VL"
"D3q8b\000VLD4LNd16\000VLD4LNd32\000VLD4LNd8\000VLD4LNq16a\000VLD4LNq16b"
"\000VLD4LNq32a\000VLD4LNq32b\000VLD4d16\000VLD4d32\000VLD4d64\000VLD4d8"
"\000VLD4q16a\000VLD4q16b\000VLD4q32a\000VLD4q32b\000VLD4q8a\000VLD4q8b\000"
"VLDMD\000VLDMS\000VLDRD\000VLDRQ\000VLDRS\000VMAXfd\000VMAXfq\000VMAXsv"
"16i8\000VMAXsv2i32\000VMAXsv4i16\000VMAXsv4i32\000VMAXsv8i16\000VMAXsv8"
"i8\000VMAXuv16i8\000VMAXuv2i32\000VMAXuv4i16\000VMAXuv4i32\000VMAXuv8i1"
"6\000VMAXuv8i8\000VMINfd\000VMINfq\000VMINsv16i8\000VMINsv2i32\000VMINs"
"v4i16\000VMINsv4i32\000VMINsv8i16\000VMINsv8i8\000VMINuv16i8\000VMINuv2"
"i32\000VMINuv4i16\000VMINuv4i32\000VMINuv8i16\000VMINuv8i8\000VMLAD\000"
"VMLALslsv2i32\000VMLALslsv4i16\000VMLALsluv2i32\000VMLALsluv4i16\000VML"
"ALsv2i64\000VMLALsv4i32\000VMLALsv8i16\000VMLALuv2i64\000VMLALuv4i32\000"
"VMLALuv8i16\000VMLAS\000VMLAfd\000VMLAfq\000VMLAslfd\000VMLAslfq\000VML"
"Aslv2i32\000VMLAslv4i16\000VMLAslv4i32\000VMLAslv8i16\000VMLAv16i8\000V"
"MLAv2i32\000VMLAv4i16\000VMLAv4i32\000VMLAv8i16\000VMLAv8i8\000VMLSD\000"
"VMLSLslsv2i32\000VMLSLslsv4i16\000VMLSLsluv2i32\000VMLSLsluv4i16\000VML"
"SLsv2i64\000VMLSLsv4i32\000VMLSLsv8i16\000VMLSLuv2i64\000VMLSLuv4i32\000"
"VMLSLuv8i16\000VMLSS\000VMLSfd\000VMLSfq\000VMLSslfd\000VMLSslfq\000VML"
"Sslv2i32\000VMLSslv4i16\000VMLSslv4i32\000VMLSslv8i16\000VMLSv16i8\000V"
"MLSv2i32\000VMLSv4i16\000VMLSv4i32\000VMLSv8i16\000VMLSv8i8\000VMOVD\000"
"VMOVDRR\000VMOVDcc\000VMOVDneon\000VMOVLsv2i64\000VMOVLsv4i32\000VMOVLs"
"v8i16\000VMOVLuv2i64\000VMOVLuv4i32\000VMOVLuv8i16\000VMOVNv2i32\000VMO"
"VNv4i16\000VMOVNv8i8\000VMOVQ\000VMOVRRD\000VMOVRRS\000VMOVRS\000VMOVS\000"
"VMOVSR\000VMOVSRR\000VMOVScc\000VMOVv16i8\000VMOVv1i64\000VMOVv2i32\000"
"VMOVv2i64\000VMOVv4i16\000VMOVv4i32\000VMOVv8i16\000VMOVv8i8\000VMRS\000"
"VMSR\000VMULD\000VMULLp\000VMULLslsv2i32\000VMULLslsv4i16\000VMULLsluv2"
"i32\000VMULLsluv4i16\000VMULLsv2i64\000VMULLsv4i32\000VMULLsv8i16\000VM"
"ULLuv2i64\000VMULLuv4i32\000VMULLuv8i16\000VMULS\000VMULfd\000VMULfd_sf"
"p\000VMULfq\000VMULpd\000VMULpq\000VMULslfd\000VMULslfq\000VMULslv2i32\000"
"VMULslv4i16\000VMULslv4i32\000VMULslv8i16\000VMULv16i8\000VMULv2i32\000"
"VMULv4i16\000VMULv4i32\000VMULv8i16\000VMULv8i8\000VMVNd\000VMVNq\000VN"
"EGD\000VNEGDcc\000VNEGS\000VNEGScc\000VNEGf32d\000VNEGf32d_sfp\000VNEGf"
"32q\000VNEGs16d\000VNEGs16q\000VNEGs32d\000VNEGs32q\000VNEGs8d\000VNEGs"
"8q\000VNMLAD\000VNMLAS\000VNMLSD\000VNMLSS\000VNMULD\000VNMULS\000VORNd"
"\000VORNq\000VORRd\000VORRq\000VPADALsv16i8\000VPADALsv2i32\000VPADALsv"
"4i16\000VPADALsv4i32\000VPADALsv8i16\000VPADALsv8i8\000VPADALuv16i8\000"
"VPADALuv2i32\000VPADALuv4i16\000VPADALuv4i32\000VPADALuv8i16\000VPADALu"
"v8i8\000VPADDLsv16i8\000VPADDLsv2i32\000VPADDLsv4i16\000VPADDLsv4i32\000"
"VPADDLsv8i16\000VPADDLsv8i8\000VPADDLuv16i8\000VPADDLuv2i32\000VPADDLuv"
"4i16\000VPADDLuv4i32\000VPADDLuv8i16\000VPADDLuv8i8\000VPADDf\000VPADDi"
"16\000VPADDi32\000VPADDi8\000VPMAXf\000VPMAXs16\000VPMAXs32\000VPMAXs8\000"
"VPMAXu16\000VPMAXu32\000VPMAXu8\000VPMINf\000VPMINs16\000VPMINs32\000VP"
"MINs8\000VPMINu16\000VPMINu32\000VPMINu8\000VQABSv16i8\000VQABSv2i32\000"
"VQABSv4i16\000VQABSv4i32\000VQABSv8i16\000VQABSv8i8\000VQADDsv16i8\000V"
"QADDsv1i64\000VQADDsv2i32\000VQADDsv2i64\000VQADDsv4i16\000VQADDsv4i32\000"
"VQADDsv8i16\000VQADDsv8i8\000VQADDuv16i8\000VQADDuv1i64\000VQADDuv2i32\000"
"VQADDuv2i64\000VQADDuv4i16\000VQADDuv4i32\000VQADDuv8i16\000VQADDuv8i8\000"
"VQDMLALslv2i32\000VQDMLALslv4i16\000VQDMLALv2i64\000VQDMLALv4i32\000VQD"
"MLSLslv2i32\000VQDMLSLslv4i16\000VQDMLSLv2i64\000VQDMLSLv4i32\000VQDMUL"
"Hslv2i32\000VQDMULHslv4i16\000VQDMULHslv4i32\000VQDMULHslv8i16\000VQDMU"
"LHv2i32\000VQDMULHv4i16\000VQDMULHv4i32\000VQDMULHv8i16\000VQDMULLslv2i"
"32\000VQDMULLslv4i16\000VQDMULLv2i64\000VQDMULLv4i32\000VQMOVNsuv2i32\000"
"VQMOVNsuv4i16\000VQMOVNsuv8i8\000VQMOVNsv2i32\000VQMOVNsv4i16\000VQMOVN"
"sv8i8\000VQMOVNuv2i32\000VQMOVNuv4i16\000VQMOVNuv8i8\000VQNEGv16i8\000V"
"QNEGv2i32\000VQNEGv4i16\000VQNEGv4i32\000VQNEGv8i16\000VQNEGv8i8\000VQR"
"DMULHslv2i32\000VQRDMULHslv4i16\000VQRDMULHslv4i32\000VQRDMULHslv8i16\000"
"VQRDMULHv2i32\000VQRDMULHv4i16\000VQRDMULHv4i32\000VQRDMULHv8i16\000VQR"
"SHLsv16i8\000VQRSHLsv1i64\000VQRSHLsv2i32\000VQRSHLsv2i64\000VQRSHLsv4i"
"16\000VQRSHLsv4i32\000VQRSHLsv8i16\000VQRSHLsv8i8\000VQRSHLuv16i8\000VQ"
"RSHLuv1i64\000VQRSHLuv2i32\000VQRSHLuv2i64\000VQRSHLuv4i16\000VQRSHLuv4"
"i32\000VQRSHLuv8i16\000VQRSHLuv8i8\000VQRSHRNsv2i32\000VQRSHRNsv4i16\000"
"VQRSHRNsv8i8\000VQRSHRNuv2i32\000VQRSHRNuv4i16\000VQRSHRNuv8i8\000VQRSH"
"RUNv2i32\000VQRSHRUNv4i16\000VQRSHRUNv8i8\000VQSHLsiv16i8\000VQSHLsiv1i"
"64\000VQSHLsiv2i32\000VQSHLsiv2i64\000VQSHLsiv4i16\000VQSHLsiv4i32\000V"
"QSHLsiv8i16\000VQSHLsiv8i8\000VQSHLsuv16i8\000VQSHLsuv1i64\000VQSHLsuv2"
"i32\000VQSHLsuv2i64\000VQSHLsuv4i16\000VQSHLsuv4i32\000VQSHLsuv8i16\000"
"VQSHLsuv8i8\000VQSHLsv16i8\000VQSHLsv1i64\000VQSHLsv2i32\000VQSHLsv2i64"
"\000VQSHLsv4i16\000VQSHLsv4i32\000VQSHLsv8i16\000VQSHLsv8i8\000VQSHLuiv"
"16i8\000VQSHLuiv1i64\000VQSHLuiv2i32\000VQSHLuiv2i64\000VQSHLuiv4i16\000"
"VQSHLuiv4i32\000VQSHLuiv8i16\000VQSHLuiv8i8\000VQSHLuv16i8\000VQSHLuv1i"
"64\000VQSHLuv2i32\000VQSHLuv2i64\000VQSHLuv4i16\000VQSHLuv4i32\000VQSHL"
"uv8i16\000VQSHLuv8i8\000VQSHRNsv2i32\000VQSHRNsv4i16\000VQSHRNsv8i8\000"
"VQSHRNuv2i32\000VQSHRNuv4i16\000VQSHRNuv8i8\000VQSHRUNv2i32\000VQSHRUNv"
"4i16\000VQSHRUNv8i8\000VQSUBsv16i8\000VQSUBsv1i64\000VQSUBsv2i32\000VQS"
"UBsv2i64\000VQSUBsv4i16\000VQSUBsv4i32\000VQSUBsv8i16\000VQSUBsv8i8\000"
"VQSUBuv16i8\000VQSUBuv1i64\000VQSUBuv2i32\000VQSUBuv2i64\000VQSUBuv4i16"
"\000VQSUBuv4i32\000VQSUBuv8i16\000VQSUBuv8i8\000VRADDHNv2i32\000VRADDHN"
"v4i16\000VRADDHNv8i8\000VRECPEd\000VRECPEfd\000VRECPEfq\000VRECPEq\000V"
"RECPSfd\000VRECPSfq\000VREV16d8\000VREV16q8\000VREV32d16\000VREV32d8\000"
"VREV32q16\000VREV32q8\000VREV64d16\000VREV64d32\000VREV64d8\000VREV64df"
"\000VREV64q16\000VREV64q32\000VREV64q8\000VREV64qf\000VRHADDsv16i8\000V"
"RHADDsv2i32\000VRHADDsv4i16\000VRHADDsv4i32\000VRHADDsv8i16\000VRHADDsv"
"8i8\000VRHADDuv16i8\000VRHADDuv2i32\000VRHADDuv4i16\000VRHADDuv4i32\000"
"VRHADDuv8i16\000VRHADDuv8i8\000VRSHLsv16i8\000VRSHLsv1i64\000VRSHLsv2i3"
"2\000VRSHLsv2i64\000VRSHLsv4i16\000VRSHLsv4i32\000VRSHLsv8i16\000VRSHLs"
"v8i8\000VRSHLuv16i8\000VRSHLuv1i64\000VRSHLuv2i32\000VRSHLuv2i64\000VRS"
"HLuv4i16\000VRSHLuv4i32\000VRSHLuv8i16\000VRSHLuv8i8\000VRSHRNv2i32\000"
"VRSHRNv4i16\000VRSHRNv8i8\000VRSHRsv16i8\000VRSHRsv1i64\000VRSHRsv2i32\000"
"VRSHRsv2i64\000VRSHRsv4i16\000VRSHRsv4i32\000VRSHRsv8i16\000VRSHRsv8i8\000"
"VRSHRuv16i8\000VRSHRuv1i64\000VRSHRuv2i32\000VRSHRuv2i64\000VRSHRuv4i16"
"\000VRSHRuv4i32\000VRSHRuv8i16\000VRSHRuv8i8\000VRSQRTEd\000VRSQRTEfd\000"
"VRSQRTEfq\000VRSQRTEq\000VRSQRTSfd\000VRSQRTSfq\000VRSRAsv16i8\000VRSRA"
"sv1i64\000VRSRAsv2i32\000VRSRAsv2i64\000VRSRAsv4i16\000VRSRAsv4i32\000V"
"RSRAsv8i16\000VRSRAsv8i8\000VRSRAuv16i8\000VRSRAuv1i64\000VRSRAuv2i32\000"
"VRSRAuv2i64\000VRSRAuv4i16\000VRSRAuv4i32\000VRSRAuv8i16\000VRSRAuv8i8\000"
"VRSUBHNv2i32\000VRSUBHNv4i16\000VRSUBHNv8i8\000VSETLNi16\000VSETLNi32\000"
"VSETLNi8\000VSHLLi16\000VSHLLi32\000VSHLLi8\000VSHLLsv2i64\000VSHLLsv4i"
"32\000VSHLLsv8i16\000VSHLLuv2i64\000VSHLLuv4i32\000VSHLLuv8i16\000VSHLi"
"v16i8\000VSHLiv1i64\000VSHLiv2i32\000VSHLiv2i64\000VSHLiv4i16\000VSHLiv"
"4i32\000VSHLiv8i16\000VSHLiv8i8\000VSHLsv16i8\000VSHLsv1i64\000VSHLsv2i"
"32\000VSHLsv2i64\000VSHLsv4i16\000VSHLsv4i32\000VSHLsv8i16\000VSHLsv8i8"
"\000VSHLuv16i8\000VSHLuv1i64\000VSHLuv2i32\000VSHLuv2i64\000VSHLuv4i16\000"
"VSHLuv4i32\000VSHLuv8i16\000VSHLuv8i8\000VSHRNv2i32\000VSHRNv4i16\000VS"
"HRNv8i8\000VSHRsv16i8\000VSHRsv1i64\000VSHRsv2i32\000VSHRsv2i64\000VSHR"
"sv4i16\000VSHRsv4i32\000VSHRsv8i16\000VSHRsv8i8\000VSHRuv16i8\000VSHRuv"
"1i64\000VSHRuv2i32\000VSHRuv2i64\000VSHRuv4i16\000VSHRuv4i32\000VSHRuv8"
"i16\000VSHRuv8i8\000VSHTOD\000VSHTOS\000VSITOD\000VSITOS\000VSLIv16i8\000"
"VSLIv1i64\000VSLIv2i32\000VSLIv2i64\000VSLIv4i16\000VSLIv4i32\000VSLIv8"
"i16\000VSLIv8i8\000VSLTOD\000VSLTOS\000VSQRTD\000VSQRTS\000VSRAsv16i8\000"
"VSRAsv1i64\000VSRAsv2i32\000VSRAsv2i64\000VSRAsv4i16\000VSRAsv4i32\000V"
"SRAsv8i16\000VSRAsv8i8\000VSRAuv16i8\000VSRAuv1i64\000VSRAuv2i32\000VSR"
"Auv2i64\000VSRAuv4i16\000VSRAuv4i32\000VSRAuv8i16\000VSRAuv8i8\000VSRIv"
"16i8\000VSRIv1i64\000VSRIv2i32\000VSRIv2i64\000VSRIv4i16\000VSRIv4i32\000"
"VSRIv8i16\000VSRIv8i8\000VST1d16\000VST1d32\000VST1d64\000VST1d8\000VST"
"1df\000VST1q16\000VST1q32\000VST1q64\000VST1q8\000VST1qf\000VST2LNd16\000"
"VST2LNd32\000VST2LNd8\000VST2LNq16a\000VST2LNq16b\000VST2LNq32a\000VST2"
"LNq32b\000VST2d16\000VST2d32\000VST2d64\000VST2d8\000VST2q16\000VST2q32"
"\000VST2q8\000VST3LNd16\000VST3LNd32\000VST3LNd8\000VST3LNq16a\000VST3L"
"Nq16b\000VST3LNq32a\000VST3LNq32b\000VST3d16\000VST3d32\000VST3d64\000V"
"ST3d8\000VST3q16a\000VST3q16b\000VST3q32a\000VST3q32b\000VST3q8a\000VST"
"3q8b\000VST4LNd16\000VST4LNd32\000VST4LNd8\000VST4LNq16a\000VST4LNq16b\000"
"VST4LNq32a\000VST4LNq32b\000VST4d16\000VST4d32\000VST4d64\000VST4d8\000"
"VST4q16a\000VST4q16b\000VST4q32a\000VST4q32b\000VST4q8a\000VST4q8b\000V"
"STMD\000VSTMS\000VSTRD\000VSTRQ\000VSTRS\000VSUBD\000VSUBHNv2i32\000VSU"
"BHNv4i16\000VSUBHNv8i8\000VSUBLsv2i64\000VSUBLsv4i32\000VSUBLsv8i16\000"
"VSUBLuv2i64\000VSUBLuv4i32\000VSUBLuv8i16\000VSUBS\000VSUBWsv2i64\000VS"
"UBWsv4i32\000VSUBWsv8i16\000VSUBWuv2i64\000VSUBWuv4i32\000VSUBWuv8i16\000"
"VSUBfd\000VSUBfd_sfp\000VSUBfq\000VSUBv16i8\000VSUBv1i64\000VSUBv2i32\000"
"VSUBv2i64\000VSUBv4i16\000VSUBv4i32\000VSUBv8i16\000VSUBv8i8\000VTBL1\000"
"VTBL2\000VTBL3\000VTBL4\000VTBX1\000VTBX2\000VTBX3\000VTBX4\000VTOSHD\000"
"VTOSHS\000VTOSIRD\000VTOSIRS\000VTOSIZD\000VTOSIZS\000VTOSLD\000VTOSLS\000"
"VTOUHD\000VTOUHS\000VTOUIRD\000VTOUIRS\000VTOUIZD\000VTOUIZS\000VTOULD\000"
"VTOULS\000VTRNd16\000VTRNd32\000VTRNd8\000VTRNq16\000VTRNq32\000VTRNq8\000"
"VTSTv16i8\000VTSTv2i32\000VTSTv4i16\000VTSTv4i32\000VTSTv8i16\000VTSTv8"
"i8\000VUHTOD\000VUHTOS\000VUITOD\000VUITOS\000VULTOD\000VULTOS\000VUZPd"
"16\000VUZPd32\000VUZPd8\000VUZPq16\000VUZPq32\000VUZPq8\000VZIPd16\000V"
"ZIPd32\000VZIPd8\000VZIPq16\000VZIPq32\000VZIPq8\000WFE\000WFI\000YIELD"
"\000t2ADCSri\000t2ADCSrr\000t2ADCSrs\000t2ADCri\000t2ADCrr\000t2ADCrs\000"
"t2ADDSri\000t2ADDSrr\000t2ADDSrs\000t2ADDrSPi\000t2ADDrSPi12\000t2ADDrS"
"Ps\000t2ADDri\000t2ADDri12\000t2ADDrr\000t2ADDrs\000t2ANDri\000t2ANDrr\000"
"t2ANDrs\000t2ASRri\000t2ASRrr\000t2B\000t2BFC\000t2BFI\000t2BICri\000t2"
"BICrr\000t2BICrs\000t2BR_JT\000t2Bcc\000t2CLZ\000t2CMNzri\000t2CMNzrr\000"
"t2CMNzrs\000t2CMPri\000t2CMPrr\000t2CMPrs\000t2CMPzri\000t2CMPzrr\000t2"
"CMPzrs\000t2EORri\000t2EORrr\000t2EORrs\000t2IT\000t2Int_MemBarrierV7\000"
"t2Int_SyncBarrierV7\000t2Int_eh_sjlj_setjmp\000t2LDM\000t2LDM_RET\000t2"
"LDRB_POST\000t2LDRB_PRE\000t2LDRBi12\000t2LDRBi8\000t2LDRBpci\000t2LDRB"
"s\000t2LDRDi8\000t2LDRDpci\000t2LDREX\000t2LDREXB\000t2LDREXD\000t2LDRE"
"XH\000t2LDRH_POST\000t2LDRH_PRE\000t2LDRHi12\000t2LDRHi8\000t2LDRHpci\000"
"t2LDRHs\000t2LDRSB_POST\000t2LDRSB_PRE\000t2LDRSBi12\000t2LDRSBi8\000t2"
"LDRSBpci\000t2LDRSBs\000t2LDRSH_POST\000t2LDRSH_PRE\000t2LDRSHi12\000t2"
"LDRSHi8\000t2LDRSHpci\000t2LDRSHs\000t2LDR_POST\000t2LDR_PRE\000t2LDRi1"
"2\000t2LDRi8\000t2LDRpci\000t2LDRpci_pic\000t2LDRs\000t2LEApcrel\000t2L"
"EApcrelJT\000t2LSLri\000t2LSLrr\000t2LSRri\000t2LSRrr\000t2MLA\000t2MLS"
"\000t2MOVCCasr\000t2MOVCCi\000t2MOVCClsl\000t2MOVCClsr\000t2MOVCCr\000t"
"2MOVCCror\000t2MOVTi16\000t2MOVi\000t2MOVi16\000t2MOVi32imm\000t2MOVr\000"
"t2MOVrx\000t2MOVsra_flag\000t2MOVsrl_flag\000t2MUL\000t2MVNi\000t2MVNr\000"
"t2MVNs\000t2ORNri\000t2ORNrr\000t2ORNrs\000t2ORRri\000t2ORRrr\000t2ORRr"
"s\000t2PKHBT\000t2PKHTB\000t2RBIT\000t2REV\000t2REV16\000t2REVSH\000t2R"
"ORri\000t2RORrr\000t2RSBSri\000t2RSBSrs\000t2RSBri\000t2RSBrs\000t2SBCS"
"ri\000t2SBCSrr\000t2SBCSrs\000t2SBCri\000t2SBCrr\000t2SBCrs\000t2SBFX\000"
"t2SMLABB\000t2SMLABT\000t2SMLAL\000t2SMLATB\000t2SMLATT\000t2SMLAWB\000"
"t2SMLAWT\000t2SMMLA\000t2SMMLS\000t2SMMUL\000t2SMULBB\000t2SMULBT\000t2"
"SMULL\000t2SMULTB\000t2SMULTT\000t2SMULWB\000t2SMULWT\000t2STM\000t2STR"
"B_POST\000t2STRB_PRE\000t2STRBi12\000t2STRBi8\000t2STRBs\000t2STRDi8\000"
"t2STREX\000t2STREXB\000t2STREXD\000t2STREXH\000t2STRH_POST\000t2STRH_PR"
"E\000t2STRHi12\000t2STRHi8\000t2STRHs\000t2STR_POST\000t2STR_PRE\000t2S"
"TRi12\000t2STRi8\000t2STRs\000t2SUBSri\000t2SUBSrr\000t2SUBSrs\000t2SUB"
"rSPi\000t2SUBrSPi12\000t2SUBrSPi12_\000t2SUBrSPi_\000t2SUBrSPs\000t2SUB"
"rSPs_\000t2SUBri\000t2SUBri12\000t2SUBrr\000t2SUBrs\000t2SXTABrr\000t2S"
"XTABrr_rot\000t2SXTAHrr\000t2SXTAHrr_rot\000t2SXTBr\000t2SXTBr_rot\000t"
"2SXTHr\000t2SXTHr_rot\000t2TBB\000t2TBH\000t2TEQri\000t2TEQrr\000t2TEQr"
"s\000t2TPsoft\000t2TSTri\000t2TSTrr\000t2TSTrs\000t2UBFX\000t2UMAAL\000"
"t2UMLAL\000t2UMULL\000t2UXTABrr\000t2UXTABrr_rot\000t2UXTAHrr\000t2UXTA"
"Hrr_rot\000t2UXTB16r\000t2UXTB16r_rot\000t2UXTBr\000t2UXTBr_rot\000t2UX"
"THr\000t2UXTHr_rot\000tADC\000tADDhirr\000tADDi3\000tADDi8\000tADDrPCi\000"
"tADDrSP\000tADDrSPi\000tADDrr\000tADDspi\000tADDspr\000tADDspr_\000tADJ"
"CALLSTACKDOWN\000tADJCALLSTACKUP\000tAND\000tANDsp\000tASRri\000tASRrr\000"
"tB\000tBIC\000tBKPT\000tBL\000tBLXi\000tBLXi_r9\000tBLXr\000tBLXr_r9\000"
"tBLr9\000tBRIND\000tBR_JTr\000tBX\000tBX_RET\000tBX_RET_vararg\000tBXr9"
"\000tBcc\000tBfar\000tCBNZ\000tCBZ\000tCMNz\000tCMPhir\000tCMPi8\000tCM"
"Pr\000tCMPzhir\000tCMPzi8\000tCMPzr\000tEOR\000tInt_eh_sjlj_setjmp\000t"
"LDM\000tLDR\000tLDRB\000tLDRBi\000tLDRH\000tLDRHi\000tLDRSB\000tLDRSH\000"
"tLDRcp\000tLDRi\000tLDRpci\000tLDRpci_pic\000tLDRspi\000tLEApcrel\000tL"
"EApcrelJT\000tLSLri\000tLSLrr\000tLSRri\000tLSRrr\000tMOVCCi\000tMOVCCr"
"\000tMOVCCr_pseudo\000tMOVSr\000tMOVgpr2gpr\000tMOVgpr2tgpr\000tMOVi8\000"
"tMOVr\000tMOVtgpr2gpr\000tMUL\000tMVN\000tORR\000tPICADD\000tPOP\000tPO"
"P_RET\000tPUSH\000tREV\000tREV16\000tREVSH\000tROR\000tRSB\000tRestore\000"
"tSBC\000tSTM\000tSTR\000tSTRB\000tSTRBi\000tSTRH\000tSTRHi\000tSTRi\000"
"tSTRspi\000tSUBi3\000tSUBi8\000tSUBrr\000tSUBspi\000tSUBspi_\000tSXTB\000"
"tSXTH\000tSpill\000tTPsoft\000tTST\000tUXTB\000tUXTH\000";
return Strs+InstAsmOffset[Opcode];
}
#endif