//===- TableGen'erated file -------------------------------------*- C++ -*-===//
//
// Target Instruction Descriptors
//
// Automatically generated file, do not edit!
//
//===----------------------------------------------------------------------===//

namespace llvm {

static const unsigned ImplicitList1[] = { ARM::CPSR, 0 };
static const TargetRegisterClass* Barriers1[] = { &ARM::CCRRegClass, NULL };
static const unsigned ImplicitList2[] = { ARM::SP, 0 };
static const TargetRegisterClass* Barriers2[] = { &ARM::CCRRegClass, &ARM::DPR_8RegClass, NULL };
static const unsigned ImplicitList3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12, ARM::LR, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::CPSR, ARM::FPSCR, 0 };
static const unsigned ImplicitList4[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R9, ARM::R12, ARM::LR, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::CPSR, ARM::FPSCR, 0 };
static const unsigned ImplicitList5[] = { ARM::FPSCR, 0 };
static const TargetRegisterClass* Barriers3[] = { &ARM::DPRRegClass, &ARM::DPR_8RegClass, &ARM::DPR_VFP2RegClass, &ARM::tGPRRegClass, NULL };
static const unsigned ImplicitList6[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 0 };
static const unsigned ImplicitList7[] = { ARM::R0, ARM::R12, ARM::LR, ARM::CPSR, 0 };
static const unsigned ImplicitList8[] = { ARM::LR, 0 };
static const TargetRegisterClass* Barriers4[] = { &ARM::tGPRRegClass, NULL };
static const unsigned ImplicitList9[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, 0 };
static const unsigned ImplicitList10[] = { ARM::R0, ARM::LR, 0 };

static const TargetOperandInfo OperandInfo2[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo3[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo4[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo5[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
static const TargetOperandInfo OperandInfo6[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
static const TargetOperandInfo OperandInfo7[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
static const TargetOperandInfo OperandInfo8[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo9[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo10[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo11[] = { { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo12[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo13[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo14[] = { { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo15[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo16[] = { { ARM::GPRRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo17[] = { { ARM::tGPRRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo18[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo19[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo20[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo21[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo22[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo23[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo24[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo25[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo26[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo27[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo28[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo29[] = { { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo30[] = { { ARM::SPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo31[] = { { 0, 0, 0 }, { 0, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo32[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo33[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo34[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo35[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo36[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo37[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo38[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo39[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo40[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo41[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo42[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
static const TargetOperandInfo OperandInfo43[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo44[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo45[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo46[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
static const TargetOperandInfo OperandInfo47[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
static const TargetOperandInfo OperandInfo48[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
static const TargetOperandInfo OperandInfo49[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo50[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo51[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo52[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo53[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo54[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo55[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo56[] = { { ARM::GPRRegClassID, 0, (1 << TOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo57[] = { { ARM::GPRRegClassID, 0, (1 << TOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo58[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo59[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo60[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo61[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo62[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo63[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo64[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo65[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo66[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo67[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo68[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo69[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo70[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo71[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo72[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo73[] = { { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo74[] = { { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo75[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo76[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo77[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo78[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo79[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo80[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo81[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo82[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo83[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo84[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo85[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo86[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo87[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo88[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo89[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo90[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo91[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo92[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo93[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo94[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo95[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((4 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo96[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo97[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo98[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo99[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo100[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo101[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo102[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo103[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo104[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo105[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo106[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo107[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo108[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo109[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo110[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo111[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo112[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo113[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo114[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo115[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo116[] = { { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo117[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo118[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo119[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo120[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo121[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo122[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo123[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo124[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo125[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo126[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo127[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo128[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo129[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo130[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo131[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo132[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo133[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo134[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo135[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo136[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo137[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo138[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo139[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo140[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo141[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo142[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo143[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo144[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo145[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo146[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo147[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo148[] = { { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo149[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo150[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo151[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo152[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
static const TargetOperandInfo OperandInfo153[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
static const TargetOperandInfo OperandInfo154[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo155[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo156[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo157[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo158[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo159[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo160[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo161[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo162[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo163[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo164[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo165[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo166[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo167[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo168[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo169[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo170[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo171[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo172[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo173[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo174[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo175[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo176[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo177[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };

static const TargetInstrDesc ARMInsts[] = {
  { 0,	0,	0,	128,	"PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 },  // Inst #0 = PHI
  { 1,	0,	0,	128,	"INLINEASM", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 },  // Inst #1 = INLINEASM
  { 2,	1,	0,	128,	"DBG_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo14 },  // Inst #2 = DBG_LABEL
  { 3,	1,	0,	128,	"EH_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo14 },  // Inst #3 = EH_LABEL
  { 4,	1,	0,	128,	"GC_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo14 },  // Inst #4 = GC_LABEL
  { 5,	0,	0,	128,	"KILL", 0|(1<<TID::Variadic), 0, NULL, NULL, NULL, 0 },  // Inst #5 = KILL
  { 6,	3,	1,	128,	"EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo28 },  // Inst #6 = EXTRACT_SUBREG
  { 7,	4,	1,	128,	"INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo31 },  // Inst #7 = INSERT_SUBREG
  { 8,	1,	1,	128,	"IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo14 },  // Inst #8 = IMPLICIT_DEF
  { 9,	4,	1,	128,	"SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo58 },  // Inst #9 = SUBREG_TO_REG
  { 10,	3,	1,	128,	"COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo28 },  // Inst #10 = COPY_TO_REGCLASS
  { 11,	0,	0,	128,	"DBG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 },  // Inst #11 = DBG_VALUE
  { 12,	3,	1,	88,	"ADCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #12 = ADCSSri
  { 13,	3,	1,	89,	"ADCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 },  // Inst #13 = ADCSSrr
  { 14,	5,	1,	91,	"ADCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 },  // Inst #14 = ADCSSrs
  { 15,	6,	1,	88,	"ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 },  // Inst #15 = ADCri
  { 16,	6,	1,	89,	"ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo6 },  // Inst #16 = ADCrr
  { 17,	8,	1,	91,	"ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 },  // Inst #17 = ADCrs
  { 18,	5,	1,	88,	"ADDSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 },  // Inst #18 = ADDSri
  { 19,	5,	1,	89,	"ADDSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 },  // Inst #19 = ADDSrr
  { 20,	7,	1,	91,	"ADDSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #20 = ADDSrs
  { 21,	6,	1,	88,	"ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #21 = ADDri
  { 22,	6,	1,	89,	"ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #22 = ADDrr
  { 23,	8,	1,	91,	"ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 },  // Inst #23 = ADDrs
  { 24,	3,	0,	128,	"ADJCALLSTACKDOWN", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo11 },  // Inst #24 = ADJCALLSTACKDOWN
  { 25,	4,	0,	128,	"ADJCALLSTACKUP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo12 },  // Inst #25 = ADJCALLSTACKUP
  { 26,	6,	1,	88,	"ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #26 = ANDri
  { 27,	6,	1,	89,	"ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #27 = ANDrr
  { 28,	8,	1,	91,	"ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 },  // Inst #28 = ANDrs
  { 29,	4,	1,	128,	"ATOMIC_CMP_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #29 = ATOMIC_CMP_SWAP_I16
  { 30,	4,	1,	128,	"ATOMIC_CMP_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #30 = ATOMIC_CMP_SWAP_I32
  { 31,	4,	1,	128,	"ATOMIC_CMP_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #31 = ATOMIC_CMP_SWAP_I8
  { 32,	3,	1,	128,	"ATOMIC_LOAD_ADD_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #32 = ATOMIC_LOAD_ADD_I16
  { 33,	3,	1,	128,	"ATOMIC_LOAD_ADD_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #33 = ATOMIC_LOAD_ADD_I32
  { 34,	3,	1,	128,	"ATOMIC_LOAD_ADD_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #34 = ATOMIC_LOAD_ADD_I8
  { 35,	3,	1,	128,	"ATOMIC_LOAD_AND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #35 = ATOMIC_LOAD_AND_I16
  { 36,	3,	1,	128,	"ATOMIC_LOAD_AND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #36 = ATOMIC_LOAD_AND_I32
  { 37,	3,	1,	128,	"ATOMIC_LOAD_AND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #37 = ATOMIC_LOAD_AND_I8
  { 38,	3,	1,	128,	"ATOMIC_LOAD_NAND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #38 = ATOMIC_LOAD_NAND_I16
  { 39,	3,	1,	128,	"ATOMIC_LOAD_NAND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #39 = ATOMIC_LOAD_NAND_I32
  { 40,	3,	1,	128,	"ATOMIC_LOAD_NAND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #40 = ATOMIC_LOAD_NAND_I8
  { 41,	3,	1,	128,	"ATOMIC_LOAD_OR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #41 = ATOMIC_LOAD_OR_I16
  { 42,	3,	1,	128,	"ATOMIC_LOAD_OR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #42 = ATOMIC_LOAD_OR_I32
  { 43,	3,	1,	128,	"ATOMIC_LOAD_OR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #43 = ATOMIC_LOAD_OR_I8
  { 44,	3,	1,	128,	"ATOMIC_LOAD_SUB_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #44 = ATOMIC_LOAD_SUB_I16
  { 45,	3,	1,	128,	"ATOMIC_LOAD_SUB_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #45 = ATOMIC_LOAD_SUB_I32
  { 46,	3,	1,	128,	"ATOMIC_LOAD_SUB_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #46 = ATOMIC_LOAD_SUB_I8
  { 47,	3,	1,	128,	"ATOMIC_LOAD_XOR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #47 = ATOMIC_LOAD_XOR_I16
  { 48,	3,	1,	128,	"ATOMIC_LOAD_XOR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #48 = ATOMIC_LOAD_XOR_I32
  { 49,	3,	1,	128,	"ATOMIC_LOAD_XOR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #49 = ATOMIC_LOAD_XOR_I8
  { 50,	3,	1,	128,	"ATOMIC_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #50 = ATOMIC_SWAP_I16
  { 51,	3,	1,	128,	"ATOMIC_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #51 = ATOMIC_SWAP_I32
  { 52,	3,	1,	128,	"ATOMIC_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 },  // Inst #52 = ATOMIC_SWAP_I8
  { 53,	1,	0,	0,	"B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo14 },  // Inst #53 = B
  { 54,	5,	1,	126,	"BFC", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo15 },  // Inst #54 = BFC
  { 55,	5,	1,	126,	"BFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #55 = BFI
  { 56,	6,	1,	88,	"BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #56 = BICri
  { 57,	6,	1,	89,	"BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #57 = BICrr
  { 58,	8,	1,	91,	"BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 },  // Inst #58 = BICrs
  { 59,	3,	0,	128,	"BKPT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #59 = BKPT
  { 60,	1,	0,	0,	"BL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 },  // Inst #60 = BL
  { 61,	1,	0,	0,	"BLX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 },  // Inst #61 = BLX
  { 62,	1,	0,	0,	"BLXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 },  // Inst #62 = BLXr9
  { 63,	3,	0,	0,	"BL_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo11 },  // Inst #63 = BL_pred
  { 64,	1,	0,	0,	"BLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 },  // Inst #64 = BLr9
  { 65,	3,	0,	0,	"BLr9_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo11 },  // Inst #65 = BLr9_pred
  { 66,	1,	0,	0,	"BMOVPCRX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo17 },  // Inst #66 = BMOVPCRX
  { 67,	1,	0,	0,	"BMOVPCRXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo17 },  // Inst #67 = BMOVPCRXr9
  { 68,	1,	0,	0,	"BRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo16 },  // Inst #68 = BRIND
  { 69,	4,	0,	0,	"BR_JTadd", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo18 },  // Inst #69 = BR_JTadd
  { 70,	5,	0,	0,	"BR_JTm", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo19 },  // Inst #70 = BR_JTm
  { 71,	3,	0,	0,	"BR_JTr", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo20 },  // Inst #71 = BR_JTr
  { 72,	1,	0,	0,	"BX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo17 },  // Inst #72 = BX
  { 73,	3,	0,	128,	"BXJ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 },  // Inst #73 = BXJ
  { 74,	2,	0,	0,	"BX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #74 = BX_RET
  { 75,	1,	0,	0,	"BXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo17 },  // Inst #75 = BXr9
  { 76,	3,	0,	0,	"Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #76 = Bcc
  { 77,	8,	0,	128,	"CDP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo23 },  // Inst #77 = CDP
  { 78,	6,	0,	128,	"CDP2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo24 },  // Inst #78 = CDP2
  { 79,	0,	0,	128,	"CLREX", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #79 = CLREX
  { 80,	4,	1,	125,	"CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #80 = CLZ
  { 81,	4,	0,	97,	"CMNzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #81 = CMNzri
  { 82,	4,	0,	98,	"CMNzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #82 = CMNzrr
  { 83,	6,	0,	100,	"CMNzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #83 = CMNzrs
  { 84,	4,	0,	97,	"CMPri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #84 = CMPri
  { 85,	4,	0,	98,	"CMPrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #85 = CMPrr
  { 86,	6,	0,	100,	"CMPrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #86 = CMPrs
  { 87,	4,	0,	97,	"CMPzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #87 = CMPzri
  { 88,	4,	0,	98,	"CMPzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #88 = CMPzrr
  { 89,	6,	0,	100,	"CMPzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #89 = CMPzrs
  { 90,	3,	0,	128,	"CONSTPOOL_ENTRY", 0|(1<<TID::NotDuplicable), 0|(1<<4), NULL, NULL, NULL, OperandInfo28 },  // Inst #90 = CONSTPOOL_ENTRY
  { 91,	1,	0,	128,	"CPS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo14 },  // Inst #91 = CPS
  { 92,	3,	0,	128,	"DBG", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #92 = DBG
  { 93,	0,	0,	128,	"DMBish", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #93 = DMBish
  { 94,	0,	0,	128,	"DMBishst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #94 = DMBishst
  { 95,	0,	0,	128,	"DMBnsh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #95 = DMBnsh
  { 96,	0,	0,	128,	"DMBnshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #96 = DMBnshst
  { 97,	0,	0,	128,	"DMBosh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #97 = DMBosh
  { 98,	0,	0,	128,	"DMBoshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #98 = DMBoshst
  { 99,	0,	0,	128,	"DMBst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #99 = DMBst
  { 100,	0,	0,	128,	"DSBish", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #100 = DSBish
  { 101,	0,	0,	128,	"DSBishst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #101 = DSBishst
  { 102,	0,	0,	128,	"DSBnsh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #102 = DSBnsh
  { 103,	0,	0,	128,	"DSBnshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #103 = DSBnshst
  { 104,	0,	0,	128,	"DSBosh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #104 = DSBosh
  { 105,	0,	0,	128,	"DSBoshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #105 = DSBoshst
  { 106,	0,	0,	128,	"DSBst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #106 = DSBst
  { 107,	6,	1,	88,	"EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #107 = EORri
  { 108,	6,	1,	89,	"EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #108 = EORrr
  { 109,	8,	1,	91,	"EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 },  // Inst #109 = EORrs
  { 110,	4,	1,	26,	"FCONSTD", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo29 },  // Inst #110 = FCONSTD
  { 111,	4,	1,	26,	"FCONSTS", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo30 },  // Inst #111 = FCONSTS
  { 112,	2,	0,	82,	"FMSTAT", 0|(1<<TID::Predicable), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #112 = FMSTAT
  { 113,	0,	0,	128,	"ISBsy", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #113 = ISBsy
  { 114,	1,	0,	128,	"Int_MemBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 },  // Inst #114 = Int_MemBarrierV6
  { 115,	0,	0,	128,	"Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 },  // Inst #115 = Int_MemBarrierV7
  { 116,	1,	0,	128,	"Int_SyncBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 },  // Inst #116 = Int_SyncBarrierV6
  { 117,	0,	0,	128,	"Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 },  // Inst #117 = Int_SyncBarrierV7
  { 118,	2,	0,	128,	"Int_eh_sjlj_setjmp", 0, 0|(1<<4), NULL, ImplicitList6, Barriers3, OperandInfo32 },  // Inst #118 = Int_eh_sjlj_setjmp
  { 119,	7,	0,	128,	"LDC2L_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #119 = LDC2L_OFFSET
  { 120,	6,	0,	128,	"LDC2L_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 },  // Inst #120 = LDC2L_OPTION
  { 121,	7,	0,	128,	"LDC2L_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #121 = LDC2L_POST
  { 122,	7,	0,	128,	"LDC2L_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #122 = LDC2L_PRE
  { 123,	7,	0,	128,	"LDC2_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #123 = LDC2_OFFSET
  { 124,	6,	0,	128,	"LDC2_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 },  // Inst #124 = LDC2_OPTION
  { 125,	7,	0,	128,	"LDC2_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #125 = LDC2_POST
  { 126,	7,	0,	128,	"LDC2_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #126 = LDC2_PRE
  { 127,	7,	0,	128,	"LDCL_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #127 = LDCL_OFFSET
  { 128,	6,	0,	128,	"LDCL_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 },  // Inst #128 = LDCL_OPTION
  { 129,	7,	0,	128,	"LDCL_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #129 = LDCL_POST
  { 130,	7,	0,	128,	"LDCL_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #130 = LDCL_PRE
  { 131,	7,	0,	128,	"LDC_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #131 = LDC_OFFSET
  { 132,	6,	0,	128,	"LDC_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 },  // Inst #132 = LDC_OPTION
  { 133,	7,	0,	128,	"LDC_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #133 = LDC_POST
  { 134,	7,	0,	128,	"LDC_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #134 = LDC_PRE
  { 135,	5,	0,	103,	"LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo35 },  // Inst #135 = LDM
  { 136,	5,	0,	0,	"LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo35 },  // Inst #136 = LDM_RET
  { 137,	6,	1,	104,	"LDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #137 = LDR
  { 138,	6,	1,	104,	"LDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #138 = LDRB
  { 139,	7,	2,	105,	"LDRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #139 = LDRBT
  { 140,	7,	2,	105,	"LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #140 = LDRB_POST
  { 141,	7,	2,	105,	"LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #141 = LDRB_PRE
  { 142,	7,	2,	104,	"LDRD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo10 },  // Inst #142 = LDRD
  { 143,	8,	3,	104,	"LDRD_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo37 },  // Inst #143 = LDRD_POST
  { 144,	8,	3,	104,	"LDRD_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo37 },  // Inst #144 = LDRD_PRE
  { 145,	4,	1,	128,	"LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #145 = LDREX
  { 146,	4,	1,	128,	"LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #146 = LDREXB
  { 147,	5,	2,	128,	"LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #147 = LDREXD
  { 148,	4,	1,	128,	"LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #148 = LDREXH
  { 149,	6,	1,	104,	"LDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #149 = LDRH
  { 150,	7,	2,	105,	"LDRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #150 = LDRHT
  { 151,	7,	2,	105,	"LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #151 = LDRH_POST
  { 152,	7,	2,	105,	"LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #152 = LDRH_PRE
  { 153,	6,	1,	104,	"LDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #153 = LDRSB
  { 154,	7,	2,	105,	"LDRSBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #154 = LDRSBT
  { 155,	7,	2,	105,	"LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #155 = LDRSB_POST
  { 156,	7,	2,	105,	"LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #156 = LDRSB_PRE
  { 157,	6,	1,	104,	"LDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #157 = LDRSH
  { 158,	7,	2,	105,	"LDRSHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #158 = LDRSHT
  { 159,	7,	2,	105,	"LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #159 = LDRSH_POST
  { 160,	7,	2,	105,	"LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #160 = LDRSH_PRE
  { 161,	7,	2,	105,	"LDRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #161 = LDRT
  { 162,	7,	2,	105,	"LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #162 = LDR_POST
  { 163,	7,	2,	105,	"LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 },  // Inst #163 = LDR_PRE
  { 164,	6,	1,	104,	"LDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #164 = LDRcp
  { 165,	4,	1,	88,	"LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo26 },  // Inst #165 = LEApcrel
  { 166,	5,	1,	88,	"LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo38 },  // Inst #166 = LEApcrelJT
  { 167,	8,	0,	128,	"MCR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo39 },  // Inst #167 = MCR
  { 168,	6,	0,	128,	"MCR2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo40 },  // Inst #168 = MCR2
  { 169,	7,	0,	128,	"MCRR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #169 = MCRR
  { 170,	5,	0,	128,	"MCRR2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo41 },  // Inst #170 = MCRR2
  { 171,	7,	1,	109,	"MLA", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 },  // Inst #171 = MLA
  { 172,	6,	1,	109,	"MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #172 = MLS
  { 173,	5,	1,	93,	"MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 },  // Inst #173 = MOVCCi
  { 174,	5,	1,	94,	"MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo44 },  // Inst #174 = MOVCCr
  { 175,	7,	1,	96,	"MOVCCs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo45 },  // Inst #175 = MOVCCs
  { 176,	2,	0,	0,	"MOVPCLR", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #176 = MOVPCLR
  { 177,	1,	0,	0,	"MOVPCRX", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo16 },  // Inst #177 = MOVPCRX
  { 178,	5,	1,	111,	"MOVTi16", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 },  // Inst #178 = MOVTi16
  { 179,	5,	1,	111,	"MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo46 },  // Inst #179 = MOVi
  { 180,	4,	1,	111,	"MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo26 },  // Inst #180 = MOVi16
  { 181,	4,	1,	111,	"MOVi2pieces", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo26 },  // Inst #181 = MOVi2pieces
  { 182,	4,	1,	111,	"MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo26 },  // Inst #182 = MOVi32imm
  { 183,	5,	1,	112,	"MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo47 },  // Inst #183 = MOVr
  { 184,	5,	1,	113,	"MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(1<<15), ImplicitList1, NULL, NULL, OperandInfo47 },  // Inst #184 = MOVrx
  { 185,	7,	1,	114,	"MOVs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo48 },  // Inst #185 = MOVs
  { 186,	4,	1,	113,	"MOVsra_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #186 = MOVsra_flag
  { 187,	4,	1,	113,	"MOVsrl_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #187 = MOVsrl_flag
  { 188,	8,	0,	128,	"MRC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo39 },  // Inst #188 = MRC
  { 189,	6,	0,	128,	"MRC2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo40 },  // Inst #189 = MRC2
  { 190,	7,	0,	128,	"MRRC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #190 = MRRC
  { 191,	5,	0,	128,	"MRRC2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo41 },  // Inst #191 = MRRC2
  { 192,	3,	1,	128,	"MRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 },  // Inst #192 = MRS
  { 193,	3,	1,	128,	"MRSsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 },  // Inst #193 = MRSsys
  { 194,	3,	0,	128,	"MSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 },  // Inst #194 = MSR
  { 195,	3,	0,	128,	"MSRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #195 = MSRi
  { 196,	3,	0,	128,	"MSRsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 },  // Inst #196 = MSRsys
  { 197,	3,	0,	128,	"MSRsysi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #197 = MSRsysi
  { 198,	6,	1,	116,	"MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #198 = MUL
  { 199,	5,	1,	111,	"MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo46 },  // Inst #199 = MVNi
  { 200,	5,	1,	112,	"MVNr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo47 },  // Inst #200 = MVNr
  { 201,	7,	1,	114,	"MVNs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo48 },  // Inst #201 = MVNs
  { 202,	2,	0,	128,	"NOP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #202 = NOP
  { 203,	6,	1,	88,	"ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #203 = ORRri
  { 204,	6,	1,	89,	"ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #204 = ORRrr
  { 205,	8,	1,	91,	"ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 },  // Inst #205 = ORRrs
  { 206,	5,	1,	89,	"PICADD", 0|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo8 },  // Inst #206 = PICADD
  { 207,	5,	1,	104,	"PICLDR", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 },  // Inst #207 = PICLDR
  { 208,	5,	1,	104,	"PICLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 },  // Inst #208 = PICLDRB
  { 209,	5,	1,	104,	"PICLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 },  // Inst #209 = PICLDRH
  { 210,	5,	1,	104,	"PICLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 },  // Inst #210 = PICLDRSB
  { 211,	5,	1,	104,	"PICLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 },  // Inst #211 = PICLDRSH
  { 212,	5,	0,	121,	"PICSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 },  // Inst #212 = PICSTR
  { 213,	5,	0,	121,	"PICSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 },  // Inst #213 = PICSTRB
  { 214,	5,	0,	121,	"PICSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 },  // Inst #214 = PICSTRH
  { 215,	6,	1,	90,	"PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #215 = PKHBT
  { 216,	6,	1,	90,	"PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #216 = PKHTB
  { 217,	2,	0,	128,	"PLDWi", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo49 },  // Inst #217 = PLDWi
  { 218,	3,	0,	128,	"PLDWr", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo2 },  // Inst #218 = PLDWr
  { 219,	2,	0,	128,	"PLDi", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo49 },  // Inst #219 = PLDi
  { 220,	3,	0,	128,	"PLDr", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo2 },  // Inst #220 = PLDr
  { 221,	2,	0,	128,	"PLIi", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo49 },  // Inst #221 = PLIi
  { 222,	3,	0,	128,	"PLIr", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo2 },  // Inst #222 = PLIr
  { 223,	5,	1,	89,	"QADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #223 = QADD
  { 224,	5,	1,	89,	"QADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #224 = QADD16
  { 225,	5,	1,	89,	"QADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #225 = QADD8
  { 226,	5,	1,	89,	"QASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #226 = QASX
  { 227,	5,	1,	89,	"QDADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #227 = QDADD
  { 228,	5,	1,	89,	"QDSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #228 = QDSUB
  { 229,	5,	1,	89,	"QSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #229 = QSAX
  { 230,	5,	1,	89,	"QSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #230 = QSUB
  { 231,	5,	1,	89,	"QSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #231 = QSUB16
  { 232,	5,	1,	89,	"QSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #232 = QSUB8
  { 233,	4,	1,	125,	"RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #233 = RBIT
  { 234,	4,	1,	125,	"REV", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #234 = REV
  { 235,	4,	1,	125,	"REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #235 = REV16
  { 236,	4,	1,	125,	"REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #236 = REVSH
  { 237,	3,	0,	128,	"RFE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo50 },  // Inst #237 = RFE
  { 238,	3,	0,	128,	"RFEW", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo50 },  // Inst #238 = RFEW
  { 239,	5,	1,	88,	"RSBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 },  // Inst #239 = RSBSri
  { 240,	7,	1,	91,	"RSBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #240 = RSBSrs
  { 241,	6,	1,	88,	"RSBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #241 = RSBri
  { 242,	8,	1,	91,	"RSBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 },  // Inst #242 = RSBrs
  { 243,	3,	1,	88,	"RSCSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #243 = RSCSri
  { 244,	5,	1,	91,	"RSCSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 },  // Inst #244 = RSCSrs
  { 245,	6,	1,	88,	"RSCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 },  // Inst #245 = RSCri
  { 246,	8,	1,	91,	"RSCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 },  // Inst #246 = RSCrs
  { 247,	5,	1,	89,	"SADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #247 = SADD16
  { 248,	5,	1,	89,	"SADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #248 = SADD8
  { 249,	5,	1,	89,	"SASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #249 = SASX
  { 250,	3,	1,	88,	"SBCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #250 = SBCSSri
  { 251,	3,	1,	89,	"SBCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 },  // Inst #251 = SBCSSrr
  { 252,	5,	1,	91,	"SBCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 },  // Inst #252 = SBCSSrs
  { 253,	6,	1,	88,	"SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 },  // Inst #253 = SBCri
  { 254,	6,	1,	89,	"SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo6 },  // Inst #254 = SBCrr
  { 255,	8,	1,	91,	"SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 },  // Inst #255 = SBCrs
  { 256,	6,	1,	88,	"SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo51 },  // Inst #256 = SBFX
  { 257,	5,	1,	128,	"SEL", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #257 = SEL
  { 258,	0,	0,	128,	"SETENDBE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #258 = SETENDBE
  { 259,	0,	0,	128,	"SETENDLE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 },  // Inst #259 = SETENDLE
  { 260,	2,	0,	128,	"SEV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #260 = SEV
  { 261,	5,	1,	89,	"SHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #261 = SHADD16
  { 262,	5,	1,	89,	"SHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #262 = SHADD8
  { 263,	5,	1,	89,	"SHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #263 = SHASX
  { 264,	5,	1,	89,	"SHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #264 = SHSAX
  { 265,	5,	1,	89,	"SHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #265 = SHSUB16
  { 266,	5,	1,	89,	"SHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #266 = SHSUB8
  { 267,	3,	0,	128,	"SMC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #267 = SMC
  { 268,	6,	1,	108,	"SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #268 = SMLABB
  { 269,	6,	1,	108,	"SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #269 = SMLABT
  { 270,	6,	1,	128,	"SMLAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #270 = SMLAD
  { 271,	6,	1,	128,	"SMLADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #271 = SMLADX
  { 272,	7,	2,	110,	"SMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 },  // Inst #272 = SMLAL
  { 273,	6,	2,	110,	"SMLALBB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #273 = SMLALBB
  { 274,	6,	2,	110,	"SMLALBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #274 = SMLALBT
  { 275,	6,	2,	128,	"SMLALD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #275 = SMLALD
  { 276,	6,	2,	128,	"SMLALDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #276 = SMLALDX
  { 277,	6,	2,	110,	"SMLALTB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #277 = SMLALTB
  { 278,	6,	2,	110,	"SMLALTT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #278 = SMLALTT
  { 279,	6,	1,	108,	"SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #279 = SMLATB
  { 280,	6,	1,	108,	"SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #280 = SMLATT
  { 281,	6,	1,	108,	"SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #281 = SMLAWB
  { 282,	6,	1,	108,	"SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #282 = SMLAWT
  { 283,	6,	1,	128,	"SMLSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #283 = SMLSD
  { 284,	6,	1,	128,	"SMLSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #284 = SMLSDX
  { 285,	6,	2,	128,	"SMLSLD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #285 = SMLSLD
  { 286,	6,	2,	128,	"SMLSLDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #286 = SMLSLDX
  { 287,	6,	1,	109,	"SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #287 = SMMLA
  { 288,	6,	1,	109,	"SMMLAR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #288 = SMMLAR
  { 289,	6,	1,	109,	"SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #289 = SMMLS
  { 290,	6,	1,	109,	"SMMLSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #290 = SMMLSR
  { 291,	5,	1,	116,	"SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #291 = SMMUL
  { 292,	5,	1,	116,	"SMMULR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #292 = SMMULR
  { 293,	5,	1,	128,	"SMUAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #293 = SMUAD
  { 294,	5,	1,	128,	"SMUADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #294 = SMUADX
  { 295,	5,	1,	116,	"SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #295 = SMULBB
  { 296,	5,	1,	116,	"SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #296 = SMULBT
  { 297,	7,	2,	117,	"SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 },  // Inst #297 = SMULL
  { 298,	5,	1,	116,	"SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #298 = SMULTB
  { 299,	5,	1,	116,	"SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #299 = SMULTT
  { 300,	5,	1,	115,	"SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #300 = SMULWB
  { 301,	5,	1,	115,	"SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #301 = SMULWT
  { 302,	5,	1,	128,	"SMUSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #302 = SMUSD
  { 303,	5,	1,	128,	"SMUSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #303 = SMUSDX
  { 304,	3,	0,	128,	"SRS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo20 },  // Inst #304 = SRS
  { 305,	3,	0,	128,	"SRSW", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo20 },  // Inst #305 = SRSW
  { 306,	5,	1,	128,	"SSAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo52 },  // Inst #306 = SSAT16
  { 307,	6,	1,	128,	"SSATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 },  // Inst #307 = SSATasr
  { 308,	6,	1,	128,	"SSATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 },  // Inst #308 = SSATlsl
  { 309,	5,	1,	89,	"SSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #309 = SSAX
  { 310,	5,	1,	89,	"SSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #310 = SSUB16
  { 311,	5,	1,	89,	"SSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #311 = SSUB8
  { 312,	7,	0,	128,	"STC2L_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #312 = STC2L_OFFSET
  { 313,	6,	0,	128,	"STC2L_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 },  // Inst #313 = STC2L_OPTION
  { 314,	7,	0,	128,	"STC2L_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #314 = STC2L_POST
  { 315,	7,	0,	128,	"STC2L_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #315 = STC2L_PRE
  { 316,	7,	0,	128,	"STC2_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #316 = STC2_OFFSET
  { 317,	6,	0,	128,	"STC2_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 },  // Inst #317 = STC2_OPTION
  { 318,	7,	0,	128,	"STC2_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #318 = STC2_POST
  { 319,	7,	0,	128,	"STC2_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #319 = STC2_PRE
  { 320,	7,	0,	128,	"STCL_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #320 = STCL_OFFSET
  { 321,	6,	0,	128,	"STCL_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 },  // Inst #321 = STCL_OPTION
  { 322,	7,	0,	128,	"STCL_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #322 = STCL_POST
  { 323,	7,	0,	128,	"STCL_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #323 = STCL_PRE
  { 324,	7,	0,	128,	"STC_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #324 = STC_OFFSET
  { 325,	6,	0,	128,	"STC_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 },  // Inst #325 = STC_OPTION
  { 326,	7,	0,	128,	"STC_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #326 = STC_POST
  { 327,	7,	0,	128,	"STC_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 },  // Inst #327 = STC_PRE
  { 328,	5,	0,	120,	"STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo35 },  // Inst #328 = STM
  { 329,	6,	0,	121,	"STR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #329 = STR
  { 330,	6,	0,	121,	"STRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #330 = STRB
  { 331,	7,	1,	122,	"STRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 },  // Inst #331 = STRBT
  { 332,	7,	1,	122,	"STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 },  // Inst #332 = STRB_POST
  { 333,	7,	1,	122,	"STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 },  // Inst #333 = STRB_PRE
  { 334,	7,	0,	121,	"STRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo10 },  // Inst #334 = STRD
  { 335,	8,	1,	122,	"STRD_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo55 },  // Inst #335 = STRD_POST
  { 336,	8,	1,	122,	"STRD_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo55 },  // Inst #336 = STRD_PRE
  { 337,	5,	1,	128,	"STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo56 },  // Inst #337 = STREX
  { 338,	5,	1,	128,	"STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo56 },  // Inst #338 = STREXB
  { 339,	6,	1,	128,	"STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo57 },  // Inst #339 = STREXD
  { 340,	5,	1,	128,	"STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo56 },  // Inst #340 = STREXH
  { 341,	6,	0,	121,	"STRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #341 = STRH
  { 342,	7,	1,	122,	"STRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo54 },  // Inst #342 = STRHT
  { 343,	7,	1,	122,	"STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo54 },  // Inst #343 = STRH_POST
  { 344,	7,	1,	122,	"STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo54 },  // Inst #344 = STRH_PRE
  { 345,	7,	1,	122,	"STRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 },  // Inst #345 = STRT
  { 346,	7,	1,	122,	"STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 },  // Inst #346 = STR_POST
  { 347,	7,	1,	122,	"STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 },  // Inst #347 = STR_PRE
  { 348,	5,	1,	88,	"SUBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 },  // Inst #348 = SUBSri
  { 349,	5,	1,	89,	"SUBSrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 },  // Inst #349 = SUBSrr
  { 350,	7,	1,	91,	"SUBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #350 = SUBSrs
  { 351,	6,	1,	88,	"SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #351 = SUBri
  { 352,	6,	1,	89,	"SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #352 = SUBrr
  { 353,	8,	1,	91,	"SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 },  // Inst #353 = SUBrs
  { 354,	3,	0,	0,	"SVC", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #354 = SVC
  { 355,	5,	1,	128,	"SWP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #355 = SWP
  { 356,	5,	1,	128,	"SWPB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #356 = SWPB
  { 357,	5,	1,	89,	"SXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #357 = SXTAB16rr
  { 358,	6,	1,	90,	"SXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #358 = SXTAB16rr_rot
  { 359,	5,	1,	89,	"SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #359 = SXTABrr
  { 360,	6,	1,	90,	"SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #360 = SXTABrr_rot
  { 361,	5,	1,	89,	"SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #361 = SXTAHrr
  { 362,	6,	1,	90,	"SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #362 = SXTAHrr_rot
  { 363,	4,	1,	125,	"SXTB16r", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #363 = SXTB16r
  { 364,	5,	1,	126,	"SXTB16r_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #364 = SXTB16r_rot
  { 365,	4,	1,	125,	"SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #365 = SXTBr
  { 366,	5,	1,	126,	"SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #366 = SXTBr_rot
  { 367,	4,	1,	125,	"SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #367 = SXTHr
  { 368,	5,	1,	126,	"SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #368 = SXTHr_rot
  { 369,	4,	0,	97,	"TEQri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #369 = TEQri
  { 370,	4,	0,	98,	"TEQrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #370 = TEQrr
  { 371,	6,	0,	100,	"TEQrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #371 = TEQrs
  { 372,	0,	0,	0,	"TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(2<<9), NULL, ImplicitList7, Barriers1, 0 },  // Inst #372 = TPsoft
  { 373,	2,	0,	128,	"TRAP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #373 = TRAP
  { 374,	4,	0,	97,	"TSTri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #374 = TSTri
  { 375,	4,	0,	98,	"TSTrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #375 = TSTrr
  { 376,	6,	0,	100,	"TSTrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #376 = TSTrs
  { 377,	5,	1,	89,	"UADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #377 = UADD16
  { 378,	5,	1,	89,	"UADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #378 = UADD8
  { 379,	5,	1,	89,	"UASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #379 = UASX
  { 380,	6,	1,	88,	"UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo51 },  // Inst #380 = UBFX
  { 381,	5,	1,	89,	"UHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #381 = UHADD16
  { 382,	5,	1,	89,	"UHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #382 = UHADD8
  { 383,	5,	1,	89,	"UHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #383 = UHASX
  { 384,	5,	1,	89,	"UHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #384 = UHSAX
  { 385,	5,	1,	89,	"UHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #385 = UHSUB16
  { 386,	5,	1,	89,	"UHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #386 = UHSUB8
  { 387,	6,	2,	110,	"UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #387 = UMAAL
  { 388,	7,	2,	110,	"UMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 },  // Inst #388 = UMLAL
  { 389,	7,	2,	117,	"UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 },  // Inst #389 = UMULL
  { 390,	5,	1,	89,	"UQADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #390 = UQADD16
  { 391,	5,	1,	89,	"UQADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #391 = UQADD8
  { 392,	5,	1,	89,	"UQASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #392 = UQASX
  { 393,	5,	1,	89,	"UQSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #393 = UQSAX
  { 394,	5,	1,	89,	"UQSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #394 = UQSUB16
  { 395,	5,	1,	89,	"UQSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #395 = UQSUB8
  { 396,	5,	1,	128,	"USAD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #396 = USAD8
  { 397,	6,	1,	128,	"USADA8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #397 = USADA8
  { 398,	5,	1,	128,	"USAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo52 },  // Inst #398 = USAT16
  { 399,	6,	1,	128,	"USATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 },  // Inst #399 = USATasr
  { 400,	6,	1,	128,	"USATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 },  // Inst #400 = USATlsl
  { 401,	5,	1,	89,	"USAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #401 = USAX
  { 402,	5,	1,	89,	"USUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #402 = USUB16
  { 403,	5,	1,	89,	"USUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #403 = USUB8
  { 404,	5,	1,	89,	"UXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #404 = UXTAB16rr
  { 405,	6,	1,	90,	"UXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #405 = UXTAB16rr_rot
  { 406,	5,	1,	89,	"UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #406 = UXTABrr
  { 407,	6,	1,	90,	"UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #407 = UXTABrr_rot
  { 408,	5,	1,	89,	"UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #408 = UXTAHrr
  { 409,	6,	1,	90,	"UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #409 = UXTAHrr_rot
  { 410,	4,	1,	125,	"UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #410 = UXTB16r
  { 411,	5,	1,	126,	"UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #411 = UXTB16r_rot
  { 412,	4,	1,	125,	"UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #412 = UXTBr
  { 413,	5,	1,	126,	"UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #413 = UXTBr_rot
  { 414,	4,	1,	125,	"UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #414 = UXTHr
  { 415,	5,	1,	126,	"UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #415 = UXTHr_rot
  { 416,	6,	1,	17,	"VABALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #416 = VABALsv2i64
  { 417,	6,	1,	17,	"VABALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #417 = VABALsv4i32
  { 418,	6,	1,	17,	"VABALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #418 = VABALsv8i16
  { 419,	6,	1,	17,	"VABALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #419 = VABALuv2i64
  { 420,	6,	1,	17,	"VABALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #420 = VABALuv4i32
  { 421,	6,	1,	17,	"VABALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #421 = VABALuv8i16
  { 422,	6,	1,	18,	"VABAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #422 = VABAsv16i8
  { 423,	6,	1,	19,	"VABAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #423 = VABAsv2i32
  { 424,	6,	1,	17,	"VABAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #424 = VABAsv4i16
  { 425,	6,	1,	20,	"VABAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #425 = VABAsv4i32
  { 426,	6,	1,	18,	"VABAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #426 = VABAsv8i16
  { 427,	6,	1,	17,	"VABAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #427 = VABAsv8i8
  { 428,	6,	1,	18,	"VABAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #428 = VABAuv16i8
  { 429,	6,	1,	19,	"VABAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #429 = VABAuv2i32
  { 430,	6,	1,	17,	"VABAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #430 = VABAuv4i16
  { 431,	6,	1,	20,	"VABAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #431 = VABAuv4i32
  { 432,	6,	1,	18,	"VABAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #432 = VABAuv8i16
  { 433,	6,	1,	17,	"VABAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #433 = VABAuv8i8
  { 434,	5,	1,	4,	"VABDLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #434 = VABDLsv2i64
  { 435,	5,	1,	4,	"VABDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #435 = VABDLsv4i32
  { 436,	5,	1,	4,	"VABDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #436 = VABDLsv8i16
  { 437,	5,	1,	4,	"VABDLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #437 = VABDLuv2i64
  { 438,	5,	1,	4,	"VABDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #438 = VABDLuv4i32
  { 439,	5,	1,	4,	"VABDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #439 = VABDLuv8i16
  { 440,	5,	1,	1,	"VABDfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #440 = VABDfd
  { 441,	5,	1,	2,	"VABDfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #441 = VABDfq
  { 442,	5,	1,	4,	"VABDsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #442 = VABDsv16i8
  { 443,	5,	1,	3,	"VABDsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #443 = VABDsv2i32
  { 444,	5,	1,	3,	"VABDsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #444 = VABDsv4i16
  { 445,	5,	1,	4,	"VABDsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #445 = VABDsv4i32
  { 446,	5,	1,	4,	"VABDsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #446 = VABDsv8i16
  { 447,	5,	1,	3,	"VABDsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #447 = VABDsv8i8
  { 448,	5,	1,	4,	"VABDuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #448 = VABDuv16i8
  { 449,	5,	1,	3,	"VABDuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #449 = VABDuv2i32
  { 450,	5,	1,	3,	"VABDuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #450 = VABDuv4i16
  { 451,	5,	1,	4,	"VABDuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #451 = VABDuv4i32
  { 452,	5,	1,	4,	"VABDuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #452 = VABDuv8i16
  { 453,	5,	1,	3,	"VABDuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #453 = VABDuv8i8
  { 454,	4,	1,	87,	"VABSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #454 = VABSD
  { 455,	4,	1,	86,	"VABSS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 },  // Inst #455 = VABSS
  { 456,	4,	1,	57,	"VABSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #456 = VABSfd
  { 457,	4,	1,	57,	"VABSfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 },  // Inst #457 = VABSfd_sfp
  { 458,	4,	1,	58,	"VABSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #458 = VABSfq
  { 459,	4,	1,	60,	"VABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #459 = VABSv16i8
  { 460,	4,	1,	59,	"VABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #460 = VABSv2i32
  { 461,	4,	1,	59,	"VABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #461 = VABSv4i16
  { 462,	4,	1,	60,	"VABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #462 = VABSv4i32
  { 463,	4,	1,	60,	"VABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #463 = VABSv8i16
  { 464,	4,	1,	59,	"VABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #464 = VABSv8i8
  { 465,	5,	1,	1,	"VACGEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #465 = VACGEd
  { 466,	5,	1,	2,	"VACGEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #466 = VACGEq
  { 467,	5,	1,	1,	"VACGTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #467 = VACGTd
  { 468,	5,	1,	2,	"VACGTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #468 = VACGTq
  { 469,	5,	1,	62,	"VADDD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #469 = VADDD
  { 470,	5,	1,	3,	"VADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 },  // Inst #470 = VADDHNv2i32
  { 471,	5,	1,	3,	"VADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 },  // Inst #471 = VADDHNv4i16
  { 472,	5,	1,	3,	"VADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 },  // Inst #472 = VADDHNv8i8
  { 473,	5,	1,	44,	"VADDLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #473 = VADDLsv2i64
  { 474,	5,	1,	44,	"VADDLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #474 = VADDLsv4i32
  { 475,	5,	1,	44,	"VADDLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #475 = VADDLsv8i16
  { 476,	5,	1,	44,	"VADDLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #476 = VADDLuv2i64
  { 477,	5,	1,	44,	"VADDLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #477 = VADDLuv4i32
  { 478,	5,	1,	44,	"VADDLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #478 = VADDLuv8i16
  { 479,	5,	1,	61,	"VADDS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 },  // Inst #479 = VADDS
  { 480,	5,	1,	47,	"VADDWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 },  // Inst #480 = VADDWsv2i64
  { 481,	5,	1,	47,	"VADDWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 },  // Inst #481 = VADDWsv4i32
  { 482,	5,	1,	47,	"VADDWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 },  // Inst #482 = VADDWsv8i16
  { 483,	5,	1,	47,	"VADDWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 },  // Inst #483 = VADDWuv2i64
  { 484,	5,	1,	47,	"VADDWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 },  // Inst #484 = VADDWuv4i32
  { 485,	5,	1,	47,	"VADDWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 },  // Inst #485 = VADDWuv8i16
  { 486,	5,	1,	1,	"VADDfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #486 = VADDfd
  { 487,	5,	1,	1,	"VADDfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 },  // Inst #487 = VADDfd_sfp
  { 488,	5,	1,	2,	"VADDfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #488 = VADDfq
  { 489,	5,	1,	6,	"VADDv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #489 = VADDv16i8
  { 490,	5,	1,	5,	"VADDv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #490 = VADDv1i64
  { 491,	5,	1,	5,	"VADDv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #491 = VADDv2i32
  { 492,	5,	1,	6,	"VADDv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #492 = VADDv2i64
  { 493,	5,	1,	5,	"VADDv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #493 = VADDv4i16
  { 494,	5,	1,	6,	"VADDv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #494 = VADDv4i32
  { 495,	5,	1,	6,	"VADDv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #495 = VADDv8i16
  { 496,	5,	1,	5,	"VADDv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #496 = VADDv8i8
  { 497,	5,	1,	5,	"VANDd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #497 = VANDd
  { 498,	5,	1,	6,	"VANDq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #498 = VANDq
  { 499,	5,	1,	5,	"VBICd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #499 = VBICd
  { 500,	5,	1,	6,	"VBICq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #500 = VBICq
  { 501,	6,	1,	5,	"VBIFd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #501 = VBIFd
  { 502,	6,	1,	6,	"VBIFq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #502 = VBIFq
  { 503,	6,	1,	5,	"VBITd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #503 = VBITd
  { 504,	6,	1,	6,	"VBITq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #504 = VBITq
  { 505,	6,	1,	7,	"VBSLd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #505 = VBSLd
  { 506,	6,	1,	8,	"VBSLq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #506 = VBSLq
  { 507,	5,	1,	1,	"VCEQfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #507 = VCEQfd
  { 508,	5,	1,	2,	"VCEQfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #508 = VCEQfq
  { 509,	5,	1,	4,	"VCEQv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #509 = VCEQv16i8
  { 510,	5,	1,	3,	"VCEQv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #510 = VCEQv2i32
  { 511,	5,	1,	3,	"VCEQv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #511 = VCEQv4i16
  { 512,	5,	1,	4,	"VCEQv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #512 = VCEQv4i32
  { 513,	5,	1,	4,	"VCEQv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #513 = VCEQv8i16
  { 514,	5,	1,	3,	"VCEQv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #514 = VCEQv8i8
  { 515,	4,	1,	128,	"VCEQzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #515 = VCEQzv16i8
  { 516,	4,	1,	128,	"VCEQzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #516 = VCEQzv2f32
  { 517,	4,	1,	128,	"VCEQzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #517 = VCEQzv2i32
  { 518,	4,	1,	128,	"VCEQzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #518 = VCEQzv4f32
  { 519,	4,	1,	128,	"VCEQzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #519 = VCEQzv4i16
  { 520,	4,	1,	128,	"VCEQzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #520 = VCEQzv4i32
  { 521,	4,	1,	128,	"VCEQzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #521 = VCEQzv8i16
  { 522,	4,	1,	128,	"VCEQzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #522 = VCEQzv8i8
  { 523,	5,	1,	1,	"VCGEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #523 = VCGEfd
  { 524,	5,	1,	2,	"VCGEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #524 = VCGEfq
  { 525,	5,	1,	4,	"VCGEsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #525 = VCGEsv16i8
  { 526,	5,	1,	3,	"VCGEsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #526 = VCGEsv2i32
  { 527,	5,	1,	3,	"VCGEsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #527 = VCGEsv4i16
  { 528,	5,	1,	4,	"VCGEsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #528 = VCGEsv4i32
  { 529,	5,	1,	4,	"VCGEsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #529 = VCGEsv8i16
  { 530,	5,	1,	3,	"VCGEsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #530 = VCGEsv8i8
  { 531,	5,	1,	4,	"VCGEuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #531 = VCGEuv16i8
  { 532,	5,	1,	3,	"VCGEuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #532 = VCGEuv2i32
  { 533,	5,	1,	3,	"VCGEuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #533 = VCGEuv4i16
  { 534,	5,	1,	4,	"VCGEuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #534 = VCGEuv4i32
  { 535,	5,	1,	4,	"VCGEuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #535 = VCGEuv8i16
  { 536,	5,	1,	3,	"VCGEuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #536 = VCGEuv8i8
  { 537,	4,	1,	128,	"VCGEzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #537 = VCGEzv16i8
  { 538,	4,	1,	128,	"VCGEzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #538 = VCGEzv2f32
  { 539,	4,	1,	128,	"VCGEzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #539 = VCGEzv2i32
  { 540,	4,	1,	128,	"VCGEzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #540 = VCGEzv4f32
  { 541,	4,	1,	128,	"VCGEzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #541 = VCGEzv4i16
  { 542,	4,	1,	128,	"VCGEzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #542 = VCGEzv4i32
  { 543,	4,	1,	128,	"VCGEzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #543 = VCGEzv8i16
  { 544,	4,	1,	128,	"VCGEzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #544 = VCGEzv8i8
  { 545,	5,	1,	1,	"VCGTfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #545 = VCGTfd
  { 546,	5,	1,	2,	"VCGTfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #546 = VCGTfq
  { 547,	5,	1,	4,	"VCGTsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #547 = VCGTsv16i8
  { 548,	5,	1,	3,	"VCGTsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #548 = VCGTsv2i32
  { 549,	5,	1,	3,	"VCGTsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #549 = VCGTsv4i16
  { 550,	5,	1,	4,	"VCGTsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #550 = VCGTsv4i32
  { 551,	5,	1,	4,	"VCGTsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #551 = VCGTsv8i16
  { 552,	5,	1,	3,	"VCGTsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #552 = VCGTsv8i8
  { 553,	5,	1,	4,	"VCGTuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #553 = VCGTuv16i8
  { 554,	5,	1,	3,	"VCGTuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #554 = VCGTuv2i32
  { 555,	5,	1,	3,	"VCGTuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #555 = VCGTuv4i16
  { 556,	5,	1,	4,	"VCGTuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #556 = VCGTuv4i32
  { 557,	5,	1,	4,	"VCGTuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #557 = VCGTuv8i16
  { 558,	5,	1,	3,	"VCGTuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #558 = VCGTuv8i8
  { 559,	4,	1,	128,	"VCGTzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #559 = VCGTzv16i8
  { 560,	4,	1,	128,	"VCGTzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #560 = VCGTzv2f32
  { 561,	4,	1,	128,	"VCGTzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #561 = VCGTzv2i32
  { 562,	4,	1,	128,	"VCGTzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #562 = VCGTzv4f32
  { 563,	4,	1,	128,	"VCGTzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #563 = VCGTzv4i16
  { 564,	4,	1,	128,	"VCGTzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #564 = VCGTzv4i32
  { 565,	4,	1,	128,	"VCGTzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #565 = VCGTzv8i16
  { 566,	4,	1,	128,	"VCGTzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #566 = VCGTzv8i8
  { 567,	4,	1,	128,	"VCLEzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #567 = VCLEzv16i8
  { 568,	4,	1,	128,	"VCLEzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #568 = VCLEzv2f32
  { 569,	4,	1,	128,	"VCLEzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #569 = VCLEzv2i32
  { 570,	4,	1,	128,	"VCLEzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #570 = VCLEzv4f32
  { 571,	4,	1,	128,	"VCLEzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #571 = VCLEzv4i16
  { 572,	4,	1,	128,	"VCLEzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #572 = VCLEzv4i32
  { 573,	4,	1,	128,	"VCLEzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #573 = VCLEzv8i16
  { 574,	4,	1,	128,	"VCLEzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #574 = VCLEzv8i8
  { 575,	4,	1,	8,	"VCLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #575 = VCLSv16i8
  { 576,	4,	1,	7,	"VCLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #576 = VCLSv2i32
  { 577,	4,	1,	7,	"VCLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #577 = VCLSv4i16
  { 578,	4,	1,	8,	"VCLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #578 = VCLSv4i32
  { 579,	4,	1,	8,	"VCLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #579 = VCLSv8i16
  { 580,	4,	1,	7,	"VCLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #580 = VCLSv8i8
  { 581,	4,	1,	128,	"VCLTzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #581 = VCLTzv16i8
  { 582,	4,	1,	128,	"VCLTzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #582 = VCLTzv2f32
  { 583,	4,	1,	128,	"VCLTzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #583 = VCLTzv2i32
  { 584,	4,	1,	128,	"VCLTzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #584 = VCLTzv4f32
  { 585,	4,	1,	128,	"VCLTzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #585 = VCLTzv4i16
  { 586,	4,	1,	128,	"VCLTzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #586 = VCLTzv4i32
  { 587,	4,	1,	128,	"VCLTzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #587 = VCLTzv8i16
  { 588,	4,	1,	128,	"VCLTzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #588 = VCLTzv8i8
  { 589,	4,	1,	8,	"VCLZv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #589 = VCLZv16i8
  { 590,	4,	1,	7,	"VCLZv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #590 = VCLZv2i32
  { 591,	4,	1,	7,	"VCLZv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #591 = VCLZv4i16
  { 592,	4,	1,	8,	"VCLZv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #592 = VCLZv4i32
  { 593,	4,	1,	8,	"VCLZv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #593 = VCLZv8i16
  { 594,	4,	1,	7,	"VCLZv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #594 = VCLZv8i8
  { 595,	4,	0,	64,	"VCMPD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo65 },  // Inst #595 = VCMPD
  { 596,	4,	0,	64,	"VCMPED", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo65 },  // Inst #596 = VCMPED
  { 597,	4,	0,	63,	"VCMPES", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo66 },  // Inst #597 = VCMPES
  { 598,	3,	0,	64,	"VCMPEZD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo73 },  // Inst #598 = VCMPEZD
  { 599,	3,	0,	63,	"VCMPEZS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo74 },  // Inst #599 = VCMPEZS
  { 600,	4,	0,	63,	"VCMPS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo66 },  // Inst #600 = VCMPS
  { 601,	3,	0,	64,	"VCMPZD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo73 },  // Inst #601 = VCMPZD
  { 602,	3,	0,	63,	"VCMPZS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo74 },  // Inst #602 = VCMPZS
  { 603,	4,	1,	7,	"VCNTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #603 = VCNTd
  { 604,	4,	1,	8,	"VCNTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #604 = VCNTq
  { 605,	4,	1,	66,	"VCVTBHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 },  // Inst #605 = VCVTBHS
  { 606,	4,	1,	66,	"VCVTBSH", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 },  // Inst #606 = VCVTBSH
  { 607,	4,	1,	66,	"VCVTDS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo75 },  // Inst #607 = VCVTDS
  { 608,	4,	1,	69,	"VCVTSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 },  // Inst #608 = VCVTSD
  { 609,	4,	1,	66,	"VCVTTHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 },  // Inst #609 = VCVTTHS
  { 610,	4,	1,	66,	"VCVTTSH", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 },  // Inst #610 = VCVTTSH
  { 611,	4,	1,	57,	"VCVTf2sd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #611 = VCVTf2sd
  { 612,	4,	1,	57,	"VCVTf2sd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 },  // Inst #612 = VCVTf2sd_sfp
  { 613,	4,	1,	58,	"VCVTf2sq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #613 = VCVTf2sq
  { 614,	4,	1,	57,	"VCVTf2ud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #614 = VCVTf2ud
  { 615,	4,	1,	57,	"VCVTf2ud_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 },  // Inst #615 = VCVTf2ud_sfp
  { 616,	4,	1,	58,	"VCVTf2uq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #616 = VCVTf2uq
  { 617,	5,	1,	57,	"VCVTf2xsd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #617 = VCVTf2xsd
  { 618,	5,	1,	58,	"VCVTf2xsq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #618 = VCVTf2xsq
  { 619,	5,	1,	57,	"VCVTf2xud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #619 = VCVTf2xud
  { 620,	5,	1,	58,	"VCVTf2xuq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #620 = VCVTf2xuq
  { 621,	4,	1,	57,	"VCVTs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #621 = VCVTs2fd
  { 622,	4,	1,	57,	"VCVTs2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 },  // Inst #622 = VCVTs2fd_sfp
  { 623,	4,	1,	58,	"VCVTs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #623 = VCVTs2fq
  { 624,	4,	1,	57,	"VCVTu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #624 = VCVTu2fd
  { 625,	4,	1,	57,	"VCVTu2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 },  // Inst #625 = VCVTu2fd_sfp
  { 626,	4,	1,	58,	"VCVTu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #626 = VCVTu2fq
  { 627,	5,	1,	57,	"VCVTxs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #627 = VCVTxs2fd
  { 628,	5,	1,	58,	"VCVTxs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #628 = VCVTxs2fq
  { 629,	5,	1,	57,	"VCVTxu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #629 = VCVTxu2fd
  { 630,	5,	1,	58,	"VCVTxu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #630 = VCVTxu2fq
  { 631,	5,	1,	72,	"VDIVD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #631 = VDIVD
  { 632,	5,	1,	71,	"VDIVS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 },  // Inst #632 = VDIVS
  { 633,	4,	1,	24,	"VDUP16d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 },  // Inst #633 = VDUP16d
  { 634,	4,	1,	24,	"VDUP16q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 },  // Inst #634 = VDUP16q
  { 635,	4,	1,	24,	"VDUP32d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 },  // Inst #635 = VDUP32d
  { 636,	4,	1,	24,	"VDUP32q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 },  // Inst #636 = VDUP32q
  { 637,	4,	1,	24,	"VDUP8d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 },  // Inst #637 = VDUP8d
  { 638,	4,	1,	24,	"VDUP8q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 },  // Inst #638 = VDUP8q
  { 639,	5,	1,	21,	"VDUPLN16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #639 = VDUPLN16d
  { 640,	5,	1,	21,	"VDUPLN16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 },  // Inst #640 = VDUPLN16q
  { 641,	5,	1,	21,	"VDUPLN32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #641 = VDUPLN32d
  { 642,	5,	1,	21,	"VDUPLN32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 },  // Inst #642 = VDUPLN32q
  { 643,	5,	1,	21,	"VDUPLN8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #643 = VDUPLN8d
  { 644,	5,	1,	21,	"VDUPLN8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 },  // Inst #644 = VDUPLN8q
  { 645,	5,	1,	21,	"VDUPLNfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #645 = VDUPLNfd
  { 646,	5,	1,	21,	"VDUPLNfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 },  // Inst #646 = VDUPLNfq
  { 647,	4,	1,	24,	"VDUPfd", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 },  // Inst #647 = VDUPfd
  { 648,	4,	1,	21,	"VDUPfdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 },  // Inst #648 = VDUPfdf
  { 649,	4,	1,	24,	"VDUPfq", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 },  // Inst #649 = VDUPfq
  { 650,	4,	1,	21,	"VDUPfqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 },  // Inst #650 = VDUPfqf
  { 651,	5,	1,	5,	"VEORd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #651 = VEORd
  { 652,	5,	1,	6,	"VEORq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #652 = VEORq
  { 653,	6,	1,	9,	"VEXTd16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 },  // Inst #653 = VEXTd16
  { 654,	6,	1,	9,	"VEXTd32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 },  // Inst #654 = VEXTd32
  { 655,	6,	1,	9,	"VEXTd8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 },  // Inst #655 = VEXTd8
  { 656,	6,	1,	9,	"VEXTdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 },  // Inst #656 = VEXTdf
  { 657,	6,	1,	10,	"VEXTq16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 },  // Inst #657 = VEXTq16
  { 658,	6,	1,	10,	"VEXTq32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 },  // Inst #658 = VEXTq32
  { 659,	6,	1,	10,	"VEXTq8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 },  // Inst #659 = VEXTq8
  { 660,	6,	1,	10,	"VEXTqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 },  // Inst #660 = VEXTqf
  { 661,	5,	1,	28,	"VGETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 },  // Inst #661 = VGETLNi32
  { 662,	5,	1,	28,	"VGETLNs16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 },  // Inst #662 = VGETLNs16
  { 663,	5,	1,	28,	"VGETLNs8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 },  // Inst #663 = VGETLNs8
  { 664,	5,	1,	28,	"VGETLNu16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 },  // Inst #664 = VGETLNu16
  { 665,	5,	1,	28,	"VGETLNu8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 },  // Inst #665 = VGETLNu8
  { 666,	5,	1,	4,	"VHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #666 = VHADDsv16i8
  { 667,	5,	1,	3,	"VHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #667 = VHADDsv2i32
  { 668,	5,	1,	3,	"VHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #668 = VHADDsv4i16
  { 669,	5,	1,	4,	"VHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #669 = VHADDsv4i32
  { 670,	5,	1,	4,	"VHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #670 = VHADDsv8i16
  { 671,	5,	1,	3,	"VHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #671 = VHADDsv8i8
  { 672,	5,	1,	4,	"VHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #672 = VHADDuv16i8
  { 673,	5,	1,	3,	"VHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #673 = VHADDuv2i32
  { 674,	5,	1,	3,	"VHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #674 = VHADDuv4i16
  { 675,	5,	1,	4,	"VHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #675 = VHADDuv4i32
  { 676,	5,	1,	4,	"VHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #676 = VHADDuv8i16
  { 677,	5,	1,	3,	"VHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #677 = VHADDuv8i8
  { 678,	5,	1,	4,	"VHSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #678 = VHSUBsv16i8
  { 679,	5,	1,	3,	"VHSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #679 = VHSUBsv2i32
  { 680,	5,	1,	3,	"VHSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #680 = VHSUBsv4i16
  { 681,	5,	1,	4,	"VHSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #681 = VHSUBsv4i32
  { 682,	5,	1,	4,	"VHSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #682 = VHSUBsv8i16
  { 683,	5,	1,	3,	"VHSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #683 = VHSUBsv8i8
  { 684,	5,	1,	4,	"VHSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #684 = VHSUBuv16i8
  { 685,	5,	1,	3,	"VHSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #685 = VHSUBuv2i32
  { 686,	5,	1,	3,	"VHSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #686 = VHSUBuv4i16
  { 687,	5,	1,	4,	"VHSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #687 = VHSUBuv4i32
  { 688,	5,	1,	4,	"VHSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #688 = VHSUBuv8i16
  { 689,	5,	1,	3,	"VHSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #689 = VHSUBuv8i8
  { 690,	7,	1,	11,	"VLD1d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 },  // Inst #690 = VLD1d16
  { 691,	10,	4,	11,	"VLD1d16Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 },  // Inst #691 = VLD1d16Q
  { 692,	9,	3,	11,	"VLD1d16T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 },  // Inst #692 = VLD1d16T
  { 693,	7,	1,	11,	"VLD1d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 },  // Inst #693 = VLD1d32
  { 694,	10,	4,	11,	"VLD1d32Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 },  // Inst #694 = VLD1d32Q
  { 695,	9,	3,	11,	"VLD1d32T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 },  // Inst #695 = VLD1d32T
  { 696,	7,	1,	11,	"VLD1d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 },  // Inst #696 = VLD1d64
  { 697,	7,	1,	11,	"VLD1d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 },  // Inst #697 = VLD1d8
  { 698,	10,	4,	11,	"VLD1d8Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 },  // Inst #698 = VLD1d8Q
  { 699,	9,	3,	11,	"VLD1d8T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 },  // Inst #699 = VLD1d8T
  { 700,	7,	1,	11,	"VLD1df", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 },  // Inst #700 = VLD1df
  { 701,	7,	1,	11,	"VLD1q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 },  // Inst #701 = VLD1q16
  { 702,	7,	1,	11,	"VLD1q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 },  // Inst #702 = VLD1q32
  { 703,	7,	1,	11,	"VLD1q64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 },  // Inst #703 = VLD1q64
  { 704,	7,	1,	11,	"VLD1q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 },  // Inst #704 = VLD1q8
  { 705,	7,	1,	11,	"VLD1qf", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 },  // Inst #705 = VLD1qf
  { 706,	11,	2,	12,	"VLD2LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 },  // Inst #706 = VLD2LNd16
  { 707,	11,	2,	12,	"VLD2LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 },  // Inst #707 = VLD2LNd32
  { 708,	11,	2,	12,	"VLD2LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 },  // Inst #708 = VLD2LNd8
  { 709,	11,	2,	12,	"VLD2LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 },  // Inst #709 = VLD2LNq16a
  { 710,	11,	2,	12,	"VLD2LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 },  // Inst #710 = VLD2LNq16b
  { 711,	11,	2,	12,	"VLD2LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 },  // Inst #711 = VLD2LNq32a
  { 712,	11,	2,	12,	"VLD2LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 },  // Inst #712 = VLD2LNq32b
  { 713,	8,	2,	12,	"VLD2d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 },  // Inst #713 = VLD2d16
  { 714,	8,	2,	12,	"VLD2d16D", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 },  // Inst #714 = VLD2d16D
  { 715,	8,	2,	12,	"VLD2d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 },  // Inst #715 = VLD2d32
  { 716,	8,	2,	12,	"VLD2d32D", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 },  // Inst #716 = VLD2d32D
  { 717,	8,	2,	11,	"VLD2d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 },  // Inst #717 = VLD2d64
  { 718,	8,	2,	12,	"VLD2d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 },  // Inst #718 = VLD2d8
  { 719,	8,	2,	12,	"VLD2d8D", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 },  // Inst #719 = VLD2d8D
  { 720,	10,	4,	12,	"VLD2q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 },  // Inst #720 = VLD2q16
  { 721,	10,	4,	12,	"VLD2q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 },  // Inst #721 = VLD2q32
  { 722,	10,	4,	12,	"VLD2q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 },  // Inst #722 = VLD2q8
  { 723,	13,	3,	13,	"VLD3LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 },  // Inst #723 = VLD3LNd16
  { 724,	13,	3,	13,	"VLD3LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 },  // Inst #724 = VLD3LNd32
  { 725,	13,	3,	13,	"VLD3LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 },  // Inst #725 = VLD3LNd8
  { 726,	13,	3,	13,	"VLD3LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 },  // Inst #726 = VLD3LNq16a
  { 727,	13,	3,	13,	"VLD3LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 },  // Inst #727 = VLD3LNq16b
  { 728,	13,	3,	13,	"VLD3LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 },  // Inst #728 = VLD3LNq32a
  { 729,	13,	3,	13,	"VLD3LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 },  // Inst #729 = VLD3LNq32b
  { 730,	9,	3,	13,	"VLD3d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 },  // Inst #730 = VLD3d16
  { 731,	9,	3,	13,	"VLD3d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 },  // Inst #731 = VLD3d32
  { 732,	9,	3,	11,	"VLD3d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 },  // Inst #732 = VLD3d64
  { 733,	9,	3,	13,	"VLD3d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 },  // Inst #733 = VLD3d8
  { 734,	10,	4,	13,	"VLD3q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 },  // Inst #734 = VLD3q16a
  { 735,	10,	4,	13,	"VLD3q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 },  // Inst #735 = VLD3q16b
  { 736,	10,	4,	13,	"VLD3q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 },  // Inst #736 = VLD3q32a
  { 737,	10,	4,	13,	"VLD3q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 },  // Inst #737 = VLD3q32b
  { 738,	10,	4,	13,	"VLD3q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 },  // Inst #738 = VLD3q8a
  { 739,	10,	4,	13,	"VLD3q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 },  // Inst #739 = VLD3q8b
  { 740,	15,	4,	14,	"VLD4LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 },  // Inst #740 = VLD4LNd16
  { 741,	15,	4,	14,	"VLD4LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 },  // Inst #741 = VLD4LNd32
  { 742,	15,	4,	14,	"VLD4LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 },  // Inst #742 = VLD4LNd8
  { 743,	15,	4,	14,	"VLD4LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 },  // Inst #743 = VLD4LNq16a
  { 744,	15,	4,	14,	"VLD4LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 },  // Inst #744 = VLD4LNq16b
  { 745,	15,	4,	14,	"VLD4LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 },  // Inst #745 = VLD4LNq32a
  { 746,	15,	4,	14,	"VLD4LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 },  // Inst #746 = VLD4LNq32b
  { 747,	10,	4,	14,	"VLD4d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 },  // Inst #747 = VLD4d16
  { 748,	10,	4,	14,	"VLD4d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 },  // Inst #748 = VLD4d32
  { 749,	10,	4,	11,	"VLD4d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 },  // Inst #749 = VLD4d64
  { 750,	10,	4,	14,	"VLD4d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 },  // Inst #750 = VLD4d8
  { 751,	11,	5,	14,	"VLD4q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 },  // Inst #751 = VLD4q16a
  { 752,	11,	5,	14,	"VLD4q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 },  // Inst #752 = VLD4q16b
  { 753,	11,	5,	14,	"VLD4q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 },  // Inst #753 = VLD4q32a
  { 754,	11,	5,	14,	"VLD4q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 },  // Inst #754 = VLD4q32b
  { 755,	11,	5,	14,	"VLD4q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 },  // Inst #755 = VLD4q8a
  { 756,	11,	5,	14,	"VLD4q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 },  // Inst #756 = VLD4q8b
  { 757,	5,	0,	75,	"VLDMD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo35 },  // Inst #757 = VLDMD
  { 758,	5,	0,	75,	"VLDMS", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo35 },  // Inst #758 = VLDMS
  { 759,	5,	1,	74,	"VLDRD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo96 },  // Inst #759 = VLDRD
  { 760,	5,	1,	75,	"VLDRQ", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 },  // Inst #760 = VLDRQ
  { 761,	5,	1,	73,	"VLDRS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo98 },  // Inst #761 = VLDRS
  { 762,	5,	1,	1,	"VMAXfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #762 = VMAXfd
  { 763,	5,	1,	1,	"VMAXfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 },  // Inst #763 = VMAXfd_sfp
  { 764,	5,	1,	2,	"VMAXfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #764 = VMAXfq
  { 765,	5,	1,	4,	"VMAXsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #765 = VMAXsv16i8
  { 766,	5,	1,	3,	"VMAXsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #766 = VMAXsv2i32
  { 767,	5,	1,	3,	"VMAXsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #767 = VMAXsv4i16
  { 768,	5,	1,	4,	"VMAXsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #768 = VMAXsv4i32
  { 769,	5,	1,	4,	"VMAXsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #769 = VMAXsv8i16
  { 770,	5,	1,	3,	"VMAXsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #770 = VMAXsv8i8
  { 771,	5,	1,	4,	"VMAXuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #771 = VMAXuv16i8
  { 772,	5,	1,	3,	"VMAXuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #772 = VMAXuv2i32
  { 773,	5,	1,	3,	"VMAXuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #773 = VMAXuv4i16
  { 774,	5,	1,	4,	"VMAXuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #774 = VMAXuv4i32
  { 775,	5,	1,	4,	"VMAXuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #775 = VMAXuv8i16
  { 776,	5,	1,	3,	"VMAXuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #776 = VMAXuv8i8
  { 777,	5,	1,	1,	"VMINfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #777 = VMINfd
  { 778,	5,	1,	1,	"VMINfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 },  // Inst #778 = VMINfd_sfp
  { 779,	5,	1,	2,	"VMINfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #779 = VMINfq
  { 780,	5,	1,	4,	"VMINsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #780 = VMINsv16i8
  { 781,	5,	1,	3,	"VMINsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #781 = VMINsv2i32
  { 782,	5,	1,	3,	"VMINsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #782 = VMINsv4i16
  { 783,	5,	1,	4,	"VMINsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #783 = VMINsv4i32
  { 784,	5,	1,	4,	"VMINsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #784 = VMINsv8i16
  { 785,	5,	1,	3,	"VMINsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #785 = VMINsv8i8
  { 786,	5,	1,	4,	"VMINuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #786 = VMINuv16i8
  { 787,	5,	1,	3,	"VMINuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #787 = VMINuv2i32
  { 788,	5,	1,	3,	"VMINuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #788 = VMINuv4i16
  { 789,	5,	1,	4,	"VMINuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #789 = VMINuv4i32
  { 790,	5,	1,	4,	"VMINuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #790 = VMINuv8i16
  { 791,	5,	1,	3,	"VMINuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #791 = VMINuv8i8
  { 792,	6,	1,	77,	"VMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #792 = VMLAD
  { 793,	7,	1,	19,	"VMLALslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 },  // Inst #793 = VMLALslsv2i32
  { 794,	7,	1,	17,	"VMLALslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 },  // Inst #794 = VMLALslsv4i16
  { 795,	7,	1,	19,	"VMLALsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 },  // Inst #795 = VMLALsluv2i32
  { 796,	7,	1,	17,	"VMLALsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 },  // Inst #796 = VMLALsluv4i16
  { 797,	6,	1,	17,	"VMLALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #797 = VMLALsv2i64
  { 798,	6,	1,	17,	"VMLALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #798 = VMLALsv4i32
  { 799,	6,	1,	17,	"VMLALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #799 = VMLALsv8i16
  { 800,	6,	1,	17,	"VMLALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #800 = VMLALuv2i64
  { 801,	6,	1,	17,	"VMLALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #801 = VMLALuv4i32
  { 802,	6,	1,	17,	"VMLALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #802 = VMLALuv8i16
  { 803,	6,	1,	76,	"VMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 },  // Inst #803 = VMLAS
  { 804,	6,	1,	15,	"VMLAfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #804 = VMLAfd
  { 805,	6,	1,	16,	"VMLAfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #805 = VMLAfq
  { 806,	7,	1,	15,	"VMLAslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 },  // Inst #806 = VMLAslfd
  { 807,	7,	1,	16,	"VMLAslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 },  // Inst #807 = VMLAslfq
  { 808,	7,	1,	19,	"VMLAslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 },  // Inst #808 = VMLAslv2i32
  { 809,	7,	1,	17,	"VMLAslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 },  // Inst #809 = VMLAslv4i16
  { 810,	7,	1,	20,	"VMLAslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 },  // Inst #810 = VMLAslv4i32
  { 811,	7,	1,	18,	"VMLAslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 },  // Inst #811 = VMLAslv8i16
  { 812,	6,	1,	18,	"VMLAv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #812 = VMLAv16i8
  { 813,	6,	1,	19,	"VMLAv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #813 = VMLAv2i32
  { 814,	6,	1,	17,	"VMLAv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #814 = VMLAv4i16
  { 815,	6,	1,	20,	"VMLAv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #815 = VMLAv4i32
  { 816,	6,	1,	18,	"VMLAv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #816 = VMLAv8i16
  { 817,	6,	1,	17,	"VMLAv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #817 = VMLAv8i8
  { 818,	6,	1,	77,	"VMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #818 = VMLSD
  { 819,	7,	1,	19,	"VMLSLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 },  // Inst #819 = VMLSLslsv2i32
  { 820,	7,	1,	17,	"VMLSLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 },  // Inst #820 = VMLSLslsv4i16
  { 821,	7,	1,	19,	"VMLSLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 },  // Inst #821 = VMLSLsluv2i32
  { 822,	7,	1,	17,	"VMLSLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 },  // Inst #822 = VMLSLsluv4i16
  { 823,	6,	1,	17,	"VMLSLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #823 = VMLSLsv2i64
  { 824,	6,	1,	17,	"VMLSLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #824 = VMLSLsv4i32
  { 825,	6,	1,	17,	"VMLSLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #825 = VMLSLsv8i16
  { 826,	6,	1,	17,	"VMLSLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #826 = VMLSLuv2i64
  { 827,	6,	1,	17,	"VMLSLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #827 = VMLSLuv4i32
  { 828,	6,	1,	17,	"VMLSLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #828 = VMLSLuv8i16
  { 829,	6,	1,	76,	"VMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 },  // Inst #829 = VMLSS
  { 830,	6,	1,	15,	"VMLSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #830 = VMLSfd
  { 831,	6,	1,	16,	"VMLSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #831 = VMLSfq
  { 832,	7,	1,	15,	"VMLSslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 },  // Inst #832 = VMLSslfd
  { 833,	7,	1,	16,	"VMLSslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 },  // Inst #833 = VMLSslfq
  { 834,	7,	1,	19,	"VMLSslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 },  // Inst #834 = VMLSslv2i32
  { 835,	7,	1,	17,	"VMLSslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 },  // Inst #835 = VMLSslv4i16
  { 836,	7,	1,	20,	"VMLSslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 },  // Inst #836 = VMLSslv4i32
  { 837,	7,	1,	18,	"VMLSslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 },  // Inst #837 = VMLSslv8i16
  { 838,	6,	1,	18,	"VMLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #838 = VMLSv16i8
  { 839,	6,	1,	19,	"VMLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #839 = VMLSv2i32
  { 840,	6,	1,	17,	"VMLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #840 = VMLSv4i16
  { 841,	6,	1,	20,	"VMLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #841 = VMLSv4i32
  { 842,	6,	1,	18,	"VMLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 },  // Inst #842 = VMLSv8i16
  { 843,	6,	1,	17,	"VMLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #843 = VMLSv8i8
  { 844,	4,	1,	87,	"VMOVD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #844 = VMOVD
  { 845,	5,	1,	23,	"VMOVDRR", 0|(1<<TID::Predicable), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo106 },  // Inst #845 = VMOVDRR
  { 846,	5,	1,	87,	"VMOVDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo107 },  // Inst #846 = VMOVDcc
  { 847,	4,	1,	21,	"VMOVDneon", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #847 = VMOVDneon
  { 848,	4,	1,	38,	"VMOVLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 },  // Inst #848 = VMOVLsv2i64
  { 849,	4,	1,	38,	"VMOVLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 },  // Inst #849 = VMOVLsv4i32
  { 850,	4,	1,	38,	"VMOVLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 },  // Inst #850 = VMOVLsv8i16
  { 851,	4,	1,	38,	"VMOVLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 },  // Inst #851 = VMOVLuv2i64
  { 852,	4,	1,	38,	"VMOVLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 },  // Inst #852 = VMOVLuv4i32
  { 853,	4,	1,	38,	"VMOVLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 },  // Inst #853 = VMOVLuv8i16
  { 854,	4,	1,	21,	"VMOVNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 },  // Inst #854 = VMOVNv2i32
  { 855,	4,	1,	21,	"VMOVNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 },  // Inst #855 = VMOVNv4i16
  { 856,	4,	1,	21,	"VMOVNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 },  // Inst #856 = VMOVNv8i8
  { 857,	4,	1,	21,	"VMOVQ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #857 = VMOVQ
  { 858,	5,	2,	22,	"VMOVRRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo110 },  // Inst #858 = VMOVRRD
  { 859,	6,	2,	22,	"VMOVRRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo111 },  // Inst #859 = VMOVRRS
  { 860,	4,	1,	28,	"VMOVRS", 0|(1<<TID::Predicable), 0|(3<<4)|(16<<9)|(1<<17), NULL, NULL, NULL, OperandInfo112 },  // Inst #860 = VMOVRS
  { 861,	4,	1,	86,	"VMOVS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 },  // Inst #861 = VMOVS
  { 862,	4,	1,	24,	"VMOVSR", 0|(1<<TID::Predicable), 0|(3<<4)|(18<<9)|(1<<17), NULL, NULL, NULL, OperandInfo113 },  // Inst #862 = VMOVSR
  { 863,	6,	2,	23,	"VMOVSRR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo114 },  // Inst #863 = VMOVSRR
  { 864,	5,	1,	86,	"VMOVScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo115 },  // Inst #864 = VMOVScc
  { 865,	4,	1,	26,	"VMOVv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 },  // Inst #865 = VMOVv16i8
  { 866,	4,	1,	26,	"VMOVv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 },  // Inst #866 = VMOVv1i64
  { 867,	4,	1,	26,	"VMOVv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 },  // Inst #867 = VMOVv2i32
  { 868,	4,	1,	26,	"VMOVv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 },  // Inst #868 = VMOVv2i64
  { 869,	4,	1,	26,	"VMOVv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 },  // Inst #869 = VMOVv4i16
  { 870,	4,	1,	26,	"VMOVv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 },  // Inst #870 = VMOVv4i32
  { 871,	4,	1,	26,	"VMOVv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 },  // Inst #871 = VMOVv8i16
  { 872,	4,	1,	26,	"VMOVv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 },  // Inst #872 = VMOVv8i8
  { 873,	3,	1,	82,	"VMRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, NULL, NULL, OperandInfo21 },  // Inst #873 = VMRS
  { 874,	3,	0,	82,	"VMSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(22<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo21 },  // Inst #874 = VMSR
  { 875,	5,	1,	79,	"VMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #875 = VMULD
  { 876,	5,	1,	29,	"VMULLp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #876 = VMULLp
  { 877,	6,	1,	29,	"VMULLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 },  // Inst #877 = VMULLslsv2i32
  { 878,	6,	1,	29,	"VMULLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 },  // Inst #878 = VMULLslsv4i16
  { 879,	6,	1,	29,	"VMULLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 },  // Inst #879 = VMULLsluv2i32
  { 880,	6,	1,	29,	"VMULLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 },  // Inst #880 = VMULLsluv4i16
  { 881,	5,	1,	29,	"VMULLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #881 = VMULLsv2i64
  { 882,	5,	1,	29,	"VMULLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #882 = VMULLsv4i32
  { 883,	5,	1,	29,	"VMULLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #883 = VMULLsv8i16
  { 884,	5,	1,	29,	"VMULLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #884 = VMULLuv2i64
  { 885,	5,	1,	29,	"VMULLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #885 = VMULLuv4i32
  { 886,	5,	1,	29,	"VMULLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #886 = VMULLuv8i16
  { 887,	5,	1,	78,	"VMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 },  // Inst #887 = VMULS
  { 888,	5,	1,	1,	"VMULfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #888 = VMULfd
  { 889,	5,	1,	1,	"VMULfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 },  // Inst #889 = VMULfd_sfp
  { 890,	5,	1,	2,	"VMULfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #890 = VMULfq
  { 891,	5,	1,	29,	"VMULpd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #891 = VMULpd
  { 892,	5,	1,	30,	"VMULpq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #892 = VMULpq
  { 893,	6,	1,	1,	"VMULslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 },  // Inst #893 = VMULslfd
  { 894,	6,	1,	2,	"VMULslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 },  // Inst #894 = VMULslfq
  { 895,	6,	1,	31,	"VMULslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 },  // Inst #895 = VMULslv2i32
  { 896,	6,	1,	29,	"VMULslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 },  // Inst #896 = VMULslv4i16
  { 897,	6,	1,	32,	"VMULslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 },  // Inst #897 = VMULslv4i32
  { 898,	6,	1,	30,	"VMULslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 },  // Inst #898 = VMULslv8i16
  { 899,	5,	1,	30,	"VMULv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #899 = VMULv16i8
  { 900,	5,	1,	31,	"VMULv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #900 = VMULv2i32
  { 901,	5,	1,	29,	"VMULv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #901 = VMULv4i16
  { 902,	5,	1,	32,	"VMULv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #902 = VMULv4i32
  { 903,	5,	1,	30,	"VMULv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #903 = VMULv8i16
  { 904,	5,	1,	29,	"VMULv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #904 = VMULv8i8
  { 905,	4,	1,	44,	"VMVNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #905 = VMVNd
  { 906,	4,	1,	44,	"VMVNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #906 = VMVNq
  { 907,	4,	1,	87,	"VNEGD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #907 = VNEGD
  { 908,	5,	1,	87,	"VNEGDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo107 },  // Inst #908 = VNEGDcc
  { 909,	4,	1,	86,	"VNEGS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 },  // Inst #909 = VNEGS
  { 910,	5,	1,	86,	"VNEGScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo115 },  // Inst #910 = VNEGScc
  { 911,	4,	1,	58,	"VNEGf32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #911 = VNEGf32q
  { 912,	4,	1,	57,	"VNEGfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #912 = VNEGfd
  { 913,	4,	1,	57,	"VNEGfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 },  // Inst #913 = VNEGfd_sfp
  { 914,	4,	1,	44,	"VNEGs16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #914 = VNEGs16d
  { 915,	4,	1,	44,	"VNEGs16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #915 = VNEGs16q
  { 916,	4,	1,	44,	"VNEGs32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #916 = VNEGs32d
  { 917,	4,	1,	44,	"VNEGs32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #917 = VNEGs32q
  { 918,	4,	1,	44,	"VNEGs8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #918 = VNEGs8d
  { 919,	4,	1,	44,	"VNEGs8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #919 = VNEGs8q
  { 920,	6,	1,	77,	"VNMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #920 = VNMLAD
  { 921,	6,	1,	76,	"VNMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 },  // Inst #921 = VNMLAS
  { 922,	6,	1,	77,	"VNMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #922 = VNMLSD
  { 923,	6,	1,	76,	"VNMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 },  // Inst #923 = VNMLSS
  { 924,	5,	1,	79,	"VNMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #924 = VNMULD
  { 925,	5,	1,	78,	"VNMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 },  // Inst #925 = VNMULS
  { 926,	5,	1,	5,	"VORNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #926 = VORNd
  { 927,	5,	1,	6,	"VORNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #927 = VORNq
  { 928,	5,	1,	5,	"VORRd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #928 = VORRd
  { 929,	5,	1,	6,	"VORRq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #929 = VORRq
  { 930,	5,	1,	34,	"VPADALsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 },  // Inst #930 = VPADALsv16i8
  { 931,	5,	1,	33,	"VPADALsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 },  // Inst #931 = VPADALsv2i32
  { 932,	5,	1,	33,	"VPADALsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 },  // Inst #932 = VPADALsv4i16
  { 933,	5,	1,	34,	"VPADALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 },  // Inst #933 = VPADALsv4i32
  { 934,	5,	1,	34,	"VPADALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 },  // Inst #934 = VPADALsv8i16
  { 935,	5,	1,	33,	"VPADALsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 },  // Inst #935 = VPADALsv8i8
  { 936,	5,	1,	34,	"VPADALuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 },  // Inst #936 = VPADALuv16i8
  { 937,	5,	1,	33,	"VPADALuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 },  // Inst #937 = VPADALuv2i32
  { 938,	5,	1,	33,	"VPADALuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 },  // Inst #938 = VPADALuv4i16
  { 939,	5,	1,	34,	"VPADALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 },  // Inst #939 = VPADALuv4i32
  { 940,	5,	1,	34,	"VPADALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 },  // Inst #940 = VPADALuv8i16
  { 941,	5,	1,	33,	"VPADALuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 },  // Inst #941 = VPADALuv8i8
  { 942,	4,	1,	44,	"VPADDLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #942 = VPADDLsv16i8
  { 943,	4,	1,	44,	"VPADDLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #943 = VPADDLsv2i32
  { 944,	4,	1,	44,	"VPADDLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #944 = VPADDLsv4i16
  { 945,	4,	1,	44,	"VPADDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #945 = VPADDLsv4i32
  { 946,	4,	1,	44,	"VPADDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #946 = VPADDLsv8i16
  { 947,	4,	1,	44,	"VPADDLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #947 = VPADDLsv8i8
  { 948,	4,	1,	44,	"VPADDLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #948 = VPADDLuv16i8
  { 949,	4,	1,	44,	"VPADDLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #949 = VPADDLuv2i32
  { 950,	4,	1,	44,	"VPADDLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #950 = VPADDLuv4i16
  { 951,	4,	1,	44,	"VPADDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #951 = VPADDLuv4i32
  { 952,	4,	1,	44,	"VPADDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #952 = VPADDLuv8i16
  { 953,	4,	1,	44,	"VPADDLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #953 = VPADDLuv8i8
  { 954,	5,	1,	1,	"VPADDf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #954 = VPADDf
  { 955,	5,	1,	5,	"VPADDi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #955 = VPADDi16
  { 956,	5,	1,	5,	"VPADDi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #956 = VPADDi32
  { 957,	5,	1,	5,	"VPADDi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #957 = VPADDi8
  { 958,	5,	1,	3,	"VPMAXf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #958 = VPMAXf
  { 959,	5,	1,	3,	"VPMAXs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #959 = VPMAXs16
  { 960,	5,	1,	3,	"VPMAXs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #960 = VPMAXs32
  { 961,	5,	1,	3,	"VPMAXs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #961 = VPMAXs8
  { 962,	5,	1,	3,	"VPMAXu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #962 = VPMAXu16
  { 963,	5,	1,	3,	"VPMAXu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #963 = VPMAXu32
  { 964,	5,	1,	3,	"VPMAXu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #964 = VPMAXu8
  { 965,	5,	1,	3,	"VPMINf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #965 = VPMINf
  { 966,	5,	1,	3,	"VPMINs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #966 = VPMINs16
  { 967,	5,	1,	3,	"VPMINs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #967 = VPMINs32
  { 968,	5,	1,	3,	"VPMINs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #968 = VPMINs8
  { 969,	5,	1,	3,	"VPMINu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #969 = VPMINu16
  { 970,	5,	1,	3,	"VPMINu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #970 = VPMINu32
  { 971,	5,	1,	3,	"VPMINu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #971 = VPMINu8
  { 972,	4,	1,	39,	"VQABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #972 = VQABSv16i8
  { 973,	4,	1,	38,	"VQABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #973 = VQABSv2i32
  { 974,	4,	1,	38,	"VQABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #974 = VQABSv4i16
  { 975,	4,	1,	39,	"VQABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #975 = VQABSv4i32
  { 976,	4,	1,	39,	"VQABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #976 = VQABSv8i16
  { 977,	4,	1,	38,	"VQABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #977 = VQABSv8i8
  { 978,	5,	1,	4,	"VQADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #978 = VQADDsv16i8
  { 979,	5,	1,	3,	"VQADDsv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #979 = VQADDsv1i64
  { 980,	5,	1,	3,	"VQADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #980 = VQADDsv2i32
  { 981,	5,	1,	4,	"VQADDsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #981 = VQADDsv2i64
  { 982,	5,	1,	3,	"VQADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #982 = VQADDsv4i16
  { 983,	5,	1,	4,	"VQADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #983 = VQADDsv4i32
  { 984,	5,	1,	4,	"VQADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #984 = VQADDsv8i16
  { 985,	5,	1,	3,	"VQADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #985 = VQADDsv8i8
  { 986,	5,	1,	4,	"VQADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #986 = VQADDuv16i8
  { 987,	5,	1,	3,	"VQADDuv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #987 = VQADDuv1i64
  { 988,	5,	1,	3,	"VQADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #988 = VQADDuv2i32
  { 989,	5,	1,	4,	"VQADDuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #989 = VQADDuv2i64
  { 990,	5,	1,	3,	"VQADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #990 = VQADDuv4i16
  { 991,	5,	1,	4,	"VQADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #991 = VQADDuv4i32
  { 992,	5,	1,	4,	"VQADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #992 = VQADDuv8i16
  { 993,	5,	1,	3,	"VQADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #993 = VQADDuv8i8
  { 994,	7,	1,	19,	"VQDMLALslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 },  // Inst #994 = VQDMLALslv2i32
  { 995,	7,	1,	17,	"VQDMLALslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 },  // Inst #995 = VQDMLALslv4i16
  { 996,	6,	1,	17,	"VQDMLALv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #996 = VQDMLALv2i64
  { 997,	6,	1,	17,	"VQDMLALv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #997 = VQDMLALv4i32
  { 998,	7,	1,	19,	"VQDMLSLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 },  // Inst #998 = VQDMLSLslv2i32
  { 999,	7,	1,	17,	"VQDMLSLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 },  // Inst #999 = VQDMLSLslv4i16
  { 1000,	6,	1,	17,	"VQDMLSLv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #1000 = VQDMLSLv2i64
  { 1001,	6,	1,	17,	"VQDMLSLv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 },  // Inst #1001 = VQDMLSLv4i32
  { 1002,	6,	1,	31,	"VQDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 },  // Inst #1002 = VQDMULHslv2i32
  { 1003,	6,	1,	29,	"VQDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 },  // Inst #1003 = VQDMULHslv4i16
  { 1004,	6,	1,	32,	"VQDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 },  // Inst #1004 = VQDMULHslv4i32
  { 1005,	6,	1,	30,	"VQDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 },  // Inst #1005 = VQDMULHslv8i16
  { 1006,	5,	1,	31,	"VQDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1006 = VQDMULHv2i32
  { 1007,	5,	1,	29,	"VQDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1007 = VQDMULHv4i16
  { 1008,	5,	1,	32,	"VQDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1008 = VQDMULHv4i32
  { 1009,	5,	1,	30,	"VQDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1009 = VQDMULHv8i16
  { 1010,	6,	1,	29,	"VQDMULLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 },  // Inst #1010 = VQDMULLslv2i32
  { 1011,	6,	1,	29,	"VQDMULLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 },  // Inst #1011 = VQDMULLslv4i16
  { 1012,	5,	1,	29,	"VQDMULLv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #1012 = VQDMULLv2i64
  { 1013,	5,	1,	29,	"VQDMULLv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #1013 = VQDMULLv4i32
  { 1014,	4,	1,	38,	"VQMOVNsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 },  // Inst #1014 = VQMOVNsuv2i32
  { 1015,	4,	1,	38,	"VQMOVNsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 },  // Inst #1015 = VQMOVNsuv4i16
  { 1016,	4,	1,	38,	"VQMOVNsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 },  // Inst #1016 = VQMOVNsuv8i8
  { 1017,	4,	1,	38,	"VQMOVNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 },  // Inst #1017 = VQMOVNsv2i32
  { 1018,	4,	1,	38,	"VQMOVNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 },  // Inst #1018 = VQMOVNsv4i16
  { 1019,	4,	1,	38,	"VQMOVNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 },  // Inst #1019 = VQMOVNsv8i8
  { 1020,	4,	1,	38,	"VQMOVNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 },  // Inst #1020 = VQMOVNuv2i32
  { 1021,	4,	1,	38,	"VQMOVNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 },  // Inst #1021 = VQMOVNuv4i16
  { 1022,	4,	1,	38,	"VQMOVNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 },  // Inst #1022 = VQMOVNuv8i8
  { 1023,	4,	1,	39,	"VQNEGv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1023 = VQNEGv16i8
  { 1024,	4,	1,	38,	"VQNEGv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1024 = VQNEGv2i32
  { 1025,	4,	1,	38,	"VQNEGv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1025 = VQNEGv4i16
  { 1026,	4,	1,	39,	"VQNEGv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1026 = VQNEGv4i32
  { 1027,	4,	1,	39,	"VQNEGv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1027 = VQNEGv8i16
  { 1028,	4,	1,	38,	"VQNEGv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1028 = VQNEGv8i8
  { 1029,	6,	1,	31,	"VQRDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 },  // Inst #1029 = VQRDMULHslv2i32
  { 1030,	6,	1,	29,	"VQRDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 },  // Inst #1030 = VQRDMULHslv4i16
  { 1031,	6,	1,	32,	"VQRDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 },  // Inst #1031 = VQRDMULHslv4i32
  { 1032,	6,	1,	30,	"VQRDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 },  // Inst #1032 = VQRDMULHslv8i16
  { 1033,	5,	1,	31,	"VQRDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1033 = VQRDMULHv2i32
  { 1034,	5,	1,	29,	"VQRDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1034 = VQRDMULHv4i16
  { 1035,	5,	1,	32,	"VQRDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1035 = VQRDMULHv4i32
  { 1036,	5,	1,	30,	"VQRDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1036 = VQRDMULHv8i16
  { 1037,	5,	1,	43,	"VQRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1037 = VQRSHLsv16i8
  { 1038,	5,	1,	42,	"VQRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1038 = VQRSHLsv1i64
  { 1039,	5,	1,	42,	"VQRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1039 = VQRSHLsv2i32
  { 1040,	5,	1,	43,	"VQRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1040 = VQRSHLsv2i64
  { 1041,	5,	1,	42,	"VQRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1041 = VQRSHLsv4i16
  { 1042,	5,	1,	43,	"VQRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1042 = VQRSHLsv4i32
  { 1043,	5,	1,	43,	"VQRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1043 = VQRSHLsv8i16
  { 1044,	5,	1,	42,	"VQRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1044 = VQRSHLsv8i8
  { 1045,	5,	1,	43,	"VQRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1045 = VQRSHLuv16i8
  { 1046,	5,	1,	42,	"VQRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1046 = VQRSHLuv1i64
  { 1047,	5,	1,	42,	"VQRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1047 = VQRSHLuv2i32
  { 1048,	5,	1,	43,	"VQRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1048 = VQRSHLuv2i64
  { 1049,	5,	1,	42,	"VQRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1049 = VQRSHLuv4i16
  { 1050,	5,	1,	43,	"VQRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1050 = VQRSHLuv4i32
  { 1051,	5,	1,	43,	"VQRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1051 = VQRSHLuv8i16
  { 1052,	5,	1,	42,	"VQRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1052 = VQRSHLuv8i8
  { 1053,	5,	1,	42,	"VQRSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1053 = VQRSHRNsv2i32
  { 1054,	5,	1,	42,	"VQRSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1054 = VQRSHRNsv4i16
  { 1055,	5,	1,	42,	"VQRSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1055 = VQRSHRNsv8i8
  { 1056,	5,	1,	42,	"VQRSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1056 = VQRSHRNuv2i32
  { 1057,	5,	1,	42,	"VQRSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1057 = VQRSHRNuv4i16
  { 1058,	5,	1,	42,	"VQRSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1058 = VQRSHRNuv8i8
  { 1059,	5,	1,	42,	"VQRSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1059 = VQRSHRUNv2i32
  { 1060,	5,	1,	42,	"VQRSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1060 = VQRSHRUNv4i16
  { 1061,	5,	1,	42,	"VQRSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1061 = VQRSHRUNv8i8
  { 1062,	5,	1,	42,	"VQSHLsiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1062 = VQSHLsiv16i8
  { 1063,	5,	1,	42,	"VQSHLsiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1063 = VQSHLsiv1i64
  { 1064,	5,	1,	42,	"VQSHLsiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1064 = VQSHLsiv2i32
  { 1065,	5,	1,	42,	"VQSHLsiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1065 = VQSHLsiv2i64
  { 1066,	5,	1,	42,	"VQSHLsiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1066 = VQSHLsiv4i16
  { 1067,	5,	1,	42,	"VQSHLsiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1067 = VQSHLsiv4i32
  { 1068,	5,	1,	42,	"VQSHLsiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1068 = VQSHLsiv8i16
  { 1069,	5,	1,	42,	"VQSHLsiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1069 = VQSHLsiv8i8
  { 1070,	5,	1,	42,	"VQSHLsuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1070 = VQSHLsuv16i8
  { 1071,	5,	1,	42,	"VQSHLsuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1071 = VQSHLsuv1i64
  { 1072,	5,	1,	42,	"VQSHLsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1072 = VQSHLsuv2i32
  { 1073,	5,	1,	42,	"VQSHLsuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1073 = VQSHLsuv2i64
  { 1074,	5,	1,	42,	"VQSHLsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1074 = VQSHLsuv4i16
  { 1075,	5,	1,	42,	"VQSHLsuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1075 = VQSHLsuv4i32
  { 1076,	5,	1,	42,	"VQSHLsuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1076 = VQSHLsuv8i16
  { 1077,	5,	1,	42,	"VQSHLsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1077 = VQSHLsuv8i8
  { 1078,	5,	1,	43,	"VQSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1078 = VQSHLsv16i8
  { 1079,	5,	1,	42,	"VQSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1079 = VQSHLsv1i64
  { 1080,	5,	1,	42,	"VQSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1080 = VQSHLsv2i32
  { 1081,	5,	1,	43,	"VQSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1081 = VQSHLsv2i64
  { 1082,	5,	1,	42,	"VQSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1082 = VQSHLsv4i16
  { 1083,	5,	1,	43,	"VQSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1083 = VQSHLsv4i32
  { 1084,	5,	1,	43,	"VQSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1084 = VQSHLsv8i16
  { 1085,	5,	1,	42,	"VQSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1085 = VQSHLsv8i8
  { 1086,	5,	1,	42,	"VQSHLuiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1086 = VQSHLuiv16i8
  { 1087,	5,	1,	42,	"VQSHLuiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1087 = VQSHLuiv1i64
  { 1088,	5,	1,	42,	"VQSHLuiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1088 = VQSHLuiv2i32
  { 1089,	5,	1,	42,	"VQSHLuiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1089 = VQSHLuiv2i64
  { 1090,	5,	1,	42,	"VQSHLuiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1090 = VQSHLuiv4i16
  { 1091,	5,	1,	42,	"VQSHLuiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1091 = VQSHLuiv4i32
  { 1092,	5,	1,	42,	"VQSHLuiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1092 = VQSHLuiv8i16
  { 1093,	5,	1,	42,	"VQSHLuiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1093 = VQSHLuiv8i8
  { 1094,	5,	1,	43,	"VQSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1094 = VQSHLuv16i8
  { 1095,	5,	1,	42,	"VQSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1095 = VQSHLuv1i64
  { 1096,	5,	1,	42,	"VQSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1096 = VQSHLuv2i32
  { 1097,	5,	1,	43,	"VQSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1097 = VQSHLuv2i64
  { 1098,	5,	1,	42,	"VQSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1098 = VQSHLuv4i16
  { 1099,	5,	1,	43,	"VQSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1099 = VQSHLuv4i32
  { 1100,	5,	1,	43,	"VQSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1100 = VQSHLuv8i16
  { 1101,	5,	1,	42,	"VQSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1101 = VQSHLuv8i8
  { 1102,	5,	1,	42,	"VQSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1102 = VQSHRNsv2i32
  { 1103,	5,	1,	42,	"VQSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1103 = VQSHRNsv4i16
  { 1104,	5,	1,	42,	"VQSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1104 = VQSHRNsv8i8
  { 1105,	5,	1,	42,	"VQSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1105 = VQSHRNuv2i32
  { 1106,	5,	1,	42,	"VQSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1106 = VQSHRNuv4i16
  { 1107,	5,	1,	42,	"VQSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1107 = VQSHRNuv8i8
  { 1108,	5,	1,	42,	"VQSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1108 = VQSHRUNv2i32
  { 1109,	5,	1,	42,	"VQSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1109 = VQSHRUNv4i16
  { 1110,	5,	1,	42,	"VQSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1110 = VQSHRUNv8i8
  { 1111,	5,	1,	4,	"VQSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1111 = VQSUBsv16i8
  { 1112,	5,	1,	3,	"VQSUBsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1112 = VQSUBsv1i64
  { 1113,	5,	1,	3,	"VQSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1113 = VQSUBsv2i32
  { 1114,	5,	1,	4,	"VQSUBsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1114 = VQSUBsv2i64
  { 1115,	5,	1,	3,	"VQSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1115 = VQSUBsv4i16
  { 1116,	5,	1,	4,	"VQSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1116 = VQSUBsv4i32
  { 1117,	5,	1,	4,	"VQSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1117 = VQSUBsv8i16
  { 1118,	5,	1,	3,	"VQSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1118 = VQSUBsv8i8
  { 1119,	5,	1,	4,	"VQSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1119 = VQSUBuv16i8
  { 1120,	5,	1,	3,	"VQSUBuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1120 = VQSUBuv1i64
  { 1121,	5,	1,	3,	"VQSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1121 = VQSUBuv2i32
  { 1122,	5,	1,	4,	"VQSUBuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1122 = VQSUBuv2i64
  { 1123,	5,	1,	3,	"VQSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1123 = VQSUBuv4i16
  { 1124,	5,	1,	4,	"VQSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1124 = VQSUBuv4i32
  { 1125,	5,	1,	4,	"VQSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1125 = VQSUBuv8i16
  { 1126,	5,	1,	3,	"VQSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1126 = VQSUBuv8i8
  { 1127,	5,	1,	3,	"VRADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 },  // Inst #1127 = VRADDHNv2i32
  { 1128,	5,	1,	3,	"VRADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 },  // Inst #1128 = VRADDHNv4i16
  { 1129,	5,	1,	3,	"VRADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 },  // Inst #1129 = VRADDHNv8i8
  { 1130,	4,	1,	57,	"VRECPEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1130 = VRECPEd
  { 1131,	4,	1,	57,	"VRECPEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1131 = VRECPEfd
  { 1132,	4,	1,	58,	"VRECPEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1132 = VRECPEfq
  { 1133,	4,	1,	58,	"VRECPEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1133 = VRECPEq
  { 1134,	5,	1,	40,	"VRECPSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1134 = VRECPSfd
  { 1135,	5,	1,	41,	"VRECPSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1135 = VRECPSfq
  { 1136,	4,	1,	21,	"VREV16d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1136 = VREV16d8
  { 1137,	4,	1,	21,	"VREV16q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1137 = VREV16q8
  { 1138,	4,	1,	21,	"VREV32d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1138 = VREV32d16
  { 1139,	4,	1,	21,	"VREV32d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1139 = VREV32d8
  { 1140,	4,	1,	21,	"VREV32q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1140 = VREV32q16
  { 1141,	4,	1,	21,	"VREV32q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1141 = VREV32q8
  { 1142,	4,	1,	21,	"VREV64d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1142 = VREV64d16
  { 1143,	4,	1,	21,	"VREV64d32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1143 = VREV64d32
  { 1144,	4,	1,	21,	"VREV64d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1144 = VREV64d8
  { 1145,	4,	1,	21,	"VREV64df", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1145 = VREV64df
  { 1146,	4,	1,	21,	"VREV64q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1146 = VREV64q16
  { 1147,	4,	1,	21,	"VREV64q32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1147 = VREV64q32
  { 1148,	4,	1,	21,	"VREV64q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1148 = VREV64q8
  { 1149,	4,	1,	21,	"VREV64qf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1149 = VREV64qf
  { 1150,	5,	1,	4,	"VRHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1150 = VRHADDsv16i8
  { 1151,	5,	1,	3,	"VRHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1151 = VRHADDsv2i32
  { 1152,	5,	1,	3,	"VRHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1152 = VRHADDsv4i16
  { 1153,	5,	1,	4,	"VRHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1153 = VRHADDsv4i32
  { 1154,	5,	1,	4,	"VRHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1154 = VRHADDsv8i16
  { 1155,	5,	1,	3,	"VRHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1155 = VRHADDsv8i8
  { 1156,	5,	1,	4,	"VRHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1156 = VRHADDuv16i8
  { 1157,	5,	1,	3,	"VRHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1157 = VRHADDuv2i32
  { 1158,	5,	1,	3,	"VRHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1158 = VRHADDuv4i16
  { 1159,	5,	1,	4,	"VRHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1159 = VRHADDuv4i32
  { 1160,	5,	1,	4,	"VRHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1160 = VRHADDuv8i16
  { 1161,	5,	1,	3,	"VRHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1161 = VRHADDuv8i8
  { 1162,	5,	1,	43,	"VRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1162 = VRSHLsv16i8
  { 1163,	5,	1,	42,	"VRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1163 = VRSHLsv1i64
  { 1164,	5,	1,	42,	"VRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1164 = VRSHLsv2i32
  { 1165,	5,	1,	43,	"VRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1165 = VRSHLsv2i64
  { 1166,	5,	1,	42,	"VRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1166 = VRSHLsv4i16
  { 1167,	5,	1,	43,	"VRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1167 = VRSHLsv4i32
  { 1168,	5,	1,	43,	"VRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1168 = VRSHLsv8i16
  { 1169,	5,	1,	42,	"VRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1169 = VRSHLsv8i8
  { 1170,	5,	1,	43,	"VRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1170 = VRSHLuv16i8
  { 1171,	5,	1,	42,	"VRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1171 = VRSHLuv1i64
  { 1172,	5,	1,	42,	"VRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1172 = VRSHLuv2i32
  { 1173,	5,	1,	43,	"VRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1173 = VRSHLuv2i64
  { 1174,	5,	1,	42,	"VRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1174 = VRSHLuv4i16
  { 1175,	5,	1,	43,	"VRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1175 = VRSHLuv4i32
  { 1176,	5,	1,	43,	"VRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1176 = VRSHLuv8i16
  { 1177,	5,	1,	42,	"VRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1177 = VRSHLuv8i8
  { 1178,	5,	1,	42,	"VRSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1178 = VRSHRNv2i32
  { 1179,	5,	1,	42,	"VRSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1179 = VRSHRNv4i16
  { 1180,	5,	1,	42,	"VRSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1180 = VRSHRNv8i8
  { 1181,	5,	1,	42,	"VRSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1181 = VRSHRsv16i8
  { 1182,	5,	1,	42,	"VRSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1182 = VRSHRsv1i64
  { 1183,	5,	1,	42,	"VRSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1183 = VRSHRsv2i32
  { 1184,	5,	1,	42,	"VRSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1184 = VRSHRsv2i64
  { 1185,	5,	1,	42,	"VRSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1185 = VRSHRsv4i16
  { 1186,	5,	1,	42,	"VRSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1186 = VRSHRsv4i32
  { 1187,	5,	1,	42,	"VRSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1187 = VRSHRsv8i16
  { 1188,	5,	1,	42,	"VRSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1188 = VRSHRsv8i8
  { 1189,	5,	1,	42,	"VRSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1189 = VRSHRuv16i8
  { 1190,	5,	1,	42,	"VRSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1190 = VRSHRuv1i64
  { 1191,	5,	1,	42,	"VRSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1191 = VRSHRuv2i32
  { 1192,	5,	1,	42,	"VRSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1192 = VRSHRuv2i64
  { 1193,	5,	1,	42,	"VRSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1193 = VRSHRuv4i16
  { 1194,	5,	1,	42,	"VRSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1194 = VRSHRuv4i32
  { 1195,	5,	1,	42,	"VRSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1195 = VRSHRuv8i16
  { 1196,	5,	1,	42,	"VRSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1196 = VRSHRuv8i8
  { 1197,	4,	1,	57,	"VRSQRTEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1197 = VRSQRTEd
  { 1198,	4,	1,	57,	"VRSQRTEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1198 = VRSQRTEfd
  { 1199,	4,	1,	58,	"VRSQRTEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1199 = VRSQRTEfq
  { 1200,	4,	1,	58,	"VRSQRTEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1200 = VRSQRTEq
  { 1201,	5,	1,	40,	"VRSQRTSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1201 = VRSQRTSfd
  { 1202,	5,	1,	41,	"VRSQRTSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1202 = VRSQRTSfq
  { 1203,	6,	1,	33,	"VRSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1203 = VRSRAsv16i8
  { 1204,	6,	1,	33,	"VRSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1204 = VRSRAsv1i64
  { 1205,	6,	1,	33,	"VRSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1205 = VRSRAsv2i32
  { 1206,	6,	1,	33,	"VRSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1206 = VRSRAsv2i64
  { 1207,	6,	1,	33,	"VRSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1207 = VRSRAsv4i16
  { 1208,	6,	1,	33,	"VRSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1208 = VRSRAsv4i32
  { 1209,	6,	1,	33,	"VRSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1209 = VRSRAsv8i16
  { 1210,	6,	1,	33,	"VRSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1210 = VRSRAsv8i8
  { 1211,	6,	1,	33,	"VRSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1211 = VRSRAuv16i8
  { 1212,	6,	1,	33,	"VRSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1212 = VRSRAuv1i64
  { 1213,	6,	1,	33,	"VRSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1213 = VRSRAuv2i32
  { 1214,	6,	1,	33,	"VRSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1214 = VRSRAuv2i64
  { 1215,	6,	1,	33,	"VRSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1215 = VRSRAuv4i16
  { 1216,	6,	1,	33,	"VRSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1216 = VRSRAuv4i32
  { 1217,	6,	1,	33,	"VRSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1217 = VRSRAuv8i16
  { 1218,	6,	1,	33,	"VRSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1218 = VRSRAuv8i8
  { 1219,	5,	1,	3,	"VRSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 },  // Inst #1219 = VRSUBHNv2i32
  { 1220,	5,	1,	3,	"VRSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 },  // Inst #1220 = VRSUBHNv4i16
  { 1221,	5,	1,	3,	"VRSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 },  // Inst #1221 = VRSUBHNv8i8
  { 1222,	6,	1,	25,	"VSETLNi16", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo127 },  // Inst #1222 = VSETLNi16
  { 1223,	6,	1,	25,	"VSETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo127 },  // Inst #1223 = VSETLNi32
  { 1224,	6,	1,	25,	"VSETLNi8", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo127 },  // Inst #1224 = VSETLNi8
  { 1225,	5,	1,	44,	"VSHLLi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 },  // Inst #1225 = VSHLLi16
  { 1226,	5,	1,	44,	"VSHLLi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 },  // Inst #1226 = VSHLLi32
  { 1227,	5,	1,	44,	"VSHLLi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 },  // Inst #1227 = VSHLLi8
  { 1228,	5,	1,	44,	"VSHLLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 },  // Inst #1228 = VSHLLsv2i64
  { 1229,	5,	1,	44,	"VSHLLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 },  // Inst #1229 = VSHLLsv4i32
  { 1230,	5,	1,	44,	"VSHLLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 },  // Inst #1230 = VSHLLsv8i16
  { 1231,	5,	1,	44,	"VSHLLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 },  // Inst #1231 = VSHLLuv2i64
  { 1232,	5,	1,	44,	"VSHLLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 },  // Inst #1232 = VSHLLuv4i32
  { 1233,	5,	1,	44,	"VSHLLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 },  // Inst #1233 = VSHLLuv8i16
  { 1234,	5,	1,	44,	"VSHLiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1234 = VSHLiv16i8
  { 1235,	5,	1,	44,	"VSHLiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1235 = VSHLiv1i64
  { 1236,	5,	1,	44,	"VSHLiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1236 = VSHLiv2i32
  { 1237,	5,	1,	44,	"VSHLiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1237 = VSHLiv2i64
  { 1238,	5,	1,	44,	"VSHLiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1238 = VSHLiv4i16
  { 1239,	5,	1,	44,	"VSHLiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1239 = VSHLiv4i32
  { 1240,	5,	1,	44,	"VSHLiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1240 = VSHLiv8i16
  { 1241,	5,	1,	44,	"VSHLiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1241 = VSHLiv8i8
  { 1242,	5,	1,	45,	"VSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1242 = VSHLsv16i8
  { 1243,	5,	1,	44,	"VSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1243 = VSHLsv1i64
  { 1244,	5,	1,	44,	"VSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1244 = VSHLsv2i32
  { 1245,	5,	1,	45,	"VSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1245 = VSHLsv2i64
  { 1246,	5,	1,	44,	"VSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1246 = VSHLsv4i16
  { 1247,	5,	1,	45,	"VSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1247 = VSHLsv4i32
  { 1248,	5,	1,	45,	"VSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1248 = VSHLsv8i16
  { 1249,	5,	1,	44,	"VSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1249 = VSHLsv8i8
  { 1250,	5,	1,	45,	"VSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1250 = VSHLuv16i8
  { 1251,	5,	1,	44,	"VSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1251 = VSHLuv1i64
  { 1252,	5,	1,	44,	"VSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1252 = VSHLuv2i32
  { 1253,	5,	1,	45,	"VSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1253 = VSHLuv2i64
  { 1254,	5,	1,	44,	"VSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1254 = VSHLuv4i16
  { 1255,	5,	1,	45,	"VSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1255 = VSHLuv4i32
  { 1256,	5,	1,	45,	"VSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1256 = VSHLuv8i16
  { 1257,	5,	1,	44,	"VSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1257 = VSHLuv8i8
  { 1258,	5,	1,	44,	"VSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1258 = VSHRNv2i32
  { 1259,	5,	1,	44,	"VSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1259 = VSHRNv4i16
  { 1260,	5,	1,	44,	"VSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 },  // Inst #1260 = VSHRNv8i8
  { 1261,	5,	1,	44,	"VSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1261 = VSHRsv16i8
  { 1262,	5,	1,	44,	"VSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1262 = VSHRsv1i64
  { 1263,	5,	1,	44,	"VSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1263 = VSHRsv2i32
  { 1264,	5,	1,	44,	"VSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1264 = VSHRsv2i64
  { 1265,	5,	1,	44,	"VSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1265 = VSHRsv4i16
  { 1266,	5,	1,	44,	"VSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1266 = VSHRsv4i32
  { 1267,	5,	1,	44,	"VSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1267 = VSHRsv8i16
  { 1268,	5,	1,	44,	"VSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1268 = VSHRsv8i8
  { 1269,	5,	1,	44,	"VSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1269 = VSHRuv16i8
  { 1270,	5,	1,	44,	"VSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1270 = VSHRuv1i64
  { 1271,	5,	1,	44,	"VSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1271 = VSHRuv2i32
  { 1272,	5,	1,	44,	"VSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1272 = VSHRuv2i64
  { 1273,	5,	1,	44,	"VSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1273 = VSHRuv4i16
  { 1274,	5,	1,	44,	"VSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1274 = VSHRuv4i32
  { 1275,	5,	1,	44,	"VSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 },  // Inst #1275 = VSHRuv8i16
  { 1276,	5,	1,	44,	"VSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 },  // Inst #1276 = VSHRuv8i8
  { 1277,	5,	1,	67,	"VSHTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 },  // Inst #1277 = VSHTOD
  { 1278,	5,	1,	68,	"VSHTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 },  // Inst #1278 = VSHTOS
  { 1279,	4,	1,	67,	"VSITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo75 },  // Inst #1279 = VSITOD
  { 1280,	4,	1,	68,	"VSITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 },  // Inst #1280 = VSITOS
  { 1281,	6,	1,	45,	"VSLIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1281 = VSLIv16i8
  { 1282,	6,	1,	44,	"VSLIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1282 = VSLIv1i64
  { 1283,	6,	1,	44,	"VSLIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1283 = VSLIv2i32
  { 1284,	6,	1,	45,	"VSLIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1284 = VSLIv2i64
  { 1285,	6,	1,	44,	"VSLIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1285 = VSLIv4i16
  { 1286,	6,	1,	45,	"VSLIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1286 = VSLIv4i32
  { 1287,	6,	1,	45,	"VSLIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1287 = VSLIv8i16
  { 1288,	6,	1,	44,	"VSLIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1288 = VSLIv8i8
  { 1289,	5,	1,	67,	"VSLTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 },  // Inst #1289 = VSLTOD
  { 1290,	5,	1,	68,	"VSLTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 },  // Inst #1290 = VSLTOS
  { 1291,	4,	1,	81,	"VSQRTD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1291 = VSQRTD
  { 1292,	4,	1,	80,	"VSQRTS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 },  // Inst #1292 = VSQRTS
  { 1293,	6,	1,	33,	"VSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1293 = VSRAsv16i8
  { 1294,	6,	1,	33,	"VSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1294 = VSRAsv1i64
  { 1295,	6,	1,	33,	"VSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1295 = VSRAsv2i32
  { 1296,	6,	1,	33,	"VSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1296 = VSRAsv2i64
  { 1297,	6,	1,	33,	"VSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1297 = VSRAsv4i16
  { 1298,	6,	1,	33,	"VSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1298 = VSRAsv4i32
  { 1299,	6,	1,	33,	"VSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1299 = VSRAsv8i16
  { 1300,	6,	1,	33,	"VSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1300 = VSRAsv8i8
  { 1301,	6,	1,	33,	"VSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1301 = VSRAuv16i8
  { 1302,	6,	1,	33,	"VSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1302 = VSRAuv1i64
  { 1303,	6,	1,	33,	"VSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1303 = VSRAuv2i32
  { 1304,	6,	1,	33,	"VSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1304 = VSRAuv2i64
  { 1305,	6,	1,	33,	"VSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1305 = VSRAuv4i16
  { 1306,	6,	1,	33,	"VSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1306 = VSRAuv4i32
  { 1307,	6,	1,	33,	"VSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1307 = VSRAuv8i16
  { 1308,	6,	1,	33,	"VSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1308 = VSRAuv8i8
  { 1309,	6,	1,	45,	"VSRIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1309 = VSRIv16i8
  { 1310,	6,	1,	44,	"VSRIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1310 = VSRIv1i64
  { 1311,	6,	1,	44,	"VSRIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1311 = VSRIv2i32
  { 1312,	6,	1,	45,	"VSRIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1312 = VSRIv2i64
  { 1313,	6,	1,	44,	"VSRIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1313 = VSRIv4i16
  { 1314,	6,	1,	45,	"VSRIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1314 = VSRIv4i32
  { 1315,	6,	1,	45,	"VSRIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 },  // Inst #1315 = VSRIv8i16
  { 1316,	6,	1,	44,	"VSRIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 },  // Inst #1316 = VSRIv8i8
  { 1317,	7,	0,	46,	"VST1d16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 },  // Inst #1317 = VST1d16
  { 1318,	10,	0,	46,	"VST1d16Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 },  // Inst #1318 = VST1d16Q
  { 1319,	9,	0,	46,	"VST1d16T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 },  // Inst #1319 = VST1d16T
  { 1320,	7,	0,	46,	"VST1d32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 },  // Inst #1320 = VST1d32
  { 1321,	10,	0,	46,	"VST1d32Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 },  // Inst #1321 = VST1d32Q
  { 1322,	9,	0,	46,	"VST1d32T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 },  // Inst #1322 = VST1d32T
  { 1323,	7,	0,	46,	"VST1d64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 },  // Inst #1323 = VST1d64
  { 1324,	7,	0,	46,	"VST1d8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 },  // Inst #1324 = VST1d8
  { 1325,	10,	0,	46,	"VST1d8Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 },  // Inst #1325 = VST1d8Q
  { 1326,	9,	0,	46,	"VST1d8T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 },  // Inst #1326 = VST1d8T
  { 1327,	7,	0,	46,	"VST1df", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 },  // Inst #1327 = VST1df
  { 1328,	7,	0,	46,	"VST1q16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 },  // Inst #1328 = VST1q16
  { 1329,	7,	0,	46,	"VST1q32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 },  // Inst #1329 = VST1q32
  { 1330,	7,	0,	46,	"VST1q64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 },  // Inst #1330 = VST1q64
  { 1331,	7,	0,	46,	"VST1q8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 },  // Inst #1331 = VST1q8
  { 1332,	7,	0,	46,	"VST1qf", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 },  // Inst #1332 = VST1qf
  { 1333,	9,	0,	46,	"VST2LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 },  // Inst #1333 = VST2LNd16
  { 1334,	9,	0,	46,	"VST2LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 },  // Inst #1334 = VST2LNd32
  { 1335,	9,	0,	46,	"VST2LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 },  // Inst #1335 = VST2LNd8
  { 1336,	9,	0,	46,	"VST2LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 },  // Inst #1336 = VST2LNq16a
  { 1337,	9,	0,	46,	"VST2LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 },  // Inst #1337 = VST2LNq16b
  { 1338,	9,	0,	46,	"VST2LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 },  // Inst #1338 = VST2LNq32a
  { 1339,	9,	0,	46,	"VST2LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 },  // Inst #1339 = VST2LNq32b
  { 1340,	8,	0,	46,	"VST2d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 },  // Inst #1340 = VST2d16
  { 1341,	8,	0,	46,	"VST2d16D", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 },  // Inst #1341 = VST2d16D
  { 1342,	8,	0,	46,	"VST2d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 },  // Inst #1342 = VST2d32
  { 1343,	8,	0,	46,	"VST2d32D", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 },  // Inst #1343 = VST2d32D
  { 1344,	8,	0,	46,	"VST2d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 },  // Inst #1344 = VST2d64
  { 1345,	8,	0,	46,	"VST2d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 },  // Inst #1345 = VST2d8
  { 1346,	8,	0,	46,	"VST2d8D", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 },  // Inst #1346 = VST2d8D
  { 1347,	10,	0,	46,	"VST2q16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 },  // Inst #1347 = VST2q16
  { 1348,	10,	0,	46,	"VST2q32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 },  // Inst #1348 = VST2q32
  { 1349,	10,	0,	46,	"VST2q8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 },  // Inst #1349 = VST2q8
  { 1350,	10,	0,	46,	"VST3LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 },  // Inst #1350 = VST3LNd16
  { 1351,	10,	0,	46,	"VST3LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 },  // Inst #1351 = VST3LNd32
  { 1352,	10,	0,	46,	"VST3LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 },  // Inst #1352 = VST3LNd8
  { 1353,	10,	0,	46,	"VST3LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 },  // Inst #1353 = VST3LNq16a
  { 1354,	10,	0,	46,	"VST3LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 },  // Inst #1354 = VST3LNq16b
  { 1355,	10,	0,	46,	"VST3LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 },  // Inst #1355 = VST3LNq32a
  { 1356,	10,	0,	46,	"VST3LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 },  // Inst #1356 = VST3LNq32b
  { 1357,	9,	0,	46,	"VST3d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 },  // Inst #1357 = VST3d16
  { 1358,	9,	0,	46,	"VST3d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 },  // Inst #1358 = VST3d32
  { 1359,	9,	0,	46,	"VST3d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 },  // Inst #1359 = VST3d64
  { 1360,	9,	0,	46,	"VST3d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 },  // Inst #1360 = VST3d8
  { 1361,	10,	1,	46,	"VST3q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 },  // Inst #1361 = VST3q16a
  { 1362,	10,	1,	46,	"VST3q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 },  // Inst #1362 = VST3q16b
  { 1363,	10,	1,	46,	"VST3q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 },  // Inst #1363 = VST3q32a
  { 1364,	10,	1,	46,	"VST3q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 },  // Inst #1364 = VST3q32b
  { 1365,	10,	1,	46,	"VST3q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 },  // Inst #1365 = VST3q8a
  { 1366,	10,	1,	46,	"VST3q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 },  // Inst #1366 = VST3q8b
  { 1367,	11,	0,	46,	"VST4LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 },  // Inst #1367 = VST4LNd16
  { 1368,	11,	0,	46,	"VST4LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 },  // Inst #1368 = VST4LNd32
  { 1369,	11,	0,	46,	"VST4LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 },  // Inst #1369 = VST4LNd8
  { 1370,	11,	0,	46,	"VST4LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 },  // Inst #1370 = VST4LNq16a
  { 1371,	11,	0,	46,	"VST4LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 },  // Inst #1371 = VST4LNq16b
  { 1372,	11,	0,	46,	"VST4LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 },  // Inst #1372 = VST4LNq32a
  { 1373,	11,	0,	46,	"VST4LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 },  // Inst #1373 = VST4LNq32b
  { 1374,	10,	0,	46,	"VST4d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 },  // Inst #1374 = VST4d16
  { 1375,	10,	0,	46,	"VST4d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 },  // Inst #1375 = VST4d32
  { 1376,	10,	0,	46,	"VST4d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 },  // Inst #1376 = VST4d64
  { 1377,	10,	0,	46,	"VST4d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 },  // Inst #1377 = VST4d8
  { 1378,	11,	1,	46,	"VST4q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 },  // Inst #1378 = VST4q16a
  { 1379,	11,	1,	46,	"VST4q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 },  // Inst #1379 = VST4q16b
  { 1380,	11,	1,	46,	"VST4q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 },  // Inst #1380 = VST4q32a
  { 1381,	11,	1,	46,	"VST4q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 },  // Inst #1381 = VST4q32b
  { 1382,	11,	1,	46,	"VST4q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 },  // Inst #1382 = VST4q8a
  { 1383,	11,	1,	46,	"VST4q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 },  // Inst #1383 = VST4q8b
  { 1384,	5,	0,	85,	"VSTMD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo35 },  // Inst #1384 = VSTMD
  { 1385,	5,	0,	85,	"VSTMS", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo35 },  // Inst #1385 = VSTMS
  { 1386,	5,	0,	84,	"VSTRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo96 },  // Inst #1386 = VSTRD
  { 1387,	5,	0,	85,	"VSTRQ", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 },  // Inst #1387 = VSTRQ
  { 1388,	5,	0,	83,	"VSTRS", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo98 },  // Inst #1388 = VSTRS
  { 1389,	5,	1,	62,	"VSUBD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1389 = VSUBD
  { 1390,	5,	1,	3,	"VSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 },  // Inst #1390 = VSUBHNv2i32
  { 1391,	5,	1,	3,	"VSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 },  // Inst #1391 = VSUBHNv4i16
  { 1392,	5,	1,	3,	"VSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 },  // Inst #1392 = VSUBHNv8i8
  { 1393,	5,	1,	44,	"VSUBLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #1393 = VSUBLsv2i64
  { 1394,	5,	1,	44,	"VSUBLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #1394 = VSUBLsv4i32
  { 1395,	5,	1,	44,	"VSUBLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #1395 = VSUBLsv8i16
  { 1396,	5,	1,	44,	"VSUBLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #1396 = VSUBLuv2i64
  { 1397,	5,	1,	44,	"VSUBLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #1397 = VSUBLuv4i32
  { 1398,	5,	1,	44,	"VSUBLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 },  // Inst #1398 = VSUBLuv8i16
  { 1399,	5,	1,	61,	"VSUBS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 },  // Inst #1399 = VSUBS
  { 1400,	5,	1,	47,	"VSUBWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 },  // Inst #1400 = VSUBWsv2i64
  { 1401,	5,	1,	47,	"VSUBWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 },  // Inst #1401 = VSUBWsv4i32
  { 1402,	5,	1,	47,	"VSUBWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 },  // Inst #1402 = VSUBWsv8i16
  { 1403,	5,	1,	47,	"VSUBWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 },  // Inst #1403 = VSUBWuv2i64
  { 1404,	5,	1,	47,	"VSUBWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 },  // Inst #1404 = VSUBWuv4i32
  { 1405,	5,	1,	47,	"VSUBWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 },  // Inst #1405 = VSUBWuv8i16
  { 1406,	5,	1,	1,	"VSUBfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1406 = VSUBfd
  { 1407,	5,	1,	1,	"VSUBfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 },  // Inst #1407 = VSUBfd_sfp
  { 1408,	5,	1,	2,	"VSUBfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1408 = VSUBfq
  { 1409,	5,	1,	48,	"VSUBv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1409 = VSUBv16i8
  { 1410,	5,	1,	47,	"VSUBv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1410 = VSUBv1i64
  { 1411,	5,	1,	47,	"VSUBv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1411 = VSUBv2i32
  { 1412,	5,	1,	48,	"VSUBv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1412 = VSUBv2i64
  { 1413,	5,	1,	47,	"VSUBv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1413 = VSUBv4i16
  { 1414,	5,	1,	48,	"VSUBv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1414 = VSUBv4i32
  { 1415,	5,	1,	48,	"VSUBv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1415 = VSUBv8i16
  { 1416,	5,	1,	47,	"VSUBv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1416 = VSUBv8i8
  { 1417,	4,	1,	128,	"VSWPd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 },  // Inst #1417 = VSWPd
  { 1418,	4,	1,	128,	"VSWPq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 },  // Inst #1418 = VSWPq
  { 1419,	5,	1,	49,	"VTBL1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1419 = VTBL1
  { 1420,	6,	1,	50,	"VTBL2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo140 },  // Inst #1420 = VTBL2
  { 1421,	7,	1,	51,	"VTBL3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo141 },  // Inst #1421 = VTBL3
  { 1422,	8,	1,	52,	"VTBL4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo142 },  // Inst #1422 = VTBL4
  { 1423,	6,	1,	53,	"VTBX1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 },  // Inst #1423 = VTBX1
  { 1424,	7,	1,	54,	"VTBX2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo143 },  // Inst #1424 = VTBX2
  { 1425,	8,	1,	55,	"VTBX3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo144 },  // Inst #1425 = VTBX3
  { 1426,	9,	1,	56,	"VTBX4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo145 },  // Inst #1426 = VTBX4
  { 1427,	5,	1,	65,	"VTOSHD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 },  // Inst #1427 = VTOSHD
  { 1428,	5,	1,	70,	"VTOSHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 },  // Inst #1428 = VTOSHS
  { 1429,	4,	1,	65,	"VTOSIRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 },  // Inst #1429 = VTOSIRD
  { 1430,	4,	1,	70,	"VTOSIRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 },  // Inst #1430 = VTOSIRS
  { 1431,	4,	1,	65,	"VTOSIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 },  // Inst #1431 = VTOSIZD
  { 1432,	4,	1,	70,	"VTOSIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 },  // Inst #1432 = VTOSIZS
  { 1433,	5,	1,	65,	"VTOSLD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 },  // Inst #1433 = VTOSLD
  { 1434,	5,	1,	70,	"VTOSLS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 },  // Inst #1434 = VTOSLS
  { 1435,	5,	1,	65,	"VTOUHD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 },  // Inst #1435 = VTOUHD
  { 1436,	5,	1,	70,	"VTOUHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 },  // Inst #1436 = VTOUHS
  { 1437,	4,	1,	65,	"VTOUIRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 },  // Inst #1437 = VTOUIRD
  { 1438,	4,	1,	70,	"VTOUIRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 },  // Inst #1438 = VTOUIRS
  { 1439,	4,	1,	65,	"VTOUIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 },  // Inst #1439 = VTOUIZD
  { 1440,	4,	1,	70,	"VTOUIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 },  // Inst #1440 = VTOUIZS
  { 1441,	5,	1,	65,	"VTOULD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 },  // Inst #1441 = VTOULD
  { 1442,	5,	1,	70,	"VTOULS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 },  // Inst #1442 = VTOULS
  { 1443,	6,	2,	35,	"VTRNd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 },  // Inst #1443 = VTRNd16
  { 1444,	6,	2,	35,	"VTRNd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 },  // Inst #1444 = VTRNd32
  { 1445,	6,	2,	35,	"VTRNd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 },  // Inst #1445 = VTRNd8
  { 1446,	6,	2,	36,	"VTRNq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 },  // Inst #1446 = VTRNq16
  { 1447,	6,	2,	36,	"VTRNq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 },  // Inst #1447 = VTRNq32
  { 1448,	6,	2,	36,	"VTRNq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 },  // Inst #1448 = VTRNq8
  { 1449,	5,	1,	4,	"VTSTv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1449 = VTSTv16i8
  { 1450,	5,	1,	3,	"VTSTv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1450 = VTSTv2i32
  { 1451,	5,	1,	3,	"VTSTv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1451 = VTSTv4i16
  { 1452,	5,	1,	4,	"VTSTv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1452 = VTSTv4i32
  { 1453,	5,	1,	4,	"VTSTv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 },  // Inst #1453 = VTSTv8i16
  { 1454,	5,	1,	3,	"VTSTv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 },  // Inst #1454 = VTSTv8i8
  { 1455,	5,	1,	67,	"VUHTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 },  // Inst #1455 = VUHTOD
  { 1456,	5,	1,	68,	"VUHTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 },  // Inst #1456 = VUHTOS
  { 1457,	4,	1,	67,	"VUITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo75 },  // Inst #1457 = VUITOD
  { 1458,	4,	1,	68,	"VUITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 },  // Inst #1458 = VUITOS
  { 1459,	5,	1,	67,	"VULTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 },  // Inst #1459 = VULTOD
  { 1460,	5,	1,	68,	"VULTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 },  // Inst #1460 = VULTOS
  { 1461,	6,	2,	35,	"VUZPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 },  // Inst #1461 = VUZPd16
  { 1462,	6,	2,	35,	"VUZPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 },  // Inst #1462 = VUZPd32
  { 1463,	6,	2,	35,	"VUZPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 },  // Inst #1463 = VUZPd8
  { 1464,	6,	2,	37,	"VUZPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 },  // Inst #1464 = VUZPq16
  { 1465,	6,	2,	37,	"VUZPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 },  // Inst #1465 = VUZPq32
  { 1466,	6,	2,	37,	"VUZPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 },  // Inst #1466 = VUZPq8
  { 1467,	6,	2,	35,	"VZIPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 },  // Inst #1467 = VZIPd16
  { 1468,	6,	2,	35,	"VZIPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 },  // Inst #1468 = VZIPd32
  { 1469,	6,	2,	35,	"VZIPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 },  // Inst #1469 = VZIPd8
  { 1470,	6,	2,	37,	"VZIPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 },  // Inst #1470 = VZIPq16
  { 1471,	6,	2,	37,	"VZIPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 },  // Inst #1471 = VZIPq32
  { 1472,	6,	2,	37,	"VZIPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 },  // Inst #1472 = VZIPq8
  { 1473,	2,	0,	128,	"WFE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1473 = WFE
  { 1474,	2,	0,	128,	"WFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1474 = WFI
  { 1475,	2,	0,	128,	"YIELD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1475 = YIELD
  { 1476,	6,	1,	88,	"t2ADCSri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 },  // Inst #1476 = t2ADCSri
  { 1477,	6,	1,	89,	"t2ADCSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 },  // Inst #1477 = t2ADCSrr
  { 1478,	7,	1,	90,	"t2ADCSrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo48 },  // Inst #1478 = t2ADCSrs
  { 1479,	6,	1,	88,	"t2ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 },  // Inst #1479 = t2ADCri
  { 1480,	6,	1,	89,	"t2ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 },  // Inst #1480 = t2ADCrr
  { 1481,	7,	1,	90,	"t2ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo48 },  // Inst #1481 = t2ADCrs
  { 1482,	5,	1,	88,	"t2ADDSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 },  // Inst #1482 = t2ADDSri
  { 1483,	5,	1,	89,	"t2ADDSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 },  // Inst #1483 = t2ADDSrr
  { 1484,	6,	1,	90,	"t2ADDSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #1484 = t2ADDSrs
  { 1485,	6,	1,	88,	"t2ADDrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1485 = t2ADDrSPi
  { 1486,	5,	1,	88,	"t2ADDrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1486 = t2ADDrSPi12
  { 1487,	7,	1,	90,	"t2ADDrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 },  // Inst #1487 = t2ADDrSPs
  { 1488,	6,	1,	88,	"t2ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1488 = t2ADDri
  { 1489,	6,	1,	88,	"t2ADDri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1489 = t2ADDri12
  { 1490,	6,	1,	89,	"t2ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #1490 = t2ADDrr
  { 1491,	7,	1,	90,	"t2ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 },  // Inst #1491 = t2ADDrs
  { 1492,	6,	1,	88,	"t2ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1492 = t2ANDri
  { 1493,	6,	1,	89,	"t2ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #1493 = t2ANDrr
  { 1494,	7,	1,	90,	"t2ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 },  // Inst #1494 = t2ANDrs
  { 1495,	6,	1,	113,	"t2ASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1495 = t2ASRri
  { 1496,	6,	1,	114,	"t2ASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #1496 = t2ASRrr
  { 1497,	1,	0,	0,	"t2B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 },  // Inst #1497 = t2B
  { 1498,	5,	1,	126,	"t2BFC", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 },  // Inst #1498 = t2BFC
  { 1499,	6,	1,	88,	"t2BFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo51 },  // Inst #1499 = t2BFI
  { 1500,	6,	1,	88,	"t2BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1500 = t2BICri
  { 1501,	6,	1,	89,	"t2BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #1501 = t2BICrr
  { 1502,	7,	1,	90,	"t2BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 },  // Inst #1502 = t2BICrs
  { 1503,	4,	0,	0,	"t2BR_JT", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo18 },  // Inst #1503 = t2BR_JT
  { 1504,	3,	0,	128,	"t2BXJ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 },  // Inst #1504 = t2BXJ
  { 1505,	3,	0,	0,	"t2Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #1505 = t2Bcc
  { 1506,	2,	0,	128,	"t2CLREX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1506 = t2CLREX
  { 1507,	4,	1,	125,	"t2CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1507 = t2CLZ
  { 1508,	4,	0,	97,	"t2CMNzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #1508 = t2CMNzri
  { 1509,	4,	0,	98,	"t2CMNzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #1509 = t2CMNzrr
  { 1510,	5,	0,	99,	"t2CMNzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 },  // Inst #1510 = t2CMNzrs
  { 1511,	4,	0,	97,	"t2CMPri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #1511 = t2CMPri
  { 1512,	4,	0,	98,	"t2CMPrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #1512 = t2CMPrr
  { 1513,	5,	0,	99,	"t2CMPrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 },  // Inst #1513 = t2CMPrs
  { 1514,	4,	0,	97,	"t2CMPzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #1514 = t2CMPzri
  { 1515,	4,	0,	98,	"t2CMPzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #1515 = t2CMPzrr
  { 1516,	5,	0,	99,	"t2CMPzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 },  // Inst #1516 = t2CMPzrs
  { 1517,	1,	0,	128,	"t2CPS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 },  // Inst #1517 = t2CPS
  { 1518,	3,	0,	128,	"t2DBG", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #1518 = t2DBG
  { 1519,	2,	0,	128,	"t2DMBish", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1519 = t2DMBish
  { 1520,	2,	0,	128,	"t2DMBishst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1520 = t2DMBishst
  { 1521,	2,	0,	128,	"t2DMBnsh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1521 = t2DMBnsh
  { 1522,	2,	0,	128,	"t2DMBnshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1522 = t2DMBnshst
  { 1523,	2,	0,	128,	"t2DMBosh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1523 = t2DMBosh
  { 1524,	2,	0,	128,	"t2DMBoshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1524 = t2DMBoshst
  { 1525,	2,	0,	128,	"t2DMBst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1525 = t2DMBst
  { 1526,	2,	0,	128,	"t2DSBish", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1526 = t2DSBish
  { 1527,	2,	0,	128,	"t2DSBishst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1527 = t2DSBishst
  { 1528,	2,	0,	128,	"t2DSBnsh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1528 = t2DSBnsh
  { 1529,	2,	0,	128,	"t2DSBnshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1529 = t2DSBnshst
  { 1530,	2,	0,	128,	"t2DSBosh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1530 = t2DSBosh
  { 1531,	2,	0,	128,	"t2DSBoshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1531 = t2DSBoshst
  { 1532,	2,	0,	128,	"t2DSBst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1532 = t2DSBst
  { 1533,	6,	1,	88,	"t2EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1533 = t2EORri
  { 1534,	6,	1,	89,	"t2EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #1534 = t2EORrr
  { 1535,	7,	1,	90,	"t2EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 },  // Inst #1535 = t2EORrs
  { 1536,	2,	0,	128,	"t2ISBsy", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1536 = t2ISBsy
  { 1537,	2,	0,	92,	"t2IT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 },  // Inst #1537 = t2IT
  { 1538,	0,	0,	128,	"t2Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 },  // Inst #1538 = t2Int_MemBarrierV7
  { 1539,	0,	0,	128,	"t2Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 },  // Inst #1539 = t2Int_SyncBarrierV7
  { 1540,	2,	0,	128,	"t2Int_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList6, Barriers3, OperandInfo149 },  // Inst #1540 = t2Int_eh_sjlj_setjmp
  { 1541,	5,	0,	103,	"t2LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 },  // Inst #1541 = t2LDM
  { 1542,	5,	0,	0,	"t2LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 },  // Inst #1542 = t2LDM_RET
  { 1543,	5,	1,	101,	"t2LDRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1543 = t2LDRBT
  { 1544,	6,	2,	102,	"t2LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 },  // Inst #1544 = t2LDRB_POST
  { 1545,	6,	2,	102,	"t2LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 },  // Inst #1545 = t2LDRB_PRE
  { 1546,	5,	1,	101,	"t2LDRBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1546 = t2LDRBi12
  { 1547,	5,	1,	101,	"t2LDRBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1547 = t2LDRBi8
  { 1548,	4,	1,	101,	"t2LDRBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1548 = t2LDRBpci
  { 1549,	6,	1,	104,	"t2LDRBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1549 = t2LDRBs
  { 1550,	6,	2,	101,	"t2LDRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1550 = t2LDRDi8
  { 1551,	5,	2,	101,	"t2LDRDpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1551 = t2LDRDpci
  { 1552,	4,	1,	128,	"t2LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1552 = t2LDREX
  { 1553,	4,	1,	128,	"t2LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1553 = t2LDREXB
  { 1554,	5,	2,	128,	"t2LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1554 = t2LDREXD
  { 1555,	4,	1,	128,	"t2LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1555 = t2LDREXH
  { 1556,	5,	1,	101,	"t2LDRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1556 = t2LDRHT
  { 1557,	6,	2,	102,	"t2LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 },  // Inst #1557 = t2LDRH_POST
  { 1558,	6,	2,	102,	"t2LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 },  // Inst #1558 = t2LDRH_PRE
  { 1559,	5,	1,	101,	"t2LDRHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1559 = t2LDRHi12
  { 1560,	5,	1,	101,	"t2LDRHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1560 = t2LDRHi8
  { 1561,	4,	1,	101,	"t2LDRHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1561 = t2LDRHpci
  { 1562,	6,	1,	104,	"t2LDRHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1562 = t2LDRHs
  { 1563,	5,	1,	101,	"t2LDRSBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1563 = t2LDRSBT
  { 1564,	6,	2,	102,	"t2LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 },  // Inst #1564 = t2LDRSB_POST
  { 1565,	6,	2,	102,	"t2LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 },  // Inst #1565 = t2LDRSB_PRE
  { 1566,	5,	1,	101,	"t2LDRSBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1566 = t2LDRSBi12
  { 1567,	5,	1,	101,	"t2LDRSBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1567 = t2LDRSBi8
  { 1568,	4,	1,	101,	"t2LDRSBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1568 = t2LDRSBpci
  { 1569,	6,	1,	104,	"t2LDRSBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1569 = t2LDRSBs
  { 1570,	5,	1,	101,	"t2LDRSHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1570 = t2LDRSHT
  { 1571,	6,	2,	102,	"t2LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 },  // Inst #1571 = t2LDRSH_POST
  { 1572,	6,	2,	102,	"t2LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 },  // Inst #1572 = t2LDRSH_PRE
  { 1573,	5,	1,	101,	"t2LDRSHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1573 = t2LDRSHi12
  { 1574,	5,	1,	101,	"t2LDRSHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1574 = t2LDRSHi8
  { 1575,	4,	1,	101,	"t2LDRSHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1575 = t2LDRSHpci
  { 1576,	6,	1,	104,	"t2LDRSHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1576 = t2LDRSHs
  { 1577,	5,	1,	101,	"t2LDRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1577 = t2LDRT
  { 1578,	6,	2,	102,	"t2LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 },  // Inst #1578 = t2LDR_POST
  { 1579,	6,	2,	102,	"t2LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 },  // Inst #1579 = t2LDR_PRE
  { 1580,	5,	1,	101,	"t2LDRi12", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1580 = t2LDRi12
  { 1581,	5,	1,	101,	"t2LDRi8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1581 = t2LDRi8
  { 1582,	4,	1,	101,	"t2LDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1582 = t2LDRpci
  { 1583,	3,	1,	128,	"t2LDRpci_pic", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo20 },  // Inst #1583 = t2LDRpci_pic
  { 1584,	6,	1,	104,	"t2LDRs", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1584 = t2LDRs
  { 1585,	4,	1,	88,	"t2LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1585 = t2LEApcrel
  { 1586,	5,	1,	88,	"t2LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo38 },  // Inst #1586 = t2LEApcrelJT
  { 1587,	6,	1,	113,	"t2LSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1587 = t2LSLri
  { 1588,	6,	1,	114,	"t2LSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #1588 = t2LSLrr
  { 1589,	6,	1,	113,	"t2LSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1589 = t2LSRri
  { 1590,	6,	1,	114,	"t2LSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #1590 = t2LSRrr
  { 1591,	6,	1,	109,	"t2MLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1591 = t2MLA
  { 1592,	6,	1,	109,	"t2MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1592 = t2MLS
  { 1593,	6,	1,	95,	"t2MOVCCasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 },  // Inst #1593 = t2MOVCCasr
  { 1594,	5,	1,	93,	"t2MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 },  // Inst #1594 = t2MOVCCi
  { 1595,	6,	1,	95,	"t2MOVCClsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 },  // Inst #1595 = t2MOVCClsl
  { 1596,	6,	1,	95,	"t2MOVCClsr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 },  // Inst #1596 = t2MOVCClsr
  { 1597,	5,	1,	94,	"t2MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo44 },  // Inst #1597 = t2MOVCCr
  { 1598,	6,	1,	95,	"t2MOVCCror", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 },  // Inst #1598 = t2MOVCCror
  { 1599,	5,	1,	111,	"t2MOVTi16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 },  // Inst #1599 = t2MOVTi16
  { 1600,	5,	1,	111,	"t2MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo46 },  // Inst #1600 = t2MOVi
  { 1601,	4,	1,	111,	"t2MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1601 = t2MOVi16
  { 1602,	4,	1,	111,	"t2MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(2<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1602 = t2MOVi32imm
  { 1603,	5,	1,	112,	"t2MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo47 },  // Inst #1603 = t2MOVr
  { 1604,	5,	1,	113,	"t2MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo47 },  // Inst #1604 = t2MOVrx
  { 1605,	2,	1,	113,	"t2MOVsra_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo32 },  // Inst #1605 = t2MOVsra_flag
  { 1606,	2,	1,	113,	"t2MOVsrl_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo32 },  // Inst #1606 = t2MOVsrl_flag
  { 1607,	3,	1,	128,	"t2MRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 },  // Inst #1607 = t2MRS
  { 1608,	3,	1,	128,	"t2MRSsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 },  // Inst #1608 = t2MRSsys
  { 1609,	3,	0,	128,	"t2MSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 },  // Inst #1609 = t2MSR
  { 1610,	3,	0,	128,	"t2MSRsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 },  // Inst #1610 = t2MSRsys
  { 1611,	5,	1,	116,	"t2MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1611 = t2MUL
  { 1612,	5,	1,	111,	"t2MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo46 },  // Inst #1612 = t2MVNi
  { 1613,	4,	1,	112,	"t2MVNr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1613 = t2MVNr
  { 1614,	5,	1,	113,	"t2MVNs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1614 = t2MVNs
  { 1615,	2,	0,	128,	"t2NOP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1615 = t2NOP
  { 1616,	6,	1,	88,	"t2ORNri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1616 = t2ORNri
  { 1617,	6,	1,	89,	"t2ORNrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #1617 = t2ORNrr
  { 1618,	7,	1,	90,	"t2ORNrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 },  // Inst #1618 = t2ORNrs
  { 1619,	6,	1,	88,	"t2ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1619 = t2ORRri
  { 1620,	6,	1,	89,	"t2ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #1620 = t2ORRrr
  { 1621,	7,	1,	90,	"t2ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 },  // Inst #1621 = t2ORRrs
  { 1622,	6,	1,	90,	"t2PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1622 = t2PKHBT
  { 1623,	6,	1,	90,	"t2PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1623 = t2PKHTB
  { 1624,	4,	0,	101,	"t2PLDWi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1624 = t2PLDWi12
  { 1625,	4,	0,	101,	"t2PLDWi8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1625 = t2PLDWi8
  { 1626,	4,	0,	101,	"t2PLDWpci", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1626 = t2PLDWpci
  { 1627,	4,	0,	101,	"t2PLDWr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1627 = t2PLDWr
  { 1628,	5,	0,	101,	"t2PLDWs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1628 = t2PLDWs
  { 1629,	4,	0,	101,	"t2PLDi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1629 = t2PLDi12
  { 1630,	4,	0,	101,	"t2PLDi8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1630 = t2PLDi8
  { 1631,	4,	0,	101,	"t2PLDpci", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1631 = t2PLDpci
  { 1632,	4,	0,	101,	"t2PLDr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1632 = t2PLDr
  { 1633,	5,	0,	101,	"t2PLDs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1633 = t2PLDs
  { 1634,	4,	0,	101,	"t2PLIi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1634 = t2PLIi12
  { 1635,	4,	0,	101,	"t2PLIi8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1635 = t2PLIi8
  { 1636,	4,	0,	101,	"t2PLIpci", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 },  // Inst #1636 = t2PLIpci
  { 1637,	4,	0,	101,	"t2PLIr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1637 = t2PLIr
  { 1638,	5,	0,	101,	"t2PLIs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1638 = t2PLIs
  { 1639,	5,	1,	128,	"t2QADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1639 = t2QADD
  { 1640,	5,	1,	128,	"t2QADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1640 = t2QADD16
  { 1641,	5,	1,	128,	"t2QADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1641 = t2QADD8
  { 1642,	5,	1,	128,	"t2QASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1642 = t2QASX
  { 1643,	5,	1,	128,	"t2QDADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1643 = t2QDADD
  { 1644,	5,	1,	128,	"t2QDSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1644 = t2QDSUB
  { 1645,	5,	1,	128,	"t2QSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1645 = t2QSAX
  { 1646,	5,	1,	128,	"t2QSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1646 = t2QSUB
  { 1647,	5,	1,	128,	"t2QSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1647 = t2QSUB16
  { 1648,	5,	1,	128,	"t2QSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1648 = t2QSUB8
  { 1649,	4,	1,	125,	"t2RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1649 = t2RBIT
  { 1650,	4,	1,	125,	"t2REV", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1650 = t2REV
  { 1651,	4,	1,	125,	"t2REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1651 = t2REV16
  { 1652,	4,	1,	125,	"t2REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1652 = t2REVSH
  { 1653,	3,	0,	128,	"t2RFEDB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 },  // Inst #1653 = t2RFEDB
  { 1654,	3,	0,	128,	"t2RFEDBW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 },  // Inst #1654 = t2RFEDBW
  { 1655,	3,	0,	128,	"t2RFEIA", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 },  // Inst #1655 = t2RFEIA
  { 1656,	3,	0,	128,	"t2RFEIAW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 },  // Inst #1656 = t2RFEIAW
  { 1657,	6,	1,	113,	"t2RORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1657 = t2RORri
  { 1658,	6,	1,	114,	"t2RORrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #1658 = t2RORrr
  { 1659,	4,	1,	88,	"t2RSBSri", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo152 },  // Inst #1659 = t2RSBSri
  { 1660,	5,	1,	90,	"t2RSBSrs", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo153 },  // Inst #1660 = t2RSBSrs
  { 1661,	5,	1,	88,	"t2RSBri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1661 = t2RSBri
  { 1662,	6,	1,	90,	"t2RSBrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1662 = t2RSBrs
  { 1663,	5,	1,	128,	"t2SADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1663 = t2SADD16
  { 1664,	5,	1,	128,	"t2SADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1664 = t2SADD8
  { 1665,	5,	1,	128,	"t2SASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1665 = t2SASX
  { 1666,	6,	1,	88,	"t2SBCSri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 },  // Inst #1666 = t2SBCSri
  { 1667,	6,	1,	89,	"t2SBCSrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 },  // Inst #1667 = t2SBCSrr
  { 1668,	7,	1,	90,	"t2SBCSrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo48 },  // Inst #1668 = t2SBCSrs
  { 1669,	6,	1,	88,	"t2SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 },  // Inst #1669 = t2SBCri
  { 1670,	6,	1,	89,	"t2SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 },  // Inst #1670 = t2SBCrr
  { 1671,	7,	1,	90,	"t2SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo48 },  // Inst #1671 = t2SBCrs
  { 1672,	6,	1,	88,	"t2SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo51 },  // Inst #1672 = t2SBFX
  { 1673,	5,	1,	88,	"t2SDIV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1673 = t2SDIV
  { 1674,	5,	1,	128,	"t2SEL", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1674 = t2SEL
  { 1675,	2,	0,	128,	"t2SEV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1675 = t2SEV
  { 1676,	5,	1,	128,	"t2SHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1676 = t2SHADD16
  { 1677,	5,	1,	128,	"t2SHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1677 = t2SHADD8
  { 1678,	5,	1,	128,	"t2SHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1678 = t2SHASX
  { 1679,	5,	1,	128,	"t2SHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1679 = t2SHSAX
  { 1680,	5,	1,	128,	"t2SHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1680 = t2SHSUB16
  { 1681,	5,	1,	128,	"t2SHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1681 = t2SHSUB8
  { 1682,	3,	0,	128,	"t2SMC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #1682 = t2SMC
  { 1683,	6,	1,	108,	"t2SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1683 = t2SMLABB
  { 1684,	6,	1,	108,	"t2SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1684 = t2SMLABT
  { 1685,	6,	1,	109,	"t2SMLAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1685 = t2SMLAD
  { 1686,	6,	1,	109,	"t2SMLADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1686 = t2SMLADX
  { 1687,	6,	2,	110,	"t2SMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1687 = t2SMLAL
  { 1688,	6,	2,	110,	"t2SMLALBB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1688 = t2SMLALBB
  { 1689,	6,	2,	110,	"t2SMLALBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1689 = t2SMLALBT
  { 1690,	6,	2,	110,	"t2SMLALD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1690 = t2SMLALD
  { 1691,	6,	2,	110,	"t2SMLALDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1691 = t2SMLALDX
  { 1692,	6,	2,	110,	"t2SMLALTB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1692 = t2SMLALTB
  { 1693,	6,	2,	110,	"t2SMLALTT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1693 = t2SMLALTT
  { 1694,	6,	1,	108,	"t2SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1694 = t2SMLATB
  { 1695,	6,	1,	108,	"t2SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1695 = t2SMLATT
  { 1696,	6,	1,	108,	"t2SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1696 = t2SMLAWB
  { 1697,	6,	1,	108,	"t2SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1697 = t2SMLAWT
  { 1698,	6,	1,	109,	"t2SMLSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1698 = t2SMLSD
  { 1699,	6,	1,	109,	"t2SMLSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1699 = t2SMLSDX
  { 1700,	6,	2,	110,	"t2SMLSLD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1700 = t2SMLSLD
  { 1701,	6,	2,	110,	"t2SMLSLDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1701 = t2SMLSLDX
  { 1702,	6,	1,	109,	"t2SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1702 = t2SMMLA
  { 1703,	6,	1,	109,	"t2SMMLAR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1703 = t2SMMLAR
  { 1704,	6,	1,	109,	"t2SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1704 = t2SMMLS
  { 1705,	6,	1,	109,	"t2SMMLSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1705 = t2SMMLSR
  { 1706,	5,	1,	116,	"t2SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1706 = t2SMMUL
  { 1707,	5,	1,	116,	"t2SMMULR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1707 = t2SMMULR
  { 1708,	5,	1,	109,	"t2SMUAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1708 = t2SMUAD
  { 1709,	5,	1,	109,	"t2SMUADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1709 = t2SMUADX
  { 1710,	5,	1,	116,	"t2SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1710 = t2SMULBB
  { 1711,	5,	1,	116,	"t2SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1711 = t2SMULBT
  { 1712,	6,	2,	117,	"t2SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1712 = t2SMULL
  { 1713,	5,	1,	116,	"t2SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1713 = t2SMULTB
  { 1714,	5,	1,	116,	"t2SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1714 = t2SMULTT
  { 1715,	5,	1,	115,	"t2SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1715 = t2SMULWB
  { 1716,	5,	1,	115,	"t2SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1716 = t2SMULWT
  { 1717,	5,	1,	109,	"t2SMUSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1717 = t2SMUSD
  { 1718,	5,	1,	109,	"t2SMUSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1718 = t2SMUSDX
  { 1719,	3,	0,	128,	"t2SRSDB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #1719 = t2SRSDB
  { 1720,	3,	0,	128,	"t2SRSDBW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #1720 = t2SRSDBW
  { 1721,	3,	0,	128,	"t2SRSIA", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #1721 = t2SRSIA
  { 1722,	3,	0,	128,	"t2SRSIAW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #1722 = t2SRSIAW
  { 1723,	5,	1,	128,	"t2SSAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo52 },  // Inst #1723 = t2SSAT16
  { 1724,	6,	1,	128,	"t2SSATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 },  // Inst #1724 = t2SSATasr
  { 1725,	6,	1,	128,	"t2SSATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 },  // Inst #1725 = t2SSATlsl
  { 1726,	5,	1,	128,	"t2SSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1726 = t2SSAX
  { 1727,	5,	1,	128,	"t2SSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1727 = t2SSUB16
  { 1728,	5,	1,	128,	"t2SSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1728 = t2SSUB8
  { 1729,	5,	0,	120,	"t2STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 },  // Inst #1729 = t2STM
  { 1730,	5,	1,	118,	"t2STRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1730 = t2STRBT
  { 1731,	6,	1,	119,	"t2STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 },  // Inst #1731 = t2STRB_POST
  { 1732,	6,	1,	119,	"t2STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 },  // Inst #1732 = t2STRB_PRE
  { 1733,	5,	0,	118,	"t2STRBi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1733 = t2STRBi12
  { 1734,	5,	0,	118,	"t2STRBi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1734 = t2STRBi8
  { 1735,	6,	0,	121,	"t2STRBs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1735 = t2STRBs
  { 1736,	6,	0,	121,	"t2STRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1736 = t2STRDi8
  { 1737,	5,	1,	128,	"t2STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo56 },  // Inst #1737 = t2STREX
  { 1738,	5,	1,	128,	"t2STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo56 },  // Inst #1738 = t2STREXB
  { 1739,	6,	1,	128,	"t2STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo57 },  // Inst #1739 = t2STREXD
  { 1740,	5,	1,	128,	"t2STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo56 },  // Inst #1740 = t2STREXH
  { 1741,	5,	1,	118,	"t2STRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1741 = t2STRHT
  { 1742,	6,	1,	119,	"t2STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 },  // Inst #1742 = t2STRH_POST
  { 1743,	6,	1,	119,	"t2STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 },  // Inst #1743 = t2STRH_PRE
  { 1744,	5,	0,	118,	"t2STRHi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1744 = t2STRHi12
  { 1745,	5,	0,	118,	"t2STRHi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1745 = t2STRHi8
  { 1746,	6,	0,	121,	"t2STRHs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1746 = t2STRHs
  { 1747,	5,	1,	118,	"t2STRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1747 = t2STRT
  { 1748,	6,	1,	119,	"t2STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 },  // Inst #1748 = t2STR_POST
  { 1749,	6,	1,	119,	"t2STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 },  // Inst #1749 = t2STR_PRE
  { 1750,	5,	0,	118,	"t2STRi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1750 = t2STRi12
  { 1751,	5,	0,	118,	"t2STRi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1751 = t2STRi8
  { 1752,	6,	0,	121,	"t2STRs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1752 = t2STRs
  { 1753,	5,	1,	88,	"t2SUBSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 },  // Inst #1753 = t2SUBSri
  { 1754,	5,	1,	89,	"t2SUBSrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 },  // Inst #1754 = t2SUBSrr
  { 1755,	6,	1,	90,	"t2SUBSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #1755 = t2SUBSrs
  { 1756,	6,	1,	88,	"t2SUBrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1756 = t2SUBrSPi
  { 1757,	5,	1,	88,	"t2SUBrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1757 = t2SUBrSPi12
  { 1758,	3,	1,	128,	"t2SUBrSPi12_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 },  // Inst #1758 = t2SUBrSPi12_
  { 1759,	3,	1,	128,	"t2SUBrSPi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 },  // Inst #1759 = t2SUBrSPi_
  { 1760,	7,	1,	90,	"t2SUBrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 },  // Inst #1760 = t2SUBrSPs
  { 1761,	4,	1,	128,	"t2SUBrSPs_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo155 },  // Inst #1761 = t2SUBrSPs_
  { 1762,	6,	1,	88,	"t2SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1762 = t2SUBri
  { 1763,	6,	1,	88,	"t2SUBri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 },  // Inst #1763 = t2SUBri12
  { 1764,	6,	1,	89,	"t2SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 },  // Inst #1764 = t2SUBrr
  { 1765,	7,	1,	90,	"t2SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 },  // Inst #1765 = t2SUBrs
  { 1766,	5,	1,	89,	"t2SXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1766 = t2SXTAB16rr
  { 1767,	6,	1,	91,	"t2SXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1767 = t2SXTAB16rr_rot
  { 1768,	5,	1,	89,	"t2SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1768 = t2SXTABrr
  { 1769,	6,	1,	91,	"t2SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1769 = t2SXTABrr_rot
  { 1770,	5,	1,	89,	"t2SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1770 = t2SXTAHrr
  { 1771,	6,	1,	91,	"t2SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1771 = t2SXTAHrr_rot
  { 1772,	4,	1,	125,	"t2SXTB16r", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1772 = t2SXTB16r
  { 1773,	5,	1,	126,	"t2SXTB16r_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1773 = t2SXTB16r_rot
  { 1774,	4,	1,	125,	"t2SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1774 = t2SXTBr
  { 1775,	5,	1,	126,	"t2SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1775 = t2SXTBr_rot
  { 1776,	4,	1,	125,	"t2SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1776 = t2SXTHr
  { 1777,	5,	1,	126,	"t2SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1777 = t2SXTHr_rot
  { 1778,	3,	0,	0,	"t2TBB", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 },  // Inst #1778 = t2TBB
  { 1779,	4,	0,	0,	"t2TBBgen", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1779 = t2TBBgen
  { 1780,	3,	0,	0,	"t2TBH", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 },  // Inst #1780 = t2TBH
  { 1781,	4,	0,	0,	"t2TBHgen", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1781 = t2TBHgen
  { 1782,	4,	0,	97,	"t2TEQri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #1782 = t2TEQri
  { 1783,	4,	0,	98,	"t2TEQrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #1783 = t2TEQrr
  { 1784,	5,	0,	99,	"t2TEQrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 },  // Inst #1784 = t2TEQrs
  { 1785,	0,	0,	0,	"t2TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList7, Barriers1, 0 },  // Inst #1785 = t2TPsoft
  { 1786,	4,	0,	97,	"t2TSTri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #1786 = t2TSTri
  { 1787,	4,	0,	98,	"t2TSTrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #1787 = t2TSTrr
  { 1788,	5,	0,	99,	"t2TSTrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 },  // Inst #1788 = t2TSTrs
  { 1789,	5,	1,	128,	"t2UADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1789 = t2UADD16
  { 1790,	5,	1,	128,	"t2UADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1790 = t2UADD8
  { 1791,	5,	1,	128,	"t2UASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1791 = t2UASX
  { 1792,	6,	1,	88,	"t2UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo51 },  // Inst #1792 = t2UBFX
  { 1793,	5,	1,	88,	"t2UDIV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1793 = t2UDIV
  { 1794,	5,	1,	128,	"t2UHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1794 = t2UHADD16
  { 1795,	5,	1,	128,	"t2UHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1795 = t2UHADD8
  { 1796,	5,	1,	128,	"t2UHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1796 = t2UHASX
  { 1797,	5,	1,	128,	"t2UHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1797 = t2UHSAX
  { 1798,	5,	1,	128,	"t2UHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1798 = t2UHSUB16
  { 1799,	5,	1,	128,	"t2UHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1799 = t2UHSUB8
  { 1800,	6,	2,	110,	"t2UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1800 = t2UMAAL
  { 1801,	6,	2,	110,	"t2UMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1801 = t2UMLAL
  { 1802,	6,	2,	117,	"t2UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1802 = t2UMULL
  { 1803,	5,	1,	128,	"t2UQADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1803 = t2UQADD16
  { 1804,	5,	1,	128,	"t2UQADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1804 = t2UQADD8
  { 1805,	5,	1,	128,	"t2UQASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1805 = t2UQASX
  { 1806,	5,	1,	128,	"t2UQSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1806 = t2UQSAX
  { 1807,	5,	1,	128,	"t2UQSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1807 = t2UQSUB16
  { 1808,	5,	1,	128,	"t2UQSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1808 = t2UQSUB8
  { 1809,	5,	1,	128,	"t2USAD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1809 = t2USAD8
  { 1810,	6,	1,	128,	"t2USADA8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 },  // Inst #1810 = t2USADA8
  { 1811,	5,	1,	128,	"t2USAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo52 },  // Inst #1811 = t2USAT16
  { 1812,	6,	1,	128,	"t2USATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 },  // Inst #1812 = t2USATasr
  { 1813,	6,	1,	128,	"t2USATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 },  // Inst #1813 = t2USATlsl
  { 1814,	5,	1,	128,	"t2USAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1814 = t2USAX
  { 1815,	5,	1,	128,	"t2USUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1815 = t2USUB16
  { 1816,	5,	1,	128,	"t2USUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1816 = t2USUB8
  { 1817,	5,	1,	89,	"t2UXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1817 = t2UXTAB16rr
  { 1818,	6,	1,	91,	"t2UXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1818 = t2UXTAB16rr_rot
  { 1819,	5,	1,	89,	"t2UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1819 = t2UXTABrr
  { 1820,	6,	1,	91,	"t2UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1820 = t2UXTABrr_rot
  { 1821,	5,	1,	89,	"t2UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 },  // Inst #1821 = t2UXTAHrr
  { 1822,	6,	1,	91,	"t2UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 },  // Inst #1822 = t2UXTAHrr_rot
  { 1823,	4,	1,	125,	"t2UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1823 = t2UXTB16r
  { 1824,	5,	1,	126,	"t2UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1824 = t2UXTB16r_rot
  { 1825,	4,	1,	125,	"t2UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1825 = t2UXTBr
  { 1826,	5,	1,	126,	"t2UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1826 = t2UXTBr_rot
  { 1827,	4,	1,	125,	"t2UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 },  // Inst #1827 = t2UXTHr
  { 1828,	5,	1,	126,	"t2UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 },  // Inst #1828 = t2UXTHr_rot
  { 1829,	2,	0,	128,	"t2WFE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1829 = t2WFE
  { 1830,	2,	0,	128,	"t2WFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1830 = t2WFI
  { 1831,	2,	0,	128,	"t2YIELD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1831 = t2YIELD
  { 1832,	6,	2,	89,	"tADC", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo156 },  // Inst #1832 = tADC
  { 1833,	5,	1,	89,	"tADDhirr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo44 },  // Inst #1833 = tADDhirr
  { 1834,	6,	2,	88,	"tADDi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 },  // Inst #1834 = tADDi3
  { 1835,	6,	2,	88,	"tADDi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo158 },  // Inst #1835 = tADDi8
  { 1836,	2,	1,	88,	"tADDrPCi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 },  // Inst #1836 = tADDrPCi
  { 1837,	3,	1,	89,	"tADDrSP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo160 },  // Inst #1837 = tADDrSP
  { 1838,	3,	1,	88,	"tADDrSPi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo161 },  // Inst #1838 = tADDrSPi
  { 1839,	6,	2,	89,	"tADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 },  // Inst #1839 = tADDrr
  { 1840,	3,	1,	88,	"tADDspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 },  // Inst #1840 = tADDspi
  { 1841,	3,	1,	89,	"tADDspr", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo160 },  // Inst #1841 = tADDspr
  { 1842,	3,	1,	128,	"tADDspr_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo3 },  // Inst #1842 = tADDspr_
  { 1843,	1,	0,	128,	"tADJCALLSTACKDOWN", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo14 },  // Inst #1843 = tADJCALLSTACKDOWN
  { 1844,	2,	0,	128,	"tADJCALLSTACKUP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo148 },  // Inst #1844 = tADJCALLSTACKUP
  { 1845,	6,	2,	89,	"tAND", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 },  // Inst #1845 = tAND
  { 1846,	3,	1,	128,	"tANDsp", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, ImplicitList1, Barriers1, OperandInfo164 },  // Inst #1846 = tANDsp
  { 1847,	6,	2,	113,	"tASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 },  // Inst #1847 = tASRri
  { 1848,	6,	2,	114,	"tASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 },  // Inst #1848 = tASRrr
  { 1849,	1,	0,	0,	"tB", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 },  // Inst #1849 = tB
  { 1850,	6,	2,	89,	"tBIC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 },  // Inst #1850 = tBIC
  { 1851,	1,	0,	128,	"tBKPT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 },  // Inst #1851 = tBKPT
  { 1852,	1,	0,	0,	"tBL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 },  // Inst #1852 = tBL
  { 1853,	1,	0,	0,	"tBLXi", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 },  // Inst #1853 = tBLXi
  { 1854,	1,	0,	0,	"tBLXi_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 },  // Inst #1854 = tBLXi_r9
  { 1855,	1,	0,	0,	"tBLXr", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 },  // Inst #1855 = tBLXr
  { 1856,	1,	0,	0,	"tBLXr_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 },  // Inst #1856 = tBLXr_r9
  { 1857,	1,	0,	0,	"tBLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 },  // Inst #1857 = tBLr9
  { 1858,	1,	0,	0,	"tBRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo16 },  // Inst #1858 = tBRIND
  { 1859,	3,	0,	0,	"tBR_JTr", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo165 },  // Inst #1859 = tBR_JTr
  { 1860,	1,	0,	0,	"tBX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo17 },  // Inst #1860 = tBX
  { 1861,	0,	0,	0,	"tBX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 },  // Inst #1861 = tBX_RET
  { 1862,	1,	0,	0,	"tBX_RET_vararg", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo17 },  // Inst #1862 = tBX_RET_vararg
  { 1863,	1,	0,	0,	"tBXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo17 },  // Inst #1863 = tBXr9
  { 1864,	3,	0,	0,	"tBcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #1864 = tBcc
  { 1865,	1,	0,	0,	"tBfar", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, ImplicitList8, NULL, OperandInfo14 },  // Inst #1865 = tBfar
  { 1866,	2,	0,	0,	"tCBNZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 },  // Inst #1866 = tCBNZ
  { 1867,	2,	0,	0,	"tCBZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 },  // Inst #1867 = tCBZ
  { 1868,	4,	0,	98,	"tCMNz", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 },  // Inst #1868 = tCMNz
  { 1869,	4,	0,	98,	"tCMPhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #1869 = tCMPhir
  { 1870,	4,	0,	97,	"tCMPi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo167 },  // Inst #1870 = tCMPi8
  { 1871,	4,	0,	98,	"tCMPr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 },  // Inst #1871 = tCMPr
  { 1872,	4,	0,	98,	"tCMPzhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #1872 = tCMPzhir
  { 1873,	4,	0,	97,	"tCMPzi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo167 },  // Inst #1873 = tCMPzi8
  { 1874,	4,	0,	98,	"tCMPzr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 },  // Inst #1874 = tCMPzr
  { 1875,	1,	0,	128,	"tCPS", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 },  // Inst #1875 = tCPS
  { 1876,	6,	2,	89,	"tEOR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 },  // Inst #1876 = tEOR
  { 1877,	2,	0,	128,	"tInt_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList9, Barriers4, OperandInfo168 },  // Inst #1877 = tInt_eh_sjlj_setjmp
  { 1878,	5,	0,	103,	"tLDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 },  // Inst #1878 = tLDM
  { 1879,	6,	1,	104,	"tLDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 },  // Inst #1879 = tLDR
  { 1880,	6,	1,	104,	"tLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 },  // Inst #1880 = tLDRB
  { 1881,	6,	1,	104,	"tLDRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 },  // Inst #1881 = tLDRBi
  { 1882,	6,	1,	104,	"tLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 },  // Inst #1882 = tLDRH
  { 1883,	6,	1,	104,	"tLDRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 },  // Inst #1883 = tLDRHi
  { 1884,	5,	1,	104,	"tLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo170 },  // Inst #1884 = tLDRSB
  { 1885,	5,	1,	104,	"tLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo170 },  // Inst #1885 = tLDRSH
  { 1886,	4,	1,	101,	"tLDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo167 },  // Inst #1886 = tLDRcp
  { 1887,	6,	1,	104,	"tLDRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 },  // Inst #1887 = tLDRi
  { 1888,	4,	1,	101,	"tLDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo167 },  // Inst #1888 = tLDRpci
  { 1889,	3,	1,	128,	"tLDRpci_pic", 0|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo20 },  // Inst #1889 = tLDRpci_pic
  { 1890,	5,	1,	101,	"tLDRspi", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 },  // Inst #1890 = tLDRspi
  { 1891,	4,	1,	88,	"tLEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo167 },  // Inst #1891 = tLEApcrel
  { 1892,	5,	1,	88,	"tLEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo172 },  // Inst #1892 = tLEApcrelJT
  { 1893,	6,	2,	113,	"tLSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 },  // Inst #1893 = tLSLri
  { 1894,	6,	2,	114,	"tLSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 },  // Inst #1894 = tLSLrr
  { 1895,	6,	2,	113,	"tLSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 },  // Inst #1895 = tLSRri
  { 1896,	6,	2,	114,	"tLSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 },  // Inst #1896 = tLSRrr
  { 1897,	5,	1,	93,	"tMOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo173 },  // Inst #1897 = tMOVCCi
  { 1898,	5,	1,	94,	"tMOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo44 },  // Inst #1898 = tMOVCCr
  { 1899,	5,	1,	128,	"tMOVCCr_pseudo", 0|(1<<TID::Predicable)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo170 },  // Inst #1899 = tMOVCCr_pseudo
  { 1900,	2,	1,	112,	"tMOVSr", 0, 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo168 },  // Inst #1900 = tMOVSr
  { 1901,	2,	1,	112,	"tMOVgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 },  // Inst #1901 = tMOVgpr2gpr
  { 1902,	2,	1,	112,	"tMOVgpr2tgpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo174 },  // Inst #1902 = tMOVgpr2tgpr
  { 1903,	5,	2,	111,	"tMOVi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo175 },  // Inst #1903 = tMOVi8
  { 1904,	2,	1,	112,	"tMOVr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo168 },  // Inst #1904 = tMOVr
  { 1905,	2,	1,	112,	"tMOVtgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 },  // Inst #1905 = tMOVtgpr2gpr
  { 1906,	6,	2,	116,	"tMUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 },  // Inst #1906 = tMUL
  { 1907,	5,	2,	112,	"tMVN", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo176 },  // Inst #1907 = tMVN
  { 1908,	2,	0,	128,	"tNOP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1908 = tNOP
  { 1909,	6,	2,	89,	"tORR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 },  // Inst #1909 = tORR
  { 1910,	3,	1,	89,	"tPICADD", 0|(1<<TID::NotDuplicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 },  // Inst #1910 = tPICADD
  { 1911,	3,	0,	0,	"tPOP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo177 },  // Inst #1911 = tPOP
  { 1912,	3,	0,	0,	"tPOP_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo177 },  // Inst #1912 = tPOP_RET
  { 1913,	3,	0,	0,	"tPUSH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo177 },  // Inst #1913 = tPUSH
  { 1914,	4,	1,	125,	"tREV", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 },  // Inst #1914 = tREV
  { 1915,	4,	1,	125,	"tREV16", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 },  // Inst #1915 = tREV16
  { 1916,	4,	1,	125,	"tREVSH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 },  // Inst #1916 = tREVSH
  { 1917,	6,	2,	114,	"tROR", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 },  // Inst #1917 = tROR
  { 1918,	5,	2,	88,	"tRSB", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo176 },  // Inst #1918 = tRSB
  { 1919,	5,	1,	101,	"tRestore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 },  // Inst #1919 = tRestore
  { 1920,	6,	2,	89,	"tSBC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo156 },  // Inst #1920 = tSBC
  { 1921,	0,	0,	128,	"tSETENDBE", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 },  // Inst #1921 = tSETENDBE
  { 1922,	0,	0,	128,	"tSETENDLE", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 },  // Inst #1922 = tSETENDLE
  { 1923,	2,	0,	128,	"tSEV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1923 = tSEV
  { 1924,	5,	0,	120,	"tSTM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 },  // Inst #1924 = tSTM
  { 1925,	6,	0,	121,	"tSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 },  // Inst #1925 = tSTR
  { 1926,	6,	0,	121,	"tSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 },  // Inst #1926 = tSTRB
  { 1927,	6,	0,	121,	"tSTRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 },  // Inst #1927 = tSTRBi
  { 1928,	6,	0,	121,	"tSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 },  // Inst #1928 = tSTRH
  { 1929,	6,	0,	121,	"tSTRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 },  // Inst #1929 = tSTRHi
  { 1930,	6,	0,	121,	"tSTRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 },  // Inst #1930 = tSTRi
  { 1931,	5,	0,	118,	"tSTRspi", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 },  // Inst #1931 = tSTRspi
  { 1932,	6,	2,	88,	"tSUBi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 },  // Inst #1932 = tSUBi3
  { 1933,	6,	2,	88,	"tSUBi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo158 },  // Inst #1933 = tSUBi8
  { 1934,	6,	2,	89,	"tSUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 },  // Inst #1934 = tSUBrr
  { 1935,	3,	1,	88,	"tSUBspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 },  // Inst #1935 = tSUBspi
  { 1936,	3,	1,	128,	"tSUBspi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 },  // Inst #1936 = tSUBspi_
  { 1937,	3,	0,	0,	"tSVC", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 },  // Inst #1937 = tSVC
  { 1938,	4,	1,	125,	"tSXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 },  // Inst #1938 = tSXTB
  { 1939,	4,	1,	125,	"tSXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 },  // Inst #1939 = tSXTH
  { 1940,	5,	0,	118,	"tSpill", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 },  // Inst #1940 = tSpill
  { 1941,	0,	0,	0,	"tTPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList10, NULL, 0 },  // Inst #1941 = tTPsoft
  { 1942,	0,	0,	0,	"tTRAP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 },  // Inst #1942 = tTRAP
  { 1943,	4,	0,	98,	"tTST", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 },  // Inst #1943 = tTST
  { 1944,	4,	1,	125,	"tUXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 },  // Inst #1944 = tUXTB
  { 1945,	4,	1,	125,	"tUXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 },  // Inst #1945 = tUXTH
  { 1946,	2,	0,	128,	"tWFE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1946 = tWFE
  { 1947,	2,	0,	128,	"tWFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1947 = tWFI
  { 1948,	2,	0,	128,	"tYIELD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 },  // Inst #1948 = tYIELD
};
} // End llvm namespace