//===- TableGen'erated file -------------------------------------*- C++ -*-===//
//
// Target Instruction Descriptors
//
// Automatically generated file, do not edit!
//
//===----------------------------------------------------------------------===//

namespace llvm {

static const unsigned ImplicitList1[] = { X86::EFLAGS, 0 };
static const TargetRegisterClass* Barriers1[] = { &X86::CCRRegClass, NULL };
static const unsigned ImplicitList2[] = { X86::ESP, 0 };
static const unsigned ImplicitList3[] = { X86::ESP, X86::EFLAGS, 0 };
static const unsigned ImplicitList4[] = { X86::RSP, 0 };
static const unsigned ImplicitList5[] = { X86::RSP, X86::EFLAGS, 0 };
static const unsigned ImplicitList6[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0 };
static const TargetRegisterClass* Barriers2[] = { &X86::CCRRegClass, &X86::GR32_ABCDRegClass, &X86::GR32_ADRegClass, &X86::GR32_TCRegClass, NULL };
static const unsigned ImplicitList7[] = { X86::EFLAGS, X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0 };
static const unsigned ImplicitList8[] = { X86::XMM0, 0 };
static const TargetRegisterClass* Barriers3[] = { &X86::CCRRegClass, &X86::FR32RegClass, &X86::FR64RegClass, &X86::GR32_ADRegClass, &X86::GR32_TCRegClass, &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, &X86::VR128RegClass, &X86::VR64RegClass, NULL };
static const unsigned ImplicitList9[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, 0 };
static const TargetRegisterClass* Barriers4[] = { &X86::CCRRegClass, &X86::FR32RegClass, &X86::FR64RegClass, &X86::GR64_TCRegClass, &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, &X86::VR128RegClass, &X86::VR64RegClass, NULL };
static const unsigned ImplicitList10[] = { X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::ST1, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, 0 };
static const unsigned ImplicitList11[] = { X86::AL, 0 };
static const unsigned ImplicitList12[] = { X86::AX, 0 };
static const unsigned ImplicitList13[] = { X86::EAX, 0 };
static const TargetRegisterClass* Barriers5[] = { &X86::GR32_ADRegClass, NULL };
static const unsigned ImplicitList14[] = { X86::EAX, X86::EDX, 0 };
static const unsigned ImplicitList15[] = { X86::RAX, 0 };
static const unsigned ImplicitList16[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, 0 };
static const unsigned ImplicitList17[] = { X86::RAX, X86::RDX, X86::EFLAGS, 0 };
static const TargetRegisterClass* Barriers6[] = { &X86::CCRRegClass, &X86::GR32_ADRegClass, NULL };
static const unsigned ImplicitList18[] = { X86::EAX, X86::EDX, X86::EFLAGS, 0 };
static const unsigned ImplicitList19[] = { X86::RAX, X86::RDX, 0 };
static const unsigned ImplicitList20[] = { X86::AX, X86::DX, 0 };
static const unsigned ImplicitList21[] = { X86::AX, X86::DX, X86::EFLAGS, 0 };
static const unsigned ImplicitList22[] = { X86::AL, X86::EFLAGS, X86::AX, 0 };
static const unsigned ImplicitList23[] = { X86::ST0, 0 };
static const unsigned ImplicitList24[] = { X86::ST1, 0 };
static const unsigned ImplicitList25[] = { X86::DX, 0 };
static const unsigned ImplicitList26[] = { X86::ECX, 0 };
static const unsigned ImplicitList27[] = { X86::AH, 0 };
static const unsigned ImplicitList28[] = { X86::AX, X86::EFLAGS, 0 };
static const unsigned ImplicitList29[] = { X86::EAX, X86::EFLAGS, 0 };
static const unsigned ImplicitList30[] = { X86::RAX, X86::EFLAGS, 0 };
static const unsigned ImplicitList31[] = { X86::AL, X86::EFLAGS, 0 };
static const unsigned ImplicitList32[] = { X86::EBP, X86::ESP, 0 };
static const unsigned ImplicitList33[] = { X86::RBP, X86::RSP, 0 };
static const unsigned ImplicitList34[] = { X86::EDI, 0 };
static const unsigned ImplicitList35[] = { X86::RDI, 0 };
static const unsigned ImplicitList36[] = { X86::EAX, X86::ESP, X86::EFLAGS, 0 };
static const unsigned ImplicitList37[] = { X86::EDI, X86::ESI, X86::EFLAGS, 0 };
static const unsigned ImplicitList38[] = { X86::EDI, X86::ESI, 0 };
static const unsigned ImplicitList39[] = { X86::DX, X86::AX, 0 };
static const unsigned ImplicitList40[] = { X86::DX, X86::EAX, 0 };
static const unsigned ImplicitList41[] = { X86::DX, X86::AL, 0 };
static const unsigned ImplicitList42[] = { X86::ECX, X86::EFLAGS, 0 };
static const unsigned ImplicitList43[] = { X86::XMM0, X86::EFLAGS, 0 };
static const TargetRegisterClass* Barriers7[] = { &X86::GR32_ABCDRegClass, &X86::GR32_ADRegClass, &X86::GR32_NOREXRegClass, &X86::GR32_TCRegClass, NULL };
static const unsigned ImplicitList44[] = { X86::EDI, X86::ESI, X86::EBP, X86::EBX, X86::EDX, X86::ECX, X86::EAX, X86::ESP, 0 };
static const unsigned ImplicitList45[] = { X86::CL, 0 };
static const unsigned ImplicitList46[] = { X86::RAX, X86::RCX, X86::RDX, 0 };
static const unsigned ImplicitList47[] = { X86::ECX, X86::EDI, X86::ESI, 0 };
static const unsigned ImplicitList48[] = { X86::RCX, X86::RDI, X86::RSI, 0 };
static const unsigned ImplicitList49[] = { X86::AL, X86::ECX, X86::EDI, 0 };
static const unsigned ImplicitList50[] = { X86::ECX, X86::EDI, 0 };
static const unsigned ImplicitList51[] = { X86::EAX, X86::ECX, X86::EDI, 0 };
static const unsigned ImplicitList52[] = { X86::RAX, X86::RCX, X86::RDI, 0 };
static const unsigned ImplicitList53[] = { X86::RCX, X86::RDI, 0 };
static const unsigned ImplicitList54[] = { X86::AX, X86::ECX, X86::EDI, 0 };
static const unsigned ImplicitList55[] = { X86::AL, X86::EDI, X86::EFLAGS, 0 };
static const unsigned ImplicitList56[] = { X86::EAX, X86::EDI, X86::EFLAGS, 0 };
static const unsigned ImplicitList57[] = { X86::RAX, X86::RCX, X86::RDI, X86::EFLAGS, 0 };
static const unsigned ImplicitList58[] = { X86::AX, X86::EDI, X86::EFLAGS, 0 };
static const unsigned ImplicitList59[] = { X86::EAX, X86::ECX, 0 };
static const TargetRegisterClass* Barriers8[] = { &X86::CCRRegClass, &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, &X86::VR64RegClass, NULL };
static const unsigned ImplicitList60[] = { X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::ST1, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::EFLAGS, 0 };

static const TargetOperandInfo OperandInfo2[] = { { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo3[] = { { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo4[] = { { -1, 0, 0 }, { -1, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo5[] = { { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo6[] = { { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo7[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo8[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo9[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo10[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo11[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo12[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo13[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo14[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo15[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo16[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo17[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo18[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo19[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo20[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo21[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo22[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo23[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo24[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo25[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo26[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo27[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR8RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo28[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo29[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR128RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo30[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo31[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo32[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo33[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo34[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo35[] = { { X86::RSTRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo36[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo37[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo38[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo39[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo40[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo41[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo42[] = { { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo43[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo44[] = { { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo45[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo46[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo47[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo48[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo49[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo50[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo51[] = { { X86::VR128RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo52[] = { { X86::VR256RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo53[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo54[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR128RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo55[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo56[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo57[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo58[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo59[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo60[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo61[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo62[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo63[] = { { X86::GR16RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo64[] = { { X86::GR32RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo65[] = { { X86::GR64RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo66[] = { { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo67[] = { { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo68[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo69[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo70[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP80RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo71[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo72[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo73[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo74[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo75[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo76[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo77[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo78[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo79[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo80[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo81[] = { { X86::GR8RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo82[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo83[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo84[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo85[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo86[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo87[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo88[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo89[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR8RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo90[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR8RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo91[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo92[] = { { X86::FR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo93[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo94[] = { { X86::FR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo95[] = { { X86::FR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo96[] = { { X86::FR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo97[] = { { X86::FR32RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo98[] = { { X86::FR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo99[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo100[] = { { X86::GR64RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo101[] = { { X86::GR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo102[] = { { X86::GR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo103[] = { { X86::GR32RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo104[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo105[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo106[] = { { X86::GR16RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo107[] = { { X86::GR8RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo108[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo109[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo110[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo111[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo112[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo113[] = { { X86::RFP32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo114[] = { { X86::RFP64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo115[] = { { X86::RFP80RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo116[] = { { X86::FR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo117[] = { { X86::FR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo118[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo119[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo120[] = { { X86::RFP32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo121[] = { { X86::RFP64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo122[] = { { X86::RFP80RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo123[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo124[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo125[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo126[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo127[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo128[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo129[] = { { X86::VR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo130[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo131[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo132[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo133[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo134[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo135[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo136[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo137[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo138[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo139[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo140[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo141[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo142[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { -1, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo143[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo144[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo145[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo146[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo147[] = { { X86::VR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo148[] = { { X86::VR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo149[] = { { X86::VR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo150[] = { { X86::FR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo151[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo152[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo153[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo154[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo155[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo156[] = { { X86::VR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo157[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo158[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo159[] = { { X86::VR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo160[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo161[] = { { X86::GR16RegClassID, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo162[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo163[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo164[] = { { X86::CONTROL_REGRegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo165[] = { { X86::DEBUG_REGRegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo166[] = { { X86::GR32_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { X86::GR32_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR32_TCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo167[] = { { X86::GR32RegClassID, 0, 0 }, { X86::CONTROL_REGRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo168[] = { { X86::GR32RegClassID, 0, 0 }, { X86::DEBUG_REGRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo169[] = { { X86::GR32_TCRegClassID, 0, 0 }, { X86::GR32_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { X86::GR32_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo170[] = { { X86::GR32_TCRegClassID, 0, 0 }, { X86::GR32_TCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo171[] = { { X86::GR32RegClassID, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo172[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo173[] = { { X86::CONTROL_REGRegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo174[] = { { X86::DEBUG_REGRegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo175[] = { { X86::GR64_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { X86::GR64_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR64_TCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo176[] = { { X86::GR64RegClassID, 0, 0 }, { X86::CONTROL_REGRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo177[] = { { X86::GR64RegClassID, 0, 0 }, { X86::DEBUG_REGRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo178[] = { { X86::GR64_TCRegClassID, 0, 0 }, { X86::GR64_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { X86::GR64_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo179[] = { { X86::GR64_TCRegClassID, 0, 0 }, { X86::GR64_TCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo180[] = { { X86::GR64RegClassID, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo181[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo182[] = { { X86::VR128RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo183[] = { { X86::GR64_NOREXRegClassID, 0, 0 }, { -1, 0, 0 }, { X86::GR64_NOREX_NOSPRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR8_NOREXRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo184[] = { { X86::GR8_NOREXRegClassID, 0, 0 }, { X86::GR64_NOREXRegClassID, 0, 0 }, { -1, 0, 0 }, { X86::GR64_NOREX_NOSPRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo185[] = { { X86::GR8_NOREXRegClassID, 0, 0 }, { X86::GR8_NOREXRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo186[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo187[] = { { X86::VR128RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo188[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo189[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo190[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo191[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo192[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo193[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo194[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo195[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo196[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo197[] = { { X86::GR32_NOREXRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo198[] = { { X86::GR32_NOREXRegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo199[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo200[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo201[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo202[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo203[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo204[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo205[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo206[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo207[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo208[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo209[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo210[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo211[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo212[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo213[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo214[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo215[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo216[] = { { X86::GR32_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { X86::GR32_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo217[] = { { X86::GR64_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { X86::GR64_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo218[] = { { X86::GR32_TCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo219[] = { { X86::GR64_TCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo220[] = { { X86::GR32_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { X86::GR32_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo221[] = { { X86::GR64_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { X86::GR64_TCRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo222[] = { { X86::GR32_TCRegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo223[] = { { X86::GR64_TCRegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo224[] = { { X86::VR256RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo225[] = { { X86::VR256RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo226[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo227[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo228[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo229[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo230[] = { { X86::GR8RegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo231[] = { { X86::VR256RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo232[] = { { X86::VR256RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo233[] = { { X86::VR256RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo234[] = { { X86::VR256RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo235[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo236[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo237[] = { { X86::VR256RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo238[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo239[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo240[] = { { X86::VR256RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo241[] = { { X86::VR256RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo242[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo243[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo244[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo245[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo246[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo247[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo248[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo249[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo250[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo251[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo252[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo253[] = { { X86::VR256RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo254[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo255[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo256[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo257[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo258[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo259[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo260[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo261[] = { { X86::VR256RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo262[] = { { X86::VR256RegClassID, 0, 0 }, { X86::VR256RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo263[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { -1, 0, 0 }, };
static const TargetOperandInfo OperandInfo264[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { -1, 0, 0 }, };

static const TargetInstrDesc X86Insts[] = {
  { 0,	0,	0,	0,	"PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, 0 },  // Inst #0 = PHI
  { 1,	0,	0,	0,	"INLINEASM", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, 0 },  // Inst #1 = INLINEASM
  { 2,	1,	0,	0,	"PROLOG_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #2 = PROLOG_LABEL
  { 3,	1,	0,	0,	"EH_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #3 = EH_LABEL
  { 4,	1,	0,	0,	"GC_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #4 = GC_LABEL
  { 5,	0,	0,	0,	"KILL", 0|(1<<TID::Variadic), 0x0ULL, NULL, NULL, NULL, 0 },  // Inst #5 = KILL
  { 6,	3,	1,	0,	"EXTRACT_SUBREG", 0, 0x0ULL, NULL, NULL, NULL, OperandInfo3 },  // Inst #6 = EXTRACT_SUBREG
  { 7,	4,	1,	0,	"INSERT_SUBREG", 0, 0x0ULL, NULL, NULL, NULL, OperandInfo4 },  // Inst #7 = INSERT_SUBREG
  { 8,	1,	1,	0,	"IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0x0ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #8 = IMPLICIT_DEF
  { 9,	4,	1,	0,	"SUBREG_TO_REG", 0, 0x0ULL, NULL, NULL, NULL, OperandInfo5 },  // Inst #9 = SUBREG_TO_REG
  { 10,	3,	1,	0,	"COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0x0ULL, NULL, NULL, NULL, OperandInfo3 },  // Inst #10 = COPY_TO_REGCLASS
  { 11,	0,	0,	0,	"DBG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0x0ULL, NULL, NULL, NULL, 0 },  // Inst #11 = DBG_VALUE
  { 12,	1,	1,	0,	"REG_SEQUENCE", 0|(1<<TID::Variadic)|(1<<TID::CheapAsAMove), 0x0ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #12 = REG_SEQUENCE
  { 13,	2,	1,	0,	"COPY", 0|(1<<TID::CheapAsAMove), 0x0ULL, NULL, NULL, NULL, OperandInfo6 },  // Inst #13 = COPY
  { 14,	0,	0,	0,	"ABS_F", 0|(1<<TID::UnmodeledSideEffects), 0xe1000401ULL, NULL, NULL, NULL, 0 },  // Inst #14 = ABS_F
  { 15,	2,	1,	0,	"ABS_Fp32", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo7 },  // Inst #15 = ABS_Fp32
  { 16,	2,	1,	0,	"ABS_Fp64", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo8 },  // Inst #16 = ABS_Fp64
  { 17,	2,	1,	0,	"ABS_Fp80", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo9 },  // Inst #17 = ABS_Fp80
  { 18,	1,	0,	0,	"ADC16i16", 0|(1<<TID::UnmodeledSideEffects), 0x15006041ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #18 = ADC16i16
  { 19,	6,	0,	0,	"ADC16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100605aULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #19 = ADC16mi
  { 20,	6,	0,	0,	"ADC16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300205aULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #20 = ADC16mi8
  { 21,	6,	0,	0,	"ADC16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x11000044ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #21 = ADC16mr
  { 22,	3,	1,	0,	"ADC16ri", 0, 0x81006052ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #22 = ADC16ri
  { 23,	3,	1,	0,	"ADC16ri8", 0, 0x83002052ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #23 = ADC16ri8
  { 24,	7,	1,	0,	"ADC16rm", 0|(1<<TID::MayLoad), 0x13000046ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 },  // Inst #24 = ADC16rm
  { 25,	3,	1,	0,	"ADC16rr", 0|(1<<TID::Commutable), 0x11000043ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #25 = ADC16rr
  { 26,	3,	1,	0,	"ADC16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x13000045ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #26 = ADC16rr_REV
  { 27,	1,	0,	0,	"ADC32i32", 0|(1<<TID::UnmodeledSideEffects), 0x1500a001ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #27 = ADC32i32
  { 28,	6,	0,	0,	"ADC32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100a01aULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #28 = ADC32mi
  { 29,	6,	0,	0,	"ADC32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300201aULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #29 = ADC32mi8
  { 30,	6,	0,	0,	"ADC32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x11000004ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #30 = ADC32mr
  { 31,	3,	1,	0,	"ADC32ri", 0, 0x8100a012ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #31 = ADC32ri
  { 32,	3,	1,	0,	"ADC32ri8", 0, 0x83002012ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #32 = ADC32ri8
  { 33,	7,	1,	0,	"ADC32rm", 0|(1<<TID::MayLoad), 0x13000006ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 },  // Inst #33 = ADC32rm
  { 34,	3,	1,	0,	"ADC32rr", 0|(1<<TID::Commutable), 0x11000003ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #34 = ADC32rr
  { 35,	3,	1,	0,	"ADC32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x13000005ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #35 = ADC32rr_REV
  { 36,	1,	0,	0,	"ADC64i32", 0|(1<<TID::UnmodeledSideEffects), 0x1500b001ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #36 = ADC64i32
  { 37,	6,	0,	0,	"ADC64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100b01aULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #37 = ADC64mi32
  { 38,	6,	0,	0,	"ADC64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300301aULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #38 = ADC64mi8
  { 39,	6,	0,	0,	"ADC64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x11001004ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #39 = ADC64mr
  { 40,	3,	1,	0,	"ADC64ri32", 0, 0x8100b012ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #40 = ADC64ri32
  { 41,	3,	1,	0,	"ADC64ri8", 0, 0x83003012ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #41 = ADC64ri8
  { 42,	7,	1,	0,	"ADC64rm", 0|(1<<TID::MayLoad), 0x13001006ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 },  // Inst #42 = ADC64rm
  { 43,	3,	1,	0,	"ADC64rr", 0|(1<<TID::Commutable), 0x11001003ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #43 = ADC64rr
  { 44,	3,	1,	0,	"ADC64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x13001005ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 },  // Inst #44 = ADC64rr_REV
  { 45,	1,	0,	0,	"ADC8i8", 0|(1<<TID::UnmodeledSideEffects), 0x14002001ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #45 = ADC8i8
  { 46,	6,	0,	0,	"ADC8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8000201aULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #46 = ADC8mi
  { 47,	6,	0,	0,	"ADC8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x10000004ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo24 },  // Inst #47 = ADC8mr
  { 48,	3,	1,	0,	"ADC8ri", 0, 0x80002012ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #48 = ADC8ri
  { 49,	7,	1,	0,	"ADC8rm", 0|(1<<TID::MayLoad), 0x12000006ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #49 = ADC8rm
  { 50,	3,	1,	0,	"ADC8rr", 0|(1<<TID::Commutable), 0x10000003ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #50 = ADC8rr
  { 51,	3,	1,	0,	"ADC8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x12000005ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #51 = ADC8rr_REV
  { 52,	1,	0,	0,	"ADD16i16", 0|(1<<TID::UnmodeledSideEffects), 0x5006041ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #52 = ADD16i16
  { 53,	6,	0,	0,	"ADD16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x81006058ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #53 = ADD16mi
  { 54,	6,	0,	0,	"ADD16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x83002058ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #54 = ADD16mi8
  { 55,	6,	0,	0,	"ADD16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x1000044ULL, NULL, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #55 = ADD16mr
  { 56,	3,	1,	0,	"ADD16ri", 0|(1<<TID::ConvertibleTo3Addr), 0x81006050ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #56 = ADD16ri
  { 57,	3,	1,	0,	"ADD16ri8", 0|(1<<TID::ConvertibleTo3Addr), 0x83002050ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #57 = ADD16ri8
  { 58,	7,	1,	0,	"ADD16rm", 0|(1<<TID::MayLoad), 0x3000046ULL, NULL, ImplicitList1, Barriers1, OperandInfo13 },  // Inst #58 = ADD16rm
  { 59,	3,	1,	0,	"ADD16rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0x1000043ULL, NULL, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #59 = ADD16rr
  { 60,	3,	1,	0,	"ADD16rr_alt", 0|(1<<TID::UnmodeledSideEffects), 0x3000045ULL, NULL, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #60 = ADD16rr_alt
  { 61,	1,	0,	0,	"ADD32i32", 0|(1<<TID::UnmodeledSideEffects), 0x500a001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #61 = ADD32i32
  { 62,	6,	0,	0,	"ADD32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100a018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #62 = ADD32mi
  { 63,	6,	0,	0,	"ADD32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x83002018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #63 = ADD32mi8
  { 64,	6,	0,	0,	"ADD32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x1000004ULL, NULL, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #64 = ADD32mr
  { 65,	3,	1,	0,	"ADD32ri", 0|(1<<TID::ConvertibleTo3Addr), 0x8100a010ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #65 = ADD32ri
  { 66,	3,	1,	0,	"ADD32ri8", 0|(1<<TID::ConvertibleTo3Addr), 0x83002010ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #66 = ADD32ri8
  { 67,	7,	1,	0,	"ADD32rm", 0|(1<<TID::MayLoad), 0x3000006ULL, NULL, ImplicitList1, Barriers1, OperandInfo17 },  // Inst #67 = ADD32rm
  { 68,	3,	1,	0,	"ADD32rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0x1000003ULL, NULL, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #68 = ADD32rr
  { 69,	3,	1,	0,	"ADD32rr_alt", 0|(1<<TID::UnmodeledSideEffects), 0x3000005ULL, NULL, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #69 = ADD32rr_alt
  { 70,	1,	0,	0,	"ADD64i32", 0|(1<<TID::UnmodeledSideEffects), 0x500b001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #70 = ADD64i32
  { 71,	6,	0,	0,	"ADD64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100b018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #71 = ADD64mi32
  { 72,	6,	0,	0,	"ADD64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x83003018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #72 = ADD64mi8
  { 73,	6,	0,	0,	"ADD64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x1001004ULL, NULL, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #73 = ADD64mr
  { 74,	3,	1,	0,	"ADD64ri32", 0|(1<<TID::ConvertibleTo3Addr), 0x8100b010ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #74 = ADD64ri32
  { 75,	3,	1,	0,	"ADD64ri8", 0|(1<<TID::ConvertibleTo3Addr), 0x83003010ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #75 = ADD64ri8
  { 76,	7,	1,	0,	"ADD64rm", 0|(1<<TID::MayLoad), 0x3001006ULL, NULL, ImplicitList1, Barriers1, OperandInfo21 },  // Inst #76 = ADD64rm
  { 77,	3,	1,	0,	"ADD64rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0x1001003ULL, NULL, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #77 = ADD64rr
  { 78,	3,	1,	0,	"ADD64rr_alt", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0x3001005ULL, NULL, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #78 = ADD64rr_alt
  { 79,	1,	0,	0,	"ADD8i8", 0|(1<<TID::UnmodeledSideEffects), 0x4002001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #79 = ADD8i8
  { 80,	6,	0,	0,	"ADD8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x80002018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #80 = ADD8mi
  { 81,	6,	0,	0,	"ADD8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x4ULL, NULL, ImplicitList1, Barriers1, OperandInfo24 },  // Inst #81 = ADD8mr
  { 82,	3,	1,	0,	"ADD8ri", 0, 0x80002010ULL, NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #82 = ADD8ri
  { 83,	7,	1,	0,	"ADD8rm", 0|(1<<TID::MayLoad), 0x2000006ULL, NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #83 = ADD8rm
  { 84,	3,	1,	0,	"ADD8rr", 0|(1<<TID::Commutable), 0x3ULL, NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #84 = ADD8rr
  { 85,	3,	1,	0,	"ADD8rr_alt", 0|(1<<TID::UnmodeledSideEffects), 0x2000005ULL, NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #85 = ADD8rr_alt
  { 86,	7,	1,	0,	"ADDPDrm", 0|(1<<TID::MayLoad), 0x58800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #86 = ADDPDrm
  { 87,	3,	1,	0,	"ADDPDrr", 0|(1<<TID::Commutable), 0x58800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #87 = ADDPDrr
  { 88,	7,	1,	0,	"ADDPSrm", 0|(1<<TID::MayLoad), 0x58400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #88 = ADDPSrm
  { 89,	3,	1,	0,	"ADDPSrr", 0|(1<<TID::Commutable), 0x58400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #89 = ADDPSrr
  { 90,	7,	1,	0,	"ADDSDrm", 0|(1<<TID::MayLoad), 0x58000b06ULL, NULL, NULL, NULL, OperandInfo30 },  // Inst #90 = ADDSDrm
  { 91,	7,	1,	0,	"ADDSDrm_Int", 0|(1<<TID::MayLoad), 0x58000b06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #91 = ADDSDrm_Int
  { 92,	3,	1,	0,	"ADDSDrr", 0|(1<<TID::Commutable), 0x58000b05ULL, NULL, NULL, NULL, OperandInfo31 },  // Inst #92 = ADDSDrr
  { 93,	3,	1,	0,	"ADDSDrr_Int", 0, 0x58000b05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #93 = ADDSDrr_Int
  { 94,	7,	1,	0,	"ADDSSrm", 0|(1<<TID::MayLoad), 0x58000c06ULL, NULL, NULL, NULL, OperandInfo32 },  // Inst #94 = ADDSSrm
  { 95,	7,	1,	0,	"ADDSSrm_Int", 0|(1<<TID::MayLoad), 0x58000c06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #95 = ADDSSrm_Int
  { 96,	3,	1,	0,	"ADDSSrr", 0|(1<<TID::Commutable), 0x58000c05ULL, NULL, NULL, NULL, OperandInfo33 },  // Inst #96 = ADDSSrr
  { 97,	3,	1,	0,	"ADDSSrr_Int", 0, 0x58000c05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #97 = ADDSSrr_Int
  { 98,	7,	1,	0,	"ADDSUBPDrm", 0|(1<<TID::MayLoad), 0xd0800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #98 = ADDSUBPDrm
  { 99,	3,	1,	0,	"ADDSUBPDrr", 0, 0xd0800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #99 = ADDSUBPDrr
  { 100,	7,	1,	0,	"ADDSUBPSrm", 0|(1<<TID::MayLoad), 0xd0800b06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #100 = ADDSUBPSrm
  { 101,	3,	1,	0,	"ADDSUBPSrr", 0, 0xd0800b05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #101 = ADDSUBPSrr
  { 102,	5,	0,	0,	"ADD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xd8000018ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #102 = ADD_F32m
  { 103,	5,	0,	0,	"ADD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xdc000018ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #103 = ADD_F64m
  { 104,	5,	0,	0,	"ADD_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xde000018ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #104 = ADD_FI16m
  { 105,	5,	0,	0,	"ADD_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xda000018ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #105 = ADD_FI32m
  { 106,	1,	0,	0,	"ADD_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0xc0000902ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #106 = ADD_FPrST0
  { 107,	1,	0,	0,	"ADD_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0xc0000302ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #107 = ADD_FST0r
  { 108,	3,	1,	0,	"ADD_Fp32", 0, 0x40000ULL, NULL, NULL, NULL, OperandInfo36 },  // Inst #108 = ADD_Fp32
  { 109,	7,	1,	0,	"ADD_Fp32m", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #109 = ADD_Fp32m
  { 110,	3,	1,	0,	"ADD_Fp64", 0, 0x40000ULL, NULL, NULL, NULL, OperandInfo38 },  // Inst #110 = ADD_Fp64
  { 111,	7,	1,	0,	"ADD_Fp64m", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #111 = ADD_Fp64m
  { 112,	7,	1,	0,	"ADD_Fp64m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #112 = ADD_Fp64m32
  { 113,	3,	1,	0,	"ADD_Fp80", 0, 0x40000ULL, NULL, NULL, NULL, OperandInfo40 },  // Inst #113 = ADD_Fp80
  { 114,	7,	1,	0,	"ADD_Fp80m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #114 = ADD_Fp80m32
  { 115,	7,	1,	0,	"ADD_Fp80m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #115 = ADD_Fp80m64
  { 116,	7,	1,	0,	"ADD_FpI16m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #116 = ADD_FpI16m32
  { 117,	7,	1,	0,	"ADD_FpI16m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #117 = ADD_FpI16m64
  { 118,	7,	1,	0,	"ADD_FpI16m80", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #118 = ADD_FpI16m80
  { 119,	7,	1,	0,	"ADD_FpI32m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #119 = ADD_FpI32m32
  { 120,	7,	1,	0,	"ADD_FpI32m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #120 = ADD_FpI32m64
  { 121,	7,	1,	0,	"ADD_FpI32m80", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #121 = ADD_FpI32m80
  { 122,	1,	0,	0,	"ADD_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0xc0000702ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #122 = ADD_FrST0
  { 123,	1,	0,	0,	"ADJCALLSTACKDOWN32", 0, 0x0ULL, ImplicitList2, ImplicitList3, Barriers1, OperandInfo2 },  // Inst #123 = ADJCALLSTACKDOWN32
  { 124,	1,	0,	0,	"ADJCALLSTACKDOWN64", 0, 0x0ULL, ImplicitList4, ImplicitList5, Barriers1, OperandInfo2 },  // Inst #124 = ADJCALLSTACKDOWN64
  { 125,	2,	0,	0,	"ADJCALLSTACKUP32", 0, 0x0ULL, ImplicitList2, ImplicitList3, Barriers1, OperandInfo6 },  // Inst #125 = ADJCALLSTACKUP32
  { 126,	2,	0,	0,	"ADJCALLSTACKUP64", 0, 0x0ULL, ImplicitList4, ImplicitList5, Barriers1, OperandInfo6 },  // Inst #126 = ADJCALLSTACKUP64
  { 127,	7,	1,	0,	"AESDECLASTrm", 0|(1<<TID::MayLoad), 0xdfc00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #127 = AESDECLASTrm
  { 128,	3,	1,	0,	"AESDECLASTrr", 0, 0xdfc00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #128 = AESDECLASTrr
  { 129,	7,	1,	0,	"AESDECrm", 0|(1<<TID::MayLoad), 0xdec00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #129 = AESDECrm
  { 130,	3,	1,	0,	"AESDECrr", 0, 0xdec00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #130 = AESDECrr
  { 131,	7,	1,	0,	"AESENCLASTrm", 0|(1<<TID::MayLoad), 0xddc00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #131 = AESENCLASTrm
  { 132,	3,	1,	0,	"AESENCLASTrr", 0, 0xddc00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #132 = AESENCLASTrr
  { 133,	7,	1,	0,	"AESENCrm", 0|(1<<TID::MayLoad), 0xdcc00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #133 = AESENCrm
  { 134,	3,	1,	0,	"AESENCrr", 0, 0xdcc00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #134 = AESENCrr
  { 135,	6,	1,	0,	"AESIMCrm", 0|(1<<TID::MayLoad), 0xdbc00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #135 = AESIMCrm
  { 136,	2,	1,	0,	"AESIMCrr", 0, 0xdbc00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #136 = AESIMCrr
  { 137,	7,	1,	0,	"AESKEYGENASSIST128rm", 0|(1<<TID::MayLoad), 0xdfc02e46ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #137 = AESKEYGENASSIST128rm
  { 138,	3,	1,	0,	"AESKEYGENASSIST128rr", 0, 0xdfc02e45ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #138 = AESKEYGENASSIST128rr
  { 139,	1,	0,	0,	"AND16i16", 0|(1<<TID::UnmodeledSideEffects), 0x25006041ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #139 = AND16i16
  { 140,	6,	0,	0,	"AND16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100605cULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #140 = AND16mi
  { 141,	6,	0,	0,	"AND16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300205cULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #141 = AND16mi8
  { 142,	6,	0,	0,	"AND16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x21000044ULL, NULL, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #142 = AND16mr
  { 143,	3,	1,	0,	"AND16ri", 0, 0x81006054ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #143 = AND16ri
  { 144,	3,	1,	0,	"AND16ri8", 0, 0x83002054ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #144 = AND16ri8
  { 145,	7,	1,	0,	"AND16rm", 0|(1<<TID::MayLoad), 0x23000046ULL, NULL, ImplicitList1, Barriers1, OperandInfo13 },  // Inst #145 = AND16rm
  { 146,	3,	1,	0,	"AND16rr", 0|(1<<TID::Commutable), 0x21000043ULL, NULL, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #146 = AND16rr
  { 147,	3,	1,	0,	"AND16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x23000045ULL, NULL, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #147 = AND16rr_REV
  { 148,	1,	0,	0,	"AND32i32", 0|(1<<TID::UnmodeledSideEffects), 0x2500a001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #148 = AND32i32
  { 149,	6,	0,	0,	"AND32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100a01cULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #149 = AND32mi
  { 150,	6,	0,	0,	"AND32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300201cULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #150 = AND32mi8
  { 151,	6,	0,	0,	"AND32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x21000004ULL, NULL, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #151 = AND32mr
  { 152,	3,	1,	0,	"AND32ri", 0, 0x8100a014ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #152 = AND32ri
  { 153,	3,	1,	0,	"AND32ri8", 0, 0x83002014ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #153 = AND32ri8
  { 154,	7,	1,	0,	"AND32rm", 0|(1<<TID::MayLoad), 0x23000006ULL, NULL, ImplicitList1, Barriers1, OperandInfo17 },  // Inst #154 = AND32rm
  { 155,	3,	1,	0,	"AND32rr", 0|(1<<TID::Commutable), 0x21000003ULL, NULL, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #155 = AND32rr
  { 156,	3,	1,	0,	"AND32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x23000005ULL, NULL, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #156 = AND32rr_REV
  { 157,	1,	0,	0,	"AND64i32", 0|(1<<TID::UnmodeledSideEffects), 0x2500b001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #157 = AND64i32
  { 158,	6,	0,	0,	"AND64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100b01cULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #158 = AND64mi32
  { 159,	6,	0,	0,	"AND64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300301cULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #159 = AND64mi8
  { 160,	6,	0,	0,	"AND64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x21001004ULL, NULL, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #160 = AND64mr
  { 161,	3,	1,	0,	"AND64ri32", 0, 0x8100b014ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #161 = AND64ri32
  { 162,	3,	1,	0,	"AND64ri8", 0, 0x83003014ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #162 = AND64ri8
  { 163,	7,	1,	0,	"AND64rm", 0|(1<<TID::MayLoad), 0x23001006ULL, NULL, ImplicitList1, Barriers1, OperandInfo21 },  // Inst #163 = AND64rm
  { 164,	3,	1,	0,	"AND64rr", 0|(1<<TID::Commutable), 0x21001003ULL, NULL, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #164 = AND64rr
  { 165,	3,	1,	0,	"AND64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x23001005ULL, NULL, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #165 = AND64rr_REV
  { 166,	1,	0,	0,	"AND8i8", 0|(1<<TID::UnmodeledSideEffects), 0x24002001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #166 = AND8i8
  { 167,	6,	0,	0,	"AND8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8000201cULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #167 = AND8mi
  { 168,	6,	0,	0,	"AND8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x20000004ULL, NULL, ImplicitList1, Barriers1, OperandInfo24 },  // Inst #168 = AND8mr
  { 169,	3,	1,	0,	"AND8ri", 0, 0x80002014ULL, NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #169 = AND8ri
  { 170,	7,	1,	0,	"AND8rm", 0|(1<<TID::MayLoad), 0x22000006ULL, NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #170 = AND8rm
  { 171,	3,	1,	0,	"AND8rr", 0|(1<<TID::Commutable), 0x20000003ULL, NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #171 = AND8rr
  { 172,	3,	1,	0,	"AND8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x22000005ULL, NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #172 = AND8rr_REV
  { 173,	7,	1,	0,	"ANDNPDrm", 0|(1<<TID::MayLoad), 0x55800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #173 = ANDNPDrm
  { 174,	3,	1,	0,	"ANDNPDrr", 0, 0x55800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #174 = ANDNPDrr
  { 175,	7,	1,	0,	"ANDNPSrm", 0|(1<<TID::MayLoad), 0x55400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #175 = ANDNPSrm
  { 176,	3,	1,	0,	"ANDNPSrr", 0, 0x55400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #176 = ANDNPSrr
  { 177,	7,	1,	0,	"ANDPDrm", 0|(1<<TID::MayLoad), 0x54800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #177 = ANDPDrm
  { 178,	3,	1,	0,	"ANDPDrr", 0|(1<<TID::Commutable), 0x54800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #178 = ANDPDrr
  { 179,	7,	1,	0,	"ANDPSrm", 0|(1<<TID::MayLoad), 0x54400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #179 = ANDPSrm
  { 180,	3,	1,	0,	"ANDPSrr", 0|(1<<TID::Commutable), 0x54400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #180 = ANDPSrr
  { 181,	9,	2,	0,	"ATOMADD6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, ImplicitList7, Barriers2, OperandInfo46 },  // Inst #181 = ATOMADD6432
  { 182,	7,	1,	0,	"ATOMAND16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo47 },  // Inst #182 = ATOMAND16
  { 183,	7,	1,	0,	"ATOMAND32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo48 },  // Inst #183 = ATOMAND32
  { 184,	7,	1,	0,	"ATOMAND64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo49 },  // Inst #184 = ATOMAND64
  { 185,	9,	2,	0,	"ATOMAND6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, ImplicitList7, Barriers2, OperandInfo46 },  // Inst #185 = ATOMAND6432
  { 186,	7,	1,	0,	"ATOMAND8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo50 },  // Inst #186 = ATOMAND8
  { 187,	7,	1,	0,	"ATOMMAX16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo47 },  // Inst #187 = ATOMMAX16
  { 188,	7,	1,	0,	"ATOMMAX32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo48 },  // Inst #188 = ATOMMAX32
  { 189,	7,	1,	0,	"ATOMMAX64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo49 },  // Inst #189 = ATOMMAX64
  { 190,	7,	1,	0,	"ATOMMIN16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo47 },  // Inst #190 = ATOMMIN16
  { 191,	7,	1,	0,	"ATOMMIN32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo48 },  // Inst #191 = ATOMMIN32
  { 192,	7,	1,	0,	"ATOMMIN64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo49 },  // Inst #192 = ATOMMIN64
  { 193,	7,	1,	0,	"ATOMNAND16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo47 },  // Inst #193 = ATOMNAND16
  { 194,	7,	1,	0,	"ATOMNAND32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo48 },  // Inst #194 = ATOMNAND32
  { 195,	7,	1,	0,	"ATOMNAND64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo49 },  // Inst #195 = ATOMNAND64
  { 196,	9,	2,	0,	"ATOMNAND6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, ImplicitList7, Barriers2, OperandInfo46 },  // Inst #196 = ATOMNAND6432
  { 197,	7,	1,	0,	"ATOMNAND8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo50 },  // Inst #197 = ATOMNAND8
  { 198,	7,	1,	0,	"ATOMOR16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo47 },  // Inst #198 = ATOMOR16
  { 199,	7,	1,	0,	"ATOMOR32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo48 },  // Inst #199 = ATOMOR32
  { 200,	7,	1,	0,	"ATOMOR64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo49 },  // Inst #200 = ATOMOR64
  { 201,	9,	2,	0,	"ATOMOR6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, ImplicitList7, Barriers2, OperandInfo46 },  // Inst #201 = ATOMOR6432
  { 202,	7,	1,	0,	"ATOMOR8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo50 },  // Inst #202 = ATOMOR8
  { 203,	9,	2,	0,	"ATOMSUB6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, ImplicitList7, Barriers2, OperandInfo46 },  // Inst #203 = ATOMSUB6432
  { 204,	9,	2,	0,	"ATOMSWAP6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, ImplicitList7, Barriers2, OperandInfo46 },  // Inst #204 = ATOMSWAP6432
  { 205,	7,	1,	0,	"ATOMUMAX16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo47 },  // Inst #205 = ATOMUMAX16
  { 206,	7,	1,	0,	"ATOMUMAX32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo48 },  // Inst #206 = ATOMUMAX32
  { 207,	7,	1,	0,	"ATOMUMAX64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo49 },  // Inst #207 = ATOMUMAX64
  { 208,	7,	1,	0,	"ATOMUMIN16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo47 },  // Inst #208 = ATOMUMIN16
  { 209,	7,	1,	0,	"ATOMUMIN32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo48 },  // Inst #209 = ATOMUMIN32
  { 210,	7,	1,	0,	"ATOMUMIN64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo49 },  // Inst #210 = ATOMUMIN64
  { 211,	7,	1,	0,	"ATOMXOR16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo47 },  // Inst #211 = ATOMXOR16
  { 212,	7,	1,	0,	"ATOMXOR32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo48 },  // Inst #212 = ATOMXOR32
  { 213,	7,	1,	0,	"ATOMXOR64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo49 },  // Inst #213 = ATOMXOR64
  { 214,	9,	2,	0,	"ATOMXOR6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, ImplicitList7, Barriers2, OperandInfo46 },  // Inst #214 = ATOMXOR6432
  { 215,	7,	1,	0,	"ATOMXOR8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, Barriers1, OperandInfo50 },  // Inst #215 = ATOMXOR8
  { 216,	1,	1,	0,	"AVX_SET0PD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0x557800160ULL, NULL, NULL, NULL, OperandInfo51 },  // Inst #216 = AVX_SET0PD
  { 217,	1,	1,	0,	"AVX_SET0PDY", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0x557800160ULL, NULL, NULL, NULL, OperandInfo52 },  // Inst #217 = AVX_SET0PDY
  { 218,	1,	1,	0,	"AVX_SET0PI", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0xefc00160ULL, NULL, NULL, NULL, OperandInfo51 },  // Inst #218 = AVX_SET0PI
  { 219,	1,	1,	0,	"AVX_SET0PS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0x557400120ULL, NULL, NULL, NULL, OperandInfo51 },  // Inst #219 = AVX_SET0PS
  { 220,	1,	1,	0,	"AVX_SET0PSY", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0x557400120ULL, NULL, NULL, NULL, OperandInfo52 },  // Inst #220 = AVX_SET0PSY
  { 221,	8,	1,	0,	"BLENDPDrmi", 0|(1<<TID::MayLoad), 0xdc02e46ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #221 = BLENDPDrmi
  { 222,	4,	1,	0,	"BLENDPDrri", 0, 0xdc02e45ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #222 = BLENDPDrri
  { 223,	8,	1,	0,	"BLENDPSrmi", 0|(1<<TID::MayLoad), 0xcc02e46ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #223 = BLENDPSrmi
  { 224,	4,	1,	0,	"BLENDPSrri", 0, 0xcc02e45ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #224 = BLENDPSrri
  { 225,	7,	1,	0,	"BLENDVPDrm0", 0|(1<<TID::MayLoad), 0x15c00d46ULL, ImplicitList8, NULL, NULL, OperandInfo28 },  // Inst #225 = BLENDVPDrm0
  { 226,	3,	1,	0,	"BLENDVPDrr0", 0, 0x15c00d45ULL, ImplicitList8, NULL, NULL, OperandInfo29 },  // Inst #226 = BLENDVPDrr0
  { 227,	7,	1,	0,	"BLENDVPSrm0", 0|(1<<TID::MayLoad), 0x14c00d46ULL, ImplicitList8, NULL, NULL, OperandInfo28 },  // Inst #227 = BLENDVPSrm0
  { 228,	3,	1,	0,	"BLENDVPSrr0", 0, 0x14c00d45ULL, ImplicitList8, NULL, NULL, OperandInfo29 },  // Inst #228 = BLENDVPSrr0
  { 229,	6,	1,	0,	"BSF16rm", 0|(1<<TID::MayLoad), 0xbc000146ULL, NULL, ImplicitList1, Barriers1, OperandInfo55 },  // Inst #229 = BSF16rm
  { 230,	2,	1,	0,	"BSF16rr", 0, 0xbc000145ULL, NULL, ImplicitList1, Barriers1, OperandInfo56 },  // Inst #230 = BSF16rr
  { 231,	6,	1,	0,	"BSF32rm", 0|(1<<TID::MayLoad), 0xbc000106ULL, NULL, ImplicitList1, Barriers1, OperandInfo57 },  // Inst #231 = BSF32rm
  { 232,	2,	1,	0,	"BSF32rr", 0, 0xbc000105ULL, NULL, ImplicitList1, Barriers1, OperandInfo58 },  // Inst #232 = BSF32rr
  { 233,	6,	1,	0,	"BSF64rm", 0|(1<<TID::MayLoad), 0xbc001106ULL, NULL, ImplicitList1, Barriers1, OperandInfo59 },  // Inst #233 = BSF64rm
  { 234,	2,	1,	0,	"BSF64rr", 0, 0xbc001105ULL, NULL, ImplicitList1, Barriers1, OperandInfo60 },  // Inst #234 = BSF64rr
  { 235,	6,	1,	0,	"BSR16rm", 0|(1<<TID::MayLoad), 0xbd000146ULL, NULL, ImplicitList1, Barriers1, OperandInfo55 },  // Inst #235 = BSR16rm
  { 236,	2,	1,	0,	"BSR16rr", 0, 0xbd000145ULL, NULL, ImplicitList1, Barriers1, OperandInfo56 },  // Inst #236 = BSR16rr
  { 237,	6,	1,	0,	"BSR32rm", 0|(1<<TID::MayLoad), 0xbd000106ULL, NULL, ImplicitList1, Barriers1, OperandInfo57 },  // Inst #237 = BSR32rm
  { 238,	2,	1,	0,	"BSR32rr", 0, 0xbd000105ULL, NULL, ImplicitList1, Barriers1, OperandInfo58 },  // Inst #238 = BSR32rr
  { 239,	6,	1,	0,	"BSR64rm", 0|(1<<TID::MayLoad), 0xbd001106ULL, NULL, ImplicitList1, Barriers1, OperandInfo59 },  // Inst #239 = BSR64rm
  { 240,	2,	1,	0,	"BSR64rr", 0, 0xbd001105ULL, NULL, ImplicitList1, Barriers1, OperandInfo60 },  // Inst #240 = BSR64rr
  { 241,	2,	1,	0,	"BSWAP32r", 0, 0xc8000102ULL, ImplicitList1, NULL, NULL, OperandInfo61 },  // Inst #241 = BSWAP32r
  { 242,	2,	1,	0,	"BSWAP64r", 0, 0xc8001102ULL, NULL, NULL, NULL, OperandInfo62 },  // Inst #242 = BSWAP64r
  { 243,	6,	0,	0,	"BT16mi8", 0|(1<<TID::MayLoad), 0xba00215cULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #243 = BT16mi8
  { 244,	6,	0,	0,	"BT16mr", 0|(1<<TID::UnmodeledSideEffects), 0xa3000144ULL, NULL, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #244 = BT16mr
  { 245,	2,	0,	0,	"BT16ri8", 0, 0xba002154ULL, NULL, ImplicitList1, Barriers1, OperandInfo63 },  // Inst #245 = BT16ri8
  { 246,	2,	0,	0,	"BT16rr", 0, 0xa3000143ULL, NULL, ImplicitList1, Barriers1, OperandInfo56 },  // Inst #246 = BT16rr
  { 247,	6,	0,	0,	"BT32mi8", 0|(1<<TID::MayLoad), 0xba00211cULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #247 = BT32mi8
  { 248,	6,	0,	0,	"BT32mr", 0|(1<<TID::UnmodeledSideEffects), 0xa3000104ULL, NULL, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #248 = BT32mr
  { 249,	2,	0,	0,	"BT32ri8", 0, 0xba002114ULL, NULL, ImplicitList1, Barriers1, OperandInfo64 },  // Inst #249 = BT32ri8
  { 250,	2,	0,	0,	"BT32rr", 0, 0xa3000103ULL, NULL, ImplicitList1, Barriers1, OperandInfo58 },  // Inst #250 = BT32rr
  { 251,	6,	0,	0,	"BT64mi8", 0|(1<<TID::MayLoad), 0xba00311cULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #251 = BT64mi8
  { 252,	6,	0,	0,	"BT64mr", 0|(1<<TID::UnmodeledSideEffects), 0xa3001104ULL, NULL, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #252 = BT64mr
  { 253,	2,	0,	0,	"BT64ri8", 0, 0xba003114ULL, NULL, ImplicitList1, Barriers1, OperandInfo65 },  // Inst #253 = BT64ri8
  { 254,	2,	0,	0,	"BT64rr", 0, 0xa3001103ULL, NULL, ImplicitList1, Barriers1, OperandInfo60 },  // Inst #254 = BT64rr
  { 255,	6,	0,	0,	"BTC16mi8", 0|(1<<TID::UnmodeledSideEffects), 0xba00215fULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #255 = BTC16mi8
  { 256,	6,	0,	0,	"BTC16mr", 0|(1<<TID::UnmodeledSideEffects), 0xbb000144ULL, NULL, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #256 = BTC16mr
  { 257,	2,	0,	0,	"BTC16ri8", 0|(1<<TID::UnmodeledSideEffects), 0xba002157ULL, NULL, ImplicitList1, Barriers1, OperandInfo63 },  // Inst #257 = BTC16ri8
  { 258,	2,	0,	0,	"BTC16rr", 0|(1<<TID::UnmodeledSideEffects), 0xbb000143ULL, NULL, ImplicitList1, Barriers1, OperandInfo56 },  // Inst #258 = BTC16rr
  { 259,	6,	0,	0,	"BTC32mi8", 0|(1<<TID::UnmodeledSideEffects), 0xba00211fULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #259 = BTC32mi8
  { 260,	6,	0,	0,	"BTC32mr", 0|(1<<TID::UnmodeledSideEffects), 0xbb000104ULL, NULL, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #260 = BTC32mr
  { 261,	2,	0,	0,	"BTC32ri8", 0|(1<<TID::UnmodeledSideEffects), 0xba002117ULL, NULL, ImplicitList1, Barriers1, OperandInfo64 },  // Inst #261 = BTC32ri8
  { 262,	2,	0,	0,	"BTC32rr", 0|(1<<TID::UnmodeledSideEffects), 0xbb000103ULL, NULL, ImplicitList1, Barriers1, OperandInfo58 },  // Inst #262 = BTC32rr
  { 263,	6,	0,	0,	"BTC64mi8", 0|(1<<TID::UnmodeledSideEffects), 0xba00311fULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #263 = BTC64mi8
  { 264,	6,	0,	0,	"BTC64mr", 0|(1<<TID::UnmodeledSideEffects), 0xbb001104ULL, NULL, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #264 = BTC64mr
  { 265,	2,	0,	0,	"BTC64ri8", 0|(1<<TID::UnmodeledSideEffects), 0xba003117ULL, NULL, ImplicitList1, Barriers1, OperandInfo65 },  // Inst #265 = BTC64ri8
  { 266,	2,	0,	0,	"BTC64rr", 0|(1<<TID::UnmodeledSideEffects), 0xbb001103ULL, NULL, ImplicitList1, Barriers1, OperandInfo60 },  // Inst #266 = BTC64rr
  { 267,	6,	0,	0,	"BTR16mi8", 0|(1<<TID::UnmodeledSideEffects), 0xba00215eULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #267 = BTR16mi8
  { 268,	6,	0,	0,	"BTR16mr", 0|(1<<TID::UnmodeledSideEffects), 0xb3000144ULL, NULL, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #268 = BTR16mr
  { 269,	2,	0,	0,	"BTR16ri8", 0|(1<<TID::UnmodeledSideEffects), 0xba002156ULL, NULL, ImplicitList1, Barriers1, OperandInfo63 },  // Inst #269 = BTR16ri8
  { 270,	2,	0,	0,	"BTR16rr", 0|(1<<TID::UnmodeledSideEffects), 0xb3000143ULL, NULL, ImplicitList1, Barriers1, OperandInfo56 },  // Inst #270 = BTR16rr
  { 271,	6,	0,	0,	"BTR32mi8", 0|(1<<TID::UnmodeledSideEffects), 0xba00211eULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #271 = BTR32mi8
  { 272,	6,	0,	0,	"BTR32mr", 0|(1<<TID::UnmodeledSideEffects), 0xb3000104ULL, NULL, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #272 = BTR32mr
  { 273,	2,	0,	0,	"BTR32ri8", 0|(1<<TID::UnmodeledSideEffects), 0xba002116ULL, NULL, ImplicitList1, Barriers1, OperandInfo64 },  // Inst #273 = BTR32ri8
  { 274,	2,	0,	0,	"BTR32rr", 0|(1<<TID::UnmodeledSideEffects), 0xb3000103ULL, NULL, ImplicitList1, Barriers1, OperandInfo58 },  // Inst #274 = BTR32rr
  { 275,	6,	0,	0,	"BTR64mi8", 0|(1<<TID::UnmodeledSideEffects), 0xba00311eULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #275 = BTR64mi8
  { 276,	6,	0,	0,	"BTR64mr", 0|(1<<TID::UnmodeledSideEffects), 0xb3001104ULL, NULL, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #276 = BTR64mr
  { 277,	2,	0,	0,	"BTR64ri8", 0|(1<<TID::UnmodeledSideEffects), 0xba003116ULL, NULL, ImplicitList1, Barriers1, OperandInfo65 },  // Inst #277 = BTR64ri8
  { 278,	2,	0,	0,	"BTR64rr", 0|(1<<TID::UnmodeledSideEffects), 0xb3001103ULL, NULL, ImplicitList1, Barriers1, OperandInfo60 },  // Inst #278 = BTR64rr
  { 279,	6,	0,	0,	"BTS16mi8", 0|(1<<TID::UnmodeledSideEffects), 0xba00215dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #279 = BTS16mi8
  { 280,	6,	0,	0,	"BTS16mr", 0|(1<<TID::UnmodeledSideEffects), 0xab000144ULL, NULL, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #280 = BTS16mr
  { 281,	2,	0,	0,	"BTS16ri8", 0|(1<<TID::UnmodeledSideEffects), 0xba002155ULL, NULL, ImplicitList1, Barriers1, OperandInfo63 },  // Inst #281 = BTS16ri8
  { 282,	2,	0,	0,	"BTS16rr", 0|(1<<TID::UnmodeledSideEffects), 0xab000143ULL, NULL, ImplicitList1, Barriers1, OperandInfo56 },  // Inst #282 = BTS16rr
  { 283,	6,	0,	0,	"BTS32mi8", 0|(1<<TID::UnmodeledSideEffects), 0xba00211dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #283 = BTS32mi8
  { 284,	6,	0,	0,	"BTS32mr", 0|(1<<TID::UnmodeledSideEffects), 0xab000104ULL, NULL, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #284 = BTS32mr
  { 285,	2,	0,	0,	"BTS32ri8", 0|(1<<TID::UnmodeledSideEffects), 0xba002115ULL, NULL, ImplicitList1, Barriers1, OperandInfo64 },  // Inst #285 = BTS32ri8
  { 286,	2,	0,	0,	"BTS32rr", 0|(1<<TID::UnmodeledSideEffects), 0xab000103ULL, NULL, ImplicitList1, Barriers1, OperandInfo58 },  // Inst #286 = BTS32rr
  { 287,	6,	0,	0,	"BTS64mi8", 0|(1<<TID::UnmodeledSideEffects), 0xba00311dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #287 = BTS64mi8
  { 288,	6,	0,	0,	"BTS64mr", 0|(1<<TID::UnmodeledSideEffects), 0xab001104ULL, NULL, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #288 = BTS64mr
  { 289,	2,	0,	0,	"BTS64ri8", 0|(1<<TID::UnmodeledSideEffects), 0xba003115ULL, NULL, ImplicitList1, Barriers1, OperandInfo65 },  // Inst #289 = BTS64ri8
  { 290,	2,	0,	0,	"BTS64rr", 0|(1<<TID::UnmodeledSideEffects), 0xab001103ULL, NULL, ImplicitList1, Barriers1, OperandInfo60 },  // Inst #290 = BTS64rr
  { 291,	5,	0,	0,	"CALL32m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0xff00001aULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo34 },  // Inst #291 = CALL32m
  { 292,	1,	0,	0,	"CALL32r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0xff000012ULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo66 },  // Inst #292 = CALL32r
  { 293,	5,	0,	0,	"CALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0xff00001aULL, ImplicitList4, ImplicitList10, Barriers4, OperandInfo34 },  // Inst #293 = CALL64m
  { 294,	1,	0,	0,	"CALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0xe800c001ULL, ImplicitList4, ImplicitList10, Barriers4, OperandInfo2 },  // Inst #294 = CALL64pcrel32
  { 295,	1,	0,	0,	"CALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0xff000012ULL, ImplicitList4, ImplicitList10, Barriers4, OperandInfo67 },  // Inst #295 = CALL64r
  { 296,	1,	0,	0,	"CALLpcrel16", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0xe8008041ULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo2 },  // Inst #296 = CALLpcrel16
  { 297,	1,	0,	0,	"CALLpcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0xe800c001ULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo2 },  // Inst #297 = CALLpcrel32
  { 298,	0,	0,	0,	"CBW", 0, 0x98000041ULL, ImplicitList11, ImplicitList12, NULL, 0 },  // Inst #298 = CBW
  { 299,	0,	0,	0,	"CDQ", 0, 0x99000001ULL, ImplicitList13, ImplicitList14, Barriers5, 0 },  // Inst #299 = CDQ
  { 300,	0,	0,	0,	"CDQE", 0, 0x98001001ULL, ImplicitList13, ImplicitList15, NULL, 0 },  // Inst #300 = CDQE
  { 301,	0,	0,	0,	"CHS_F", 0|(1<<TID::UnmodeledSideEffects), 0xe0000401ULL, NULL, NULL, NULL, 0 },  // Inst #301 = CHS_F
  { 302,	2,	1,	0,	"CHS_Fp32", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo7 },  // Inst #302 = CHS_Fp32
  { 303,	2,	1,	0,	"CHS_Fp64", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo8 },  // Inst #303 = CHS_Fp64
  { 304,	2,	1,	0,	"CHS_Fp80", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo9 },  // Inst #304 = CHS_Fp80
  { 305,	0,	0,	0,	"CLC", 0|(1<<TID::UnmodeledSideEffects), 0xf8000001ULL, NULL, NULL, NULL, 0 },  // Inst #305 = CLC
  { 306,	0,	0,	0,	"CLD", 0|(1<<TID::UnmodeledSideEffects), 0xfc000001ULL, NULL, NULL, NULL, 0 },  // Inst #306 = CLD
  { 307,	5,	0,	0,	"CLFLUSH", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xae00011fULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #307 = CLFLUSH
  { 308,	0,	0,	0,	"CLI", 0|(1<<TID::UnmodeledSideEffects), 0xfa000001ULL, NULL, NULL, NULL, 0 },  // Inst #308 = CLI
  { 309,	0,	0,	0,	"CLTS", 0|(1<<TID::UnmodeledSideEffects), 0x6000101ULL, NULL, NULL, NULL, 0 },  // Inst #309 = CLTS
  { 310,	0,	0,	0,	"CMC", 0|(1<<TID::UnmodeledSideEffects), 0xf5000001ULL, NULL, NULL, NULL, 0 },  // Inst #310 = CMC
  { 311,	7,	1,	0,	"CMOVA16rm", 0|(1<<TID::MayLoad), 0x47000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #311 = CMOVA16rm
  { 312,	3,	1,	0,	"CMOVA16rr", 0|(1<<TID::Commutable), 0x47000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #312 = CMOVA16rr
  { 313,	7,	1,	0,	"CMOVA32rm", 0|(1<<TID::MayLoad), 0x47000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #313 = CMOVA32rm
  { 314,	3,	1,	0,	"CMOVA32rr", 0|(1<<TID::Commutable), 0x47000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #314 = CMOVA32rr
  { 315,	7,	1,	0,	"CMOVA64rm", 0|(1<<TID::MayLoad), 0x47001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #315 = CMOVA64rm
  { 316,	3,	1,	0,	"CMOVA64rr", 0|(1<<TID::Commutable), 0x47001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #316 = CMOVA64rr
  { 317,	7,	1,	0,	"CMOVAE16rm", 0|(1<<TID::MayLoad), 0x43000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #317 = CMOVAE16rm
  { 318,	3,	1,	0,	"CMOVAE16rr", 0|(1<<TID::Commutable), 0x43000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #318 = CMOVAE16rr
  { 319,	7,	1,	0,	"CMOVAE32rm", 0|(1<<TID::MayLoad), 0x43000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #319 = CMOVAE32rm
  { 320,	3,	1,	0,	"CMOVAE32rr", 0|(1<<TID::Commutable), 0x43000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #320 = CMOVAE32rr
  { 321,	7,	1,	0,	"CMOVAE64rm", 0|(1<<TID::MayLoad), 0x43001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #321 = CMOVAE64rm
  { 322,	3,	1,	0,	"CMOVAE64rr", 0|(1<<TID::Commutable), 0x43001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #322 = CMOVAE64rr
  { 323,	7,	1,	0,	"CMOVB16rm", 0|(1<<TID::MayLoad), 0x42000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #323 = CMOVB16rm
  { 324,	3,	1,	0,	"CMOVB16rr", 0|(1<<TID::Commutable), 0x42000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #324 = CMOVB16rr
  { 325,	7,	1,	0,	"CMOVB32rm", 0|(1<<TID::MayLoad), 0x42000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #325 = CMOVB32rm
  { 326,	3,	1,	0,	"CMOVB32rr", 0|(1<<TID::Commutable), 0x42000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #326 = CMOVB32rr
  { 327,	7,	1,	0,	"CMOVB64rm", 0|(1<<TID::MayLoad), 0x42001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #327 = CMOVB64rm
  { 328,	3,	1,	0,	"CMOVB64rr", 0|(1<<TID::Commutable), 0x42001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #328 = CMOVB64rr
  { 329,	7,	1,	0,	"CMOVBE16rm", 0|(1<<TID::MayLoad), 0x46000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #329 = CMOVBE16rm
  { 330,	3,	1,	0,	"CMOVBE16rr", 0|(1<<TID::Commutable), 0x46000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #330 = CMOVBE16rr
  { 331,	7,	1,	0,	"CMOVBE32rm", 0|(1<<TID::MayLoad), 0x46000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #331 = CMOVBE32rm
  { 332,	3,	1,	0,	"CMOVBE32rr", 0|(1<<TID::Commutable), 0x46000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #332 = CMOVBE32rr
  { 333,	7,	1,	0,	"CMOVBE64rm", 0|(1<<TID::MayLoad), 0x46001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #333 = CMOVBE64rm
  { 334,	3,	1,	0,	"CMOVBE64rr", 0|(1<<TID::Commutable), 0x46001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #334 = CMOVBE64rr
  { 335,	1,	1,	0,	"CMOVBE_F", 0|(1<<TID::UnmodeledSideEffects), 0xd0000502ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #335 = CMOVBE_F
  { 336,	3,	1,	0,	"CMOVBE_Fp32", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo68 },  // Inst #336 = CMOVBE_Fp32
  { 337,	3,	1,	0,	"CMOVBE_Fp64", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo69 },  // Inst #337 = CMOVBE_Fp64
  { 338,	3,	1,	0,	"CMOVBE_Fp80", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo70 },  // Inst #338 = CMOVBE_Fp80
  { 339,	1,	1,	0,	"CMOVB_F", 0|(1<<TID::UnmodeledSideEffects), 0xc0000502ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #339 = CMOVB_F
  { 340,	3,	1,	0,	"CMOVB_Fp32", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo68 },  // Inst #340 = CMOVB_Fp32
  { 341,	3,	1,	0,	"CMOVB_Fp64", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo69 },  // Inst #341 = CMOVB_Fp64
  { 342,	3,	1,	0,	"CMOVB_Fp80", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo70 },  // Inst #342 = CMOVB_Fp80
  { 343,	7,	1,	0,	"CMOVE16rm", 0|(1<<TID::MayLoad), 0x44000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #343 = CMOVE16rm
  { 344,	3,	1,	0,	"CMOVE16rr", 0|(1<<TID::Commutable), 0x44000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #344 = CMOVE16rr
  { 345,	7,	1,	0,	"CMOVE32rm", 0|(1<<TID::MayLoad), 0x44000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #345 = CMOVE32rm
  { 346,	3,	1,	0,	"CMOVE32rr", 0|(1<<TID::Commutable), 0x44000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #346 = CMOVE32rr
  { 347,	7,	1,	0,	"CMOVE64rm", 0|(1<<TID::MayLoad), 0x44001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #347 = CMOVE64rm
  { 348,	3,	1,	0,	"CMOVE64rr", 0|(1<<TID::Commutable), 0x44001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #348 = CMOVE64rr
  { 349,	1,	1,	0,	"CMOVE_F", 0|(1<<TID::UnmodeledSideEffects), 0xc8000502ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #349 = CMOVE_F
  { 350,	3,	1,	0,	"CMOVE_Fp32", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo68 },  // Inst #350 = CMOVE_Fp32
  { 351,	3,	1,	0,	"CMOVE_Fp64", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo69 },  // Inst #351 = CMOVE_Fp64
  { 352,	3,	1,	0,	"CMOVE_Fp80", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo70 },  // Inst #352 = CMOVE_Fp80
  { 353,	7,	1,	0,	"CMOVG16rm", 0|(1<<TID::MayLoad), 0x4f000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #353 = CMOVG16rm
  { 354,	3,	1,	0,	"CMOVG16rr", 0|(1<<TID::Commutable), 0x4f000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #354 = CMOVG16rr
  { 355,	7,	1,	0,	"CMOVG32rm", 0|(1<<TID::MayLoad), 0x4f000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #355 = CMOVG32rm
  { 356,	3,	1,	0,	"CMOVG32rr", 0|(1<<TID::Commutable), 0x4f000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #356 = CMOVG32rr
  { 357,	7,	1,	0,	"CMOVG64rm", 0|(1<<TID::MayLoad), 0x4f001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #357 = CMOVG64rm
  { 358,	3,	1,	0,	"CMOVG64rr", 0|(1<<TID::Commutable), 0x4f001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #358 = CMOVG64rr
  { 359,	7,	1,	0,	"CMOVGE16rm", 0|(1<<TID::MayLoad), 0x4d000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #359 = CMOVGE16rm
  { 360,	3,	1,	0,	"CMOVGE16rr", 0|(1<<TID::Commutable), 0x4d000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #360 = CMOVGE16rr
  { 361,	7,	1,	0,	"CMOVGE32rm", 0|(1<<TID::MayLoad), 0x4d000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #361 = CMOVGE32rm
  { 362,	3,	1,	0,	"CMOVGE32rr", 0|(1<<TID::Commutable), 0x4d000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #362 = CMOVGE32rr
  { 363,	7,	1,	0,	"CMOVGE64rm", 0|(1<<TID::MayLoad), 0x4d001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #363 = CMOVGE64rm
  { 364,	3,	1,	0,	"CMOVGE64rr", 0|(1<<TID::Commutable), 0x4d001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #364 = CMOVGE64rr
  { 365,	7,	1,	0,	"CMOVL16rm", 0|(1<<TID::MayLoad), 0x4c000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #365 = CMOVL16rm
  { 366,	3,	1,	0,	"CMOVL16rr", 0|(1<<TID::Commutable), 0x4c000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #366 = CMOVL16rr
  { 367,	7,	1,	0,	"CMOVL32rm", 0|(1<<TID::MayLoad), 0x4c000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #367 = CMOVL32rm
  { 368,	3,	1,	0,	"CMOVL32rr", 0|(1<<TID::Commutable), 0x4c000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #368 = CMOVL32rr
  { 369,	7,	1,	0,	"CMOVL64rm", 0|(1<<TID::MayLoad), 0x4c001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #369 = CMOVL64rm
  { 370,	3,	1,	0,	"CMOVL64rr", 0|(1<<TID::Commutable), 0x4c001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #370 = CMOVL64rr
  { 371,	7,	1,	0,	"CMOVLE16rm", 0|(1<<TID::MayLoad), 0x4e000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #371 = CMOVLE16rm
  { 372,	3,	1,	0,	"CMOVLE16rr", 0|(1<<TID::Commutable), 0x4e000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #372 = CMOVLE16rr
  { 373,	7,	1,	0,	"CMOVLE32rm", 0|(1<<TID::MayLoad), 0x4e000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #373 = CMOVLE32rm
  { 374,	3,	1,	0,	"CMOVLE32rr", 0|(1<<TID::Commutable), 0x4e000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #374 = CMOVLE32rr
  { 375,	7,	1,	0,	"CMOVLE64rm", 0|(1<<TID::MayLoad), 0x4e001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #375 = CMOVLE64rm
  { 376,	3,	1,	0,	"CMOVLE64rr", 0|(1<<TID::Commutable), 0x4e001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #376 = CMOVLE64rr
  { 377,	1,	1,	0,	"CMOVNBE_F", 0|(1<<TID::UnmodeledSideEffects), 0xd0000602ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #377 = CMOVNBE_F
  { 378,	3,	1,	0,	"CMOVNBE_Fp32", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo68 },  // Inst #378 = CMOVNBE_Fp32
  { 379,	3,	1,	0,	"CMOVNBE_Fp64", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo69 },  // Inst #379 = CMOVNBE_Fp64
  { 380,	3,	1,	0,	"CMOVNBE_Fp80", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo70 },  // Inst #380 = CMOVNBE_Fp80
  { 381,	1,	1,	0,	"CMOVNB_F", 0|(1<<TID::UnmodeledSideEffects), 0xc0000602ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #381 = CMOVNB_F
  { 382,	3,	1,	0,	"CMOVNB_Fp32", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo68 },  // Inst #382 = CMOVNB_Fp32
  { 383,	3,	1,	0,	"CMOVNB_Fp64", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo69 },  // Inst #383 = CMOVNB_Fp64
  { 384,	3,	1,	0,	"CMOVNB_Fp80", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo70 },  // Inst #384 = CMOVNB_Fp80
  { 385,	7,	1,	0,	"CMOVNE16rm", 0|(1<<TID::MayLoad), 0x45000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #385 = CMOVNE16rm
  { 386,	3,	1,	0,	"CMOVNE16rr", 0|(1<<TID::Commutable), 0x45000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #386 = CMOVNE16rr
  { 387,	7,	1,	0,	"CMOVNE32rm", 0|(1<<TID::MayLoad), 0x45000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #387 = CMOVNE32rm
  { 388,	3,	1,	0,	"CMOVNE32rr", 0|(1<<TID::Commutable), 0x45000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #388 = CMOVNE32rr
  { 389,	7,	1,	0,	"CMOVNE64rm", 0|(1<<TID::MayLoad), 0x45001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #389 = CMOVNE64rm
  { 390,	3,	1,	0,	"CMOVNE64rr", 0|(1<<TID::Commutable), 0x45001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #390 = CMOVNE64rr
  { 391,	1,	1,	0,	"CMOVNE_F", 0|(1<<TID::UnmodeledSideEffects), 0xc8000602ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #391 = CMOVNE_F
  { 392,	3,	1,	0,	"CMOVNE_Fp32", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo68 },  // Inst #392 = CMOVNE_Fp32
  { 393,	3,	1,	0,	"CMOVNE_Fp64", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo69 },  // Inst #393 = CMOVNE_Fp64
  { 394,	3,	1,	0,	"CMOVNE_Fp80", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo70 },  // Inst #394 = CMOVNE_Fp80
  { 395,	7,	1,	0,	"CMOVNO16rm", 0|(1<<TID::MayLoad), 0x41000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #395 = CMOVNO16rm
  { 396,	3,	1,	0,	"CMOVNO16rr", 0|(1<<TID::Commutable), 0x41000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #396 = CMOVNO16rr
  { 397,	7,	1,	0,	"CMOVNO32rm", 0|(1<<TID::MayLoad), 0x41000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #397 = CMOVNO32rm
  { 398,	3,	1,	0,	"CMOVNO32rr", 0|(1<<TID::Commutable), 0x41000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #398 = CMOVNO32rr
  { 399,	7,	1,	0,	"CMOVNO64rm", 0|(1<<TID::MayLoad), 0x41001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #399 = CMOVNO64rm
  { 400,	3,	1,	0,	"CMOVNO64rr", 0|(1<<TID::Commutable), 0x41001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #400 = CMOVNO64rr
  { 401,	7,	1,	0,	"CMOVNP16rm", 0|(1<<TID::MayLoad), 0x4b000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #401 = CMOVNP16rm
  { 402,	3,	1,	0,	"CMOVNP16rr", 0|(1<<TID::Commutable), 0x4b000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #402 = CMOVNP16rr
  { 403,	7,	1,	0,	"CMOVNP32rm", 0|(1<<TID::MayLoad), 0x4b000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #403 = CMOVNP32rm
  { 404,	3,	1,	0,	"CMOVNP32rr", 0|(1<<TID::Commutable), 0x4b000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #404 = CMOVNP32rr
  { 405,	7,	1,	0,	"CMOVNP64rm", 0|(1<<TID::MayLoad), 0x4b001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #405 = CMOVNP64rm
  { 406,	3,	1,	0,	"CMOVNP64rr", 0|(1<<TID::Commutable), 0x4b001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #406 = CMOVNP64rr
  { 407,	1,	1,	0,	"CMOVNP_F", 0|(1<<TID::UnmodeledSideEffects), 0xd8000602ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #407 = CMOVNP_F
  { 408,	3,	1,	0,	"CMOVNP_Fp32", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo68 },  // Inst #408 = CMOVNP_Fp32
  { 409,	3,	1,	0,	"CMOVNP_Fp64", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo69 },  // Inst #409 = CMOVNP_Fp64
  { 410,	3,	1,	0,	"CMOVNP_Fp80", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo70 },  // Inst #410 = CMOVNP_Fp80
  { 411,	7,	1,	0,	"CMOVNS16rm", 0|(1<<TID::MayLoad), 0x49000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #411 = CMOVNS16rm
  { 412,	3,	1,	0,	"CMOVNS16rr", 0|(1<<TID::Commutable), 0x49000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #412 = CMOVNS16rr
  { 413,	7,	1,	0,	"CMOVNS32rm", 0|(1<<TID::MayLoad), 0x49000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #413 = CMOVNS32rm
  { 414,	3,	1,	0,	"CMOVNS32rr", 0|(1<<TID::Commutable), 0x49000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #414 = CMOVNS32rr
  { 415,	7,	1,	0,	"CMOVNS64rm", 0|(1<<TID::MayLoad), 0x49001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #415 = CMOVNS64rm
  { 416,	3,	1,	0,	"CMOVNS64rr", 0|(1<<TID::Commutable), 0x49001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #416 = CMOVNS64rr
  { 417,	7,	1,	0,	"CMOVO16rm", 0|(1<<TID::MayLoad), 0x40000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #417 = CMOVO16rm
  { 418,	3,	1,	0,	"CMOVO16rr", 0|(1<<TID::Commutable), 0x40000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #418 = CMOVO16rr
  { 419,	7,	1,	0,	"CMOVO32rm", 0|(1<<TID::MayLoad), 0x40000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #419 = CMOVO32rm
  { 420,	3,	1,	0,	"CMOVO32rr", 0|(1<<TID::Commutable), 0x40000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #420 = CMOVO32rr
  { 421,	7,	1,	0,	"CMOVO64rm", 0|(1<<TID::MayLoad), 0x40001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #421 = CMOVO64rm
  { 422,	3,	1,	0,	"CMOVO64rr", 0|(1<<TID::Commutable), 0x40001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #422 = CMOVO64rr
  { 423,	7,	1,	0,	"CMOVP16rm", 0|(1<<TID::MayLoad), 0x4a000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #423 = CMOVP16rm
  { 424,	3,	1,	0,	"CMOVP16rr", 0|(1<<TID::Commutable), 0x4a000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #424 = CMOVP16rr
  { 425,	7,	1,	0,	"CMOVP32rm", 0|(1<<TID::MayLoad), 0x4a000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #425 = CMOVP32rm
  { 426,	3,	1,	0,	"CMOVP32rr", 0|(1<<TID::Commutable), 0x4a000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #426 = CMOVP32rr
  { 427,	7,	1,	0,	"CMOVP64rm", 0|(1<<TID::MayLoad), 0x4a001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #427 = CMOVP64rm
  { 428,	3,	1,	0,	"CMOVP64rr", 0|(1<<TID::Commutable), 0x4a001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #428 = CMOVP64rr
  { 429,	1,	1,	0,	"CMOVP_F", 0|(1<<TID::UnmodeledSideEffects), 0xd8000502ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #429 = CMOVP_F
  { 430,	3,	1,	0,	"CMOVP_Fp32", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo68 },  // Inst #430 = CMOVP_Fp32
  { 431,	3,	1,	0,	"CMOVP_Fp64", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo69 },  // Inst #431 = CMOVP_Fp64
  { 432,	3,	1,	0,	"CMOVP_Fp80", 0, 0x60000ULL, ImplicitList1, NULL, NULL, OperandInfo70 },  // Inst #432 = CMOVP_Fp80
  { 433,	7,	1,	0,	"CMOVS16rm", 0|(1<<TID::MayLoad), 0x48000146ULL, ImplicitList1, NULL, NULL, OperandInfo13 },  // Inst #433 = CMOVS16rm
  { 434,	3,	1,	0,	"CMOVS16rr", 0|(1<<TID::Commutable), 0x48000145ULL, ImplicitList1, NULL, NULL, OperandInfo14 },  // Inst #434 = CMOVS16rr
  { 435,	7,	1,	0,	"CMOVS32rm", 0|(1<<TID::MayLoad), 0x48000106ULL, ImplicitList1, NULL, NULL, OperandInfo17 },  // Inst #435 = CMOVS32rm
  { 436,	3,	1,	0,	"CMOVS32rr", 0|(1<<TID::Commutable), 0x48000105ULL, ImplicitList1, NULL, NULL, OperandInfo18 },  // Inst #436 = CMOVS32rr
  { 437,	7,	1,	0,	"CMOVS64rm", 0|(1<<TID::MayLoad), 0x48001106ULL, ImplicitList1, NULL, NULL, OperandInfo21 },  // Inst #437 = CMOVS64rm
  { 438,	3,	1,	0,	"CMOVS64rr", 0|(1<<TID::Commutable), 0x48001105ULL, ImplicitList1, NULL, NULL, OperandInfo22 },  // Inst #438 = CMOVS64rr
  { 439,	4,	1,	0,	"CMOV_FR32", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, NULL, OperandInfo71 },  // Inst #439 = CMOV_FR32
  { 440,	4,	1,	0,	"CMOV_FR64", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, NULL, OperandInfo72 },  // Inst #440 = CMOV_FR64
  { 441,	4,	1,	0,	"CMOV_GR16", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo73 },  // Inst #441 = CMOV_GR16
  { 442,	4,	1,	0,	"CMOV_GR32", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo74 },  // Inst #442 = CMOV_GR32
  { 443,	4,	1,	0,	"CMOV_GR8", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo75 },  // Inst #443 = CMOV_GR8
  { 444,	4,	1,	0,	"CMOV_RFP32", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo76 },  // Inst #444 = CMOV_RFP32
  { 445,	4,	1,	0,	"CMOV_RFP64", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo77 },  // Inst #445 = CMOV_RFP64
  { 446,	4,	1,	0,	"CMOV_RFP80", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo78 },  // Inst #446 = CMOV_RFP80
  { 447,	4,	1,	0,	"CMOV_V1I64", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, NULL, OperandInfo79 },  // Inst #447 = CMOV_V1I64
  { 448,	4,	1,	0,	"CMOV_V2F64", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, NULL, OperandInfo80 },  // Inst #448 = CMOV_V2F64
  { 449,	4,	1,	0,	"CMOV_V2I64", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, NULL, OperandInfo80 },  // Inst #449 = CMOV_V2I64
  { 450,	4,	1,	0,	"CMOV_V4F32", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, NULL, OperandInfo80 },  // Inst #450 = CMOV_V4F32
  { 451,	1,	0,	0,	"CMP16i16", 0|(1<<TID::UnmodeledSideEffects), 0x3d006041ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #451 = CMP16i16
  { 452,	6,	0,	0,	"CMP16mi", 0|(1<<TID::MayLoad), 0x8100605fULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #452 = CMP16mi
  { 453,	6,	0,	0,	"CMP16mi8", 0|(1<<TID::MayLoad), 0x8300205fULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #453 = CMP16mi8
  { 454,	6,	0,	0,	"CMP16mr", 0|(1<<TID::MayLoad), 0x39000044ULL, NULL, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #454 = CMP16mr
  { 455,	2,	0,	0,	"CMP16ri", 0, 0x81006057ULL, NULL, ImplicitList1, Barriers1, OperandInfo63 },  // Inst #455 = CMP16ri
  { 456,	2,	0,	0,	"CMP16ri8", 0, 0x83002057ULL, NULL, ImplicitList1, Barriers1, OperandInfo63 },  // Inst #456 = CMP16ri8
  { 457,	6,	0,	0,	"CMP16rm", 0|(1<<TID::MayLoad), 0x3b000046ULL, NULL, ImplicitList1, Barriers1, OperandInfo55 },  // Inst #457 = CMP16rm
  { 458,	2,	0,	0,	"CMP16rr", 0, 0x39000043ULL, NULL, ImplicitList1, Barriers1, OperandInfo56 },  // Inst #458 = CMP16rr
  { 459,	2,	0,	0,	"CMP16rr_alt", 0|(1<<TID::UnmodeledSideEffects), 0x3b000045ULL, NULL, ImplicitList1, Barriers1, OperandInfo56 },  // Inst #459 = CMP16rr_alt
  { 460,	1,	0,	0,	"CMP32i32", 0|(1<<TID::UnmodeledSideEffects), 0x3d00a001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #460 = CMP32i32
  { 461,	6,	0,	0,	"CMP32mi", 0|(1<<TID::MayLoad), 0x8100a01fULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #461 = CMP32mi
  { 462,	6,	0,	0,	"CMP32mi8", 0|(1<<TID::MayLoad), 0x8300201fULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #462 = CMP32mi8
  { 463,	6,	0,	0,	"CMP32mr", 0|(1<<TID::MayLoad), 0x39000004ULL, NULL, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #463 = CMP32mr
  { 464,	2,	0,	0,	"CMP32ri", 0, 0x8100a017ULL, NULL, ImplicitList1, Barriers1, OperandInfo64 },  // Inst #464 = CMP32ri
  { 465,	2,	0,	0,	"CMP32ri8", 0, 0x83002017ULL, NULL, ImplicitList1, Barriers1, OperandInfo64 },  // Inst #465 = CMP32ri8
  { 466,	6,	0,	0,	"CMP32rm", 0|(1<<TID::MayLoad), 0x3b000006ULL, NULL, ImplicitList1, Barriers1, OperandInfo57 },  // Inst #466 = CMP32rm
  { 467,	2,	0,	0,	"CMP32rr", 0, 0x39000003ULL, NULL, ImplicitList1, Barriers1, OperandInfo58 },  // Inst #467 = CMP32rr
  { 468,	2,	0,	0,	"CMP32rr_alt", 0|(1<<TID::UnmodeledSideEffects), 0x3b000005ULL, NULL, ImplicitList1, Barriers1, OperandInfo58 },  // Inst #468 = CMP32rr_alt
  { 469,	1,	0,	0,	"CMP64i32", 0|(1<<TID::UnmodeledSideEffects), 0x3d00b001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #469 = CMP64i32
  { 470,	6,	0,	0,	"CMP64mi32", 0|(1<<TID::MayLoad), 0x8100b01fULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #470 = CMP64mi32
  { 471,	6,	0,	0,	"CMP64mi8", 0|(1<<TID::MayLoad), 0x8300301fULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #471 = CMP64mi8
  { 472,	6,	0,	0,	"CMP64mr", 0|(1<<TID::MayLoad), 0x39001004ULL, NULL, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #472 = CMP64mr
  { 473,	2,	0,	0,	"CMP64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0x3b001005ULL, NULL, ImplicitList1, Barriers1, OperandInfo60 },  // Inst #473 = CMP64mrmrr
  { 474,	2,	0,	0,	"CMP64ri32", 0, 0x8100b017ULL, NULL, ImplicitList1, Barriers1, OperandInfo65 },  // Inst #474 = CMP64ri32
  { 475,	2,	0,	0,	"CMP64ri8", 0, 0x83003017ULL, NULL, ImplicitList1, Barriers1, OperandInfo65 },  // Inst #475 = CMP64ri8
  { 476,	6,	0,	0,	"CMP64rm", 0|(1<<TID::MayLoad), 0x3b001006ULL, NULL, ImplicitList1, Barriers1, OperandInfo59 },  // Inst #476 = CMP64rm
  { 477,	2,	0,	0,	"CMP64rr", 0, 0x39001003ULL, NULL, ImplicitList1, Barriers1, OperandInfo60 },  // Inst #477 = CMP64rr
  { 478,	1,	0,	0,	"CMP8i8", 0|(1<<TID::UnmodeledSideEffects), 0x3c002001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #478 = CMP8i8
  { 479,	6,	0,	0,	"CMP8mi", 0|(1<<TID::MayLoad), 0x8000201fULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #479 = CMP8mi
  { 480,	6,	0,	0,	"CMP8mr", 0|(1<<TID::MayLoad), 0x38000004ULL, NULL, ImplicitList1, Barriers1, OperandInfo24 },  // Inst #480 = CMP8mr
  { 481,	2,	0,	0,	"CMP8ri", 0, 0x80002017ULL, NULL, ImplicitList1, Barriers1, OperandInfo81 },  // Inst #481 = CMP8ri
  { 482,	6,	0,	0,	"CMP8rm", 0|(1<<TID::MayLoad), 0x3a000006ULL, NULL, ImplicitList1, Barriers1, OperandInfo82 },  // Inst #482 = CMP8rm
  { 483,	2,	0,	0,	"CMP8rr", 0, 0x38000003ULL, NULL, ImplicitList1, Barriers1, OperandInfo83 },  // Inst #483 = CMP8rr
  { 484,	2,	0,	0,	"CMP8rr_alt", 0|(1<<TID::UnmodeledSideEffects), 0x3a000005ULL, NULL, ImplicitList1, Barriers1, OperandInfo83 },  // Inst #484 = CMP8rr_alt
  { 485,	8,	1,	0,	"CMPPDrmi", 0|(1<<TID::MayLoad), 0xc2802146ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #485 = CMPPDrmi
  { 486,	8,	1,	0,	"CMPPDrmi_alt", 0|(1<<TID::UnmodeledSideEffects), 0xc2802146ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #486 = CMPPDrmi_alt
  { 487,	4,	1,	0,	"CMPPDrri", 0, 0xc2802145ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #487 = CMPPDrri
  { 488,	4,	1,	0,	"CMPPDrri_alt", 0|(1<<TID::UnmodeledSideEffects), 0xc2802145ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #488 = CMPPDrri_alt
  { 489,	8,	1,	0,	"CMPPSrmi", 0|(1<<TID::MayLoad), 0xc2402106ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #489 = CMPPSrmi
  { 490,	8,	1,	0,	"CMPPSrmi_alt", 0|(1<<TID::UnmodeledSideEffects), 0xc2402106ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #490 = CMPPSrmi_alt
  { 491,	4,	1,	0,	"CMPPSrri", 0, 0xc2402105ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #491 = CMPPSrri
  { 492,	4,	1,	0,	"CMPPSrri_alt", 0|(1<<TID::UnmodeledSideEffects), 0xc2402105ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #492 = CMPPSrri_alt
  { 493,	0,	0,	0,	"CMPS16", 0|(1<<TID::UnmodeledSideEffects), 0xa7000041ULL, NULL, NULL, NULL, 0 },  // Inst #493 = CMPS16
  { 494,	0,	0,	0,	"CMPS32", 0|(1<<TID::UnmodeledSideEffects), 0xa7000001ULL, NULL, NULL, NULL, 0 },  // Inst #494 = CMPS32
  { 495,	0,	0,	0,	"CMPS64", 0|(1<<TID::UnmodeledSideEffects), 0xa7001001ULL, NULL, NULL, NULL, 0 },  // Inst #495 = CMPS64
  { 496,	0,	0,	0,	"CMPS8", 0|(1<<TID::UnmodeledSideEffects), 0xa6000001ULL, NULL, NULL, NULL, 0 },  // Inst #496 = CMPS8
  { 497,	8,	1,	0,	"CMPSDrm", 0|(1<<TID::MayLoad), 0xc2002b06ULL, NULL, NULL, NULL, OperandInfo84 },  // Inst #497 = CMPSDrm
  { 498,	8,	1,	0,	"CMPSDrm_alt", 0|(1<<TID::MayLoad), 0xc2002b06ULL, NULL, NULL, NULL, OperandInfo84 },  // Inst #498 = CMPSDrm_alt
  { 499,	4,	1,	0,	"CMPSDrr", 0, 0xc2002b05ULL, NULL, NULL, NULL, OperandInfo85 },  // Inst #499 = CMPSDrr
  { 500,	4,	1,	0,	"CMPSDrr_alt", 0, 0xc2002b05ULL, NULL, NULL, NULL, OperandInfo85 },  // Inst #500 = CMPSDrr_alt
  { 501,	8,	1,	0,	"CMPSSrm", 0|(1<<TID::MayLoad), 0xc2002c06ULL, NULL, NULL, NULL, OperandInfo86 },  // Inst #501 = CMPSSrm
  { 502,	8,	1,	0,	"CMPSSrm_alt", 0|(1<<TID::MayLoad), 0xc2002c06ULL, NULL, NULL, NULL, OperandInfo86 },  // Inst #502 = CMPSSrm_alt
  { 503,	4,	1,	0,	"CMPSSrr", 0, 0xc2002c05ULL, NULL, NULL, NULL, OperandInfo87 },  // Inst #503 = CMPSSrr
  { 504,	4,	1,	0,	"CMPSSrr_alt", 0, 0xc2002c05ULL, NULL, NULL, NULL, OperandInfo87 },  // Inst #504 = CMPSSrr_alt
  { 505,	5,	0,	0,	"CMPXCHG16B", 0|(1<<TID::UnmodeledSideEffects), 0xc7001119ULL, ImplicitList16, ImplicitList17, Barriers1, OperandInfo34 },  // Inst #505 = CMPXCHG16B
  { 506,	6,	0,	0,	"CMPXCHG16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xb1000144ULL, NULL, NULL, NULL, OperandInfo11 },  // Inst #506 = CMPXCHG16rm
  { 507,	2,	1,	0,	"CMPXCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0xb1000143ULL, NULL, NULL, NULL, OperandInfo56 },  // Inst #507 = CMPXCHG16rr
  { 508,	6,	0,	0,	"CMPXCHG32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xb1000104ULL, NULL, NULL, NULL, OperandInfo15 },  // Inst #508 = CMPXCHG32rm
  { 509,	2,	1,	0,	"CMPXCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0xb1000103ULL, NULL, NULL, NULL, OperandInfo58 },  // Inst #509 = CMPXCHG32rr
  { 510,	6,	0,	0,	"CMPXCHG64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xb1001104ULL, NULL, NULL, NULL, OperandInfo19 },  // Inst #510 = CMPXCHG64rm
  { 511,	2,	1,	0,	"CMPXCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0xb1001103ULL, NULL, NULL, NULL, OperandInfo60 },  // Inst #511 = CMPXCHG64rr
  { 512,	5,	0,	0,	"CMPXCHG8B", 0|(1<<TID::UnmodeledSideEffects), 0xc7000119ULL, ImplicitList6, ImplicitList18, Barriers6, OperandInfo34 },  // Inst #512 = CMPXCHG8B
  { 513,	6,	0,	0,	"CMPXCHG8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xb0000104ULL, NULL, NULL, NULL, OperandInfo24 },  // Inst #513 = CMPXCHG8rm
  { 514,	2,	1,	0,	"CMPXCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0xb0000103ULL, NULL, NULL, NULL, OperandInfo83 },  // Inst #514 = CMPXCHG8rr
  { 515,	6,	0,	0,	"COMISDrm", 0|(1<<TID::UnmodeledSideEffects), 0x2f800146ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #515 = COMISDrm
  { 516,	2,	0,	0,	"COMISDrr", 0|(1<<TID::UnmodeledSideEffects), 0x2f800145ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #516 = COMISDrr
  { 517,	6,	0,	0,	"COMISSrm", 0|(1<<TID::UnmodeledSideEffects), 0x2f400106ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #517 = COMISSrm
  { 518,	2,	0,	0,	"COMISSrr", 0|(1<<TID::UnmodeledSideEffects), 0x2f400105ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #518 = COMISSrr
  { 519,	1,	0,	0,	"COMP_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0xd8000302ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #519 = COMP_FST0r
  { 520,	1,	0,	0,	"COM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0xf0000a02ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #520 = COM_FIPr
  { 521,	1,	0,	0,	"COM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0xf0000602ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #521 = COM_FIr
  { 522,	1,	0,	0,	"COM_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0xd0000302ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #522 = COM_FST0r
  { 523,	0,	0,	0,	"COS_F", 0|(1<<TID::UnmodeledSideEffects), 0xff000401ULL, NULL, NULL, NULL, 0 },  // Inst #523 = COS_F
  { 524,	2,	1,	0,	"COS_Fp32", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo7 },  // Inst #524 = COS_Fp32
  { 525,	2,	1,	0,	"COS_Fp64", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo8 },  // Inst #525 = COS_Fp64
  { 526,	2,	1,	0,	"COS_Fp80", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo9 },  // Inst #526 = COS_Fp80
  { 527,	0,	0,	0,	"CPUID", 0|(1<<TID::UnmodeledSideEffects), 0xa2000101ULL, NULL, NULL, NULL, 0 },  // Inst #527 = CPUID
  { 528,	0,	0,	0,	"CQO", 0, 0x99001001ULL, ImplicitList15, ImplicitList19, NULL, 0 },  // Inst #528 = CQO
  { 529,	7,	1,	0,	"CRC32m16", 0|(1<<TID::MayLoad), 0xf1000f46ULL, NULL, NULL, NULL, OperandInfo17 },  // Inst #529 = CRC32m16
  { 530,	7,	1,	0,	"CRC32m32", 0|(1<<TID::MayLoad), 0xf1000f06ULL, NULL, NULL, NULL, OperandInfo17 },  // Inst #530 = CRC32m32
  { 531,	7,	1,	0,	"CRC32m8", 0|(1<<TID::MayLoad), 0xf0000f06ULL, NULL, NULL, NULL, OperandInfo17 },  // Inst #531 = CRC32m8
  { 532,	3,	1,	0,	"CRC32r16", 0, 0xf1000f45ULL, NULL, NULL, NULL, OperandInfo88 },  // Inst #532 = CRC32r16
  { 533,	3,	1,	0,	"CRC32r32", 0, 0xf1000f05ULL, NULL, NULL, NULL, OperandInfo18 },  // Inst #533 = CRC32r32
  { 534,	3,	1,	0,	"CRC32r8", 0, 0xf0000f05ULL, NULL, NULL, NULL, OperandInfo89 },  // Inst #534 = CRC32r8
  { 535,	7,	1,	0,	"CRC64m64", 0|(1<<TID::MayLoad), 0xf1001f06ULL, NULL, NULL, NULL, OperandInfo21 },  // Inst #535 = CRC64m64
  { 536,	7,	1,	0,	"CRC64m8", 0|(1<<TID::MayLoad), 0xf0001f06ULL, NULL, NULL, NULL, OperandInfo21 },  // Inst #536 = CRC64m8
  { 537,	3,	1,	0,	"CRC64r64", 0, 0xf1001f05ULL, NULL, NULL, NULL, OperandInfo22 },  // Inst #537 = CRC64r64
  { 538,	3,	1,	0,	"CRC64r8", 0, 0xf0001f05ULL, NULL, NULL, NULL, OperandInfo90 },  // Inst #538 = CRC64r8
  { 539,	0,	0,	0,	"CS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0x2e000001ULL, NULL, NULL, NULL, 0 },  // Inst #539 = CS_PREFIX
  { 540,	6,	1,	0,	"CVTDQ2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0xe6400c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #540 = CVTDQ2PDrm
  { 541,	2,	1,	0,	"CVTDQ2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0xe6400c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #541 = CVTDQ2PDrr
  { 542,	6,	1,	0,	"CVTDQ2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0x5b400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #542 = CVTDQ2PSrm
  { 543,	2,	1,	0,	"CVTDQ2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0x5b400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #543 = CVTDQ2PSrr
  { 544,	6,	1,	0,	"CVTPD2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0xe6800b06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #544 = CVTPD2DQrm
  { 545,	2,	1,	0,	"CVTPD2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0xe6800b05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #545 = CVTPD2DQrr
  { 546,	6,	1,	0,	"CVTPD2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0x5a800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #546 = CVTPD2PSrm
  { 547,	2,	1,	0,	"CVTPD2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0x5a800145ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #547 = CVTPD2PSrr
  { 548,	6,	1,	0,	"CVTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0x5b800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #548 = CVTPS2DQrm
  { 549,	2,	1,	0,	"CVTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0x5b800145ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #549 = CVTPS2DQrr
  { 550,	6,	1,	0,	"CVTPS2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0x5a000106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #550 = CVTPS2PDrm
  { 551,	2,	1,	0,	"CVTPS2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0x5a000105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #551 = CVTPS2PDrr
  { 552,	6,	1,	0,	"CVTSD2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0x2d001b06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #552 = CVTSD2SI64rm
  { 553,	2,	1,	0,	"CVTSD2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0x2d001b05ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #553 = CVTSD2SI64rr
  { 554,	6,	1,	0,	"CVTSD2SSrm", 0|(1<<TID::MayLoad), 0x5a000b06ULL, NULL, NULL, NULL, OperandInfo92 },  // Inst #554 = CVTSD2SSrm
  { 555,	2,	1,	0,	"CVTSD2SSrr", 0, 0x5a000b05ULL, NULL, NULL, NULL, OperandInfo93 },  // Inst #555 = CVTSD2SSrr
  { 556,	6,	1,	0,	"CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0x2a001b06ULL, NULL, NULL, NULL, OperandInfo94 },  // Inst #556 = CVTSI2SD64rm
  { 557,	2,	1,	0,	"CVTSI2SD64rr", 0, 0x2a001b05ULL, NULL, NULL, NULL, OperandInfo95 },  // Inst #557 = CVTSI2SD64rr
  { 558,	6,	1,	0,	"CVTSI2SDrm", 0|(1<<TID::MayLoad), 0x2a000b06ULL, NULL, NULL, NULL, OperandInfo94 },  // Inst #558 = CVTSI2SDrm
  { 559,	2,	1,	0,	"CVTSI2SDrr", 0, 0x2a000b05ULL, NULL, NULL, NULL, OperandInfo96 },  // Inst #559 = CVTSI2SDrr
  { 560,	6,	1,	0,	"CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0x2a001c06ULL, NULL, NULL, NULL, OperandInfo92 },  // Inst #560 = CVTSI2SS64rm
  { 561,	2,	1,	0,	"CVTSI2SS64rr", 0, 0x2a001c05ULL, NULL, NULL, NULL, OperandInfo97 },  // Inst #561 = CVTSI2SS64rr
  { 562,	6,	1,	0,	"CVTSI2SSrm", 0|(1<<TID::MayLoad), 0x2a000c06ULL, NULL, NULL, NULL, OperandInfo92 },  // Inst #562 = CVTSI2SSrm
  { 563,	2,	1,	0,	"CVTSI2SSrr", 0, 0x2a000c05ULL, NULL, NULL, NULL, OperandInfo98 },  // Inst #563 = CVTSI2SSrr
  { 564,	6,	1,	0,	"CVTSS2SDrm", 0|(1<<TID::MayLoad), 0x5a000c06ULL, NULL, NULL, NULL, OperandInfo94 },  // Inst #564 = CVTSS2SDrm
  { 565,	2,	1,	0,	"CVTSS2SDrr", 0, 0x5a000c05ULL, NULL, NULL, NULL, OperandInfo99 },  // Inst #565 = CVTSS2SDrr
  { 566,	6,	1,	0,	"CVTSS2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0x2d001c06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #566 = CVTSS2SI64rm
  { 567,	2,	1,	0,	"CVTSS2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0x2d001c05ULL, NULL, NULL, NULL, OperandInfo100 },  // Inst #567 = CVTSS2SI64rr
  { 568,	6,	1,	0,	"CVTSS2SIrm", 0|(1<<TID::UnmodeledSideEffects), 0x2d000c06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #568 = CVTSS2SIrm
  { 569,	2,	1,	0,	"CVTSS2SIrr", 0|(1<<TID::UnmodeledSideEffects), 0x2d000c05ULL, NULL, NULL, NULL, OperandInfo101 },  // Inst #569 = CVTSS2SIrr
  { 570,	6,	1,	0,	"CVTTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0x5b000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #570 = CVTTPS2DQrm
  { 571,	2,	1,	0,	"CVTTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0x5b000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #571 = CVTTPS2DQrr
  { 572,	6,	1,	0,	"CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0x2c001b06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #572 = CVTTSD2SI64rm
  { 573,	2,	1,	0,	"CVTTSD2SI64rr", 0, 0x2c001b05ULL, NULL, NULL, NULL, OperandInfo102 },  // Inst #573 = CVTTSD2SI64rr
  { 574,	6,	1,	0,	"CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0x2c000b06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #574 = CVTTSD2SIrm
  { 575,	2,	1,	0,	"CVTTSD2SIrr", 0, 0x2c000b05ULL, NULL, NULL, NULL, OperandInfo103 },  // Inst #575 = CVTTSD2SIrr
  { 576,	6,	1,	0,	"CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0x2c001c06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #576 = CVTTSS2SI64rm
  { 577,	2,	1,	0,	"CVTTSS2SI64rr", 0, 0x2c001c05ULL, NULL, NULL, NULL, OperandInfo100 },  // Inst #577 = CVTTSS2SI64rr
  { 578,	6,	1,	0,	"CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0x2c000c06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #578 = CVTTSS2SIrm
  { 579,	2,	1,	0,	"CVTTSS2SIrr", 0, 0x2c000c05ULL, NULL, NULL, NULL, OperandInfo101 },  // Inst #579 = CVTTSS2SIrr
  { 580,	0,	0,	0,	"CWD", 0, 0x99000041ULL, ImplicitList12, ImplicitList20, NULL, 0 },  // Inst #580 = CWD
  { 581,	0,	0,	0,	"CWDE", 0, 0x98000001ULL, ImplicitList12, ImplicitList13, NULL, 0 },  // Inst #581 = CWDE
  { 582,	5,	0,	0,	"DEC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xff000059ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #582 = DEC16m
  { 583,	2,	1,	0,	"DEC16r", 0|(1<<TID::ConvertibleTo3Addr), 0x48000042ULL, NULL, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #583 = DEC16r
  { 584,	5,	0,	0,	"DEC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xff000019ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #584 = DEC32m
  { 585,	2,	1,	0,	"DEC32r", 0|(1<<TID::ConvertibleTo3Addr), 0x48000002ULL, NULL, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #585 = DEC32r
  { 586,	5,	0,	0,	"DEC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xff000059ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #586 = DEC64_16m
  { 587,	2,	1,	0,	"DEC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0xff000051ULL, NULL, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #587 = DEC64_16r
  { 588,	5,	0,	0,	"DEC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xff000019ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #588 = DEC64_32m
  { 589,	2,	1,	0,	"DEC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0xff000011ULL, NULL, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #589 = DEC64_32r
  { 590,	5,	0,	0,	"DEC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xff001019ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #590 = DEC64m
  { 591,	2,	1,	0,	"DEC64r", 0|(1<<TID::ConvertibleTo3Addr), 0xff001011ULL, NULL, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #591 = DEC64r
  { 592,	5,	0,	0,	"DEC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xfe000019ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #592 = DEC8m
  { 593,	2,	1,	0,	"DEC8r", 0, 0xfe000011ULL, NULL, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #593 = DEC8r
  { 594,	5,	0,	0,	"DIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xf700005eULL, ImplicitList20, ImplicitList21, Barriers1, OperandInfo34 },  // Inst #594 = DIV16m
  { 595,	1,	0,	0,	"DIV16r", 0|(1<<TID::UnmodeledSideEffects), 0xf7000056ULL, ImplicitList20, ImplicitList21, Barriers1, OperandInfo106 },  // Inst #595 = DIV16r
  { 596,	5,	0,	0,	"DIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xf700001eULL, ImplicitList14, ImplicitList18, Barriers6, OperandInfo34 },  // Inst #596 = DIV32m
  { 597,	1,	0,	0,	"DIV32r", 0|(1<<TID::UnmodeledSideEffects), 0xf7000016ULL, ImplicitList14, ImplicitList18, Barriers6, OperandInfo66 },  // Inst #597 = DIV32r
  { 598,	5,	0,	0,	"DIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xf700101eULL, ImplicitList19, ImplicitList17, Barriers1, OperandInfo34 },  // Inst #598 = DIV64m
  { 599,	1,	0,	0,	"DIV64r", 0|(1<<TID::UnmodeledSideEffects), 0xf7001016ULL, ImplicitList19, ImplicitList17, Barriers1, OperandInfo67 },  // Inst #599 = DIV64r
  { 600,	5,	0,	0,	"DIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xf600001eULL, ImplicitList12, ImplicitList22, Barriers1, OperandInfo34 },  // Inst #600 = DIV8m
  { 601,	1,	0,	0,	"DIV8r", 0|(1<<TID::UnmodeledSideEffects), 0xf6000016ULL, ImplicitList12, ImplicitList22, Barriers1, OperandInfo107 },  // Inst #601 = DIV8r
  { 602,	7,	1,	0,	"DIVPDrm", 0|(1<<TID::MayLoad), 0x5e800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #602 = DIVPDrm
  { 603,	3,	1,	0,	"DIVPDrr", 0, 0x5e800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #603 = DIVPDrr
  { 604,	7,	1,	0,	"DIVPSrm", 0|(1<<TID::MayLoad), 0x5e400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #604 = DIVPSrm
  { 605,	3,	1,	0,	"DIVPSrr", 0, 0x5e400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #605 = DIVPSrr
  { 606,	5,	0,	0,	"DIVR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xd800001fULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #606 = DIVR_F32m
  { 607,	5,	0,	0,	"DIVR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xdc00001fULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #607 = DIVR_F64m
  { 608,	5,	0,	0,	"DIVR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xde00001fULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #608 = DIVR_FI16m
  { 609,	5,	0,	0,	"DIVR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xda00001fULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #609 = DIVR_FI32m
  { 610,	1,	0,	0,	"DIVR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0xf0000902ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #610 = DIVR_FPrST0
  { 611,	1,	0,	0,	"DIVR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0xf8000302ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #611 = DIVR_FST0r
  { 612,	7,	1,	0,	"DIVR_Fp32m", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #612 = DIVR_Fp32m
  { 613,	7,	1,	0,	"DIVR_Fp64m", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #613 = DIVR_Fp64m
  { 614,	7,	1,	0,	"DIVR_Fp64m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #614 = DIVR_Fp64m32
  { 615,	7,	1,	0,	"DIVR_Fp80m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #615 = DIVR_Fp80m32
  { 616,	7,	1,	0,	"DIVR_Fp80m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #616 = DIVR_Fp80m64
  { 617,	7,	1,	0,	"DIVR_FpI16m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #617 = DIVR_FpI16m32
  { 618,	7,	1,	0,	"DIVR_FpI16m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #618 = DIVR_FpI16m64
  { 619,	7,	1,	0,	"DIVR_FpI16m80", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #619 = DIVR_FpI16m80
  { 620,	7,	1,	0,	"DIVR_FpI32m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #620 = DIVR_FpI32m32
  { 621,	7,	1,	0,	"DIVR_FpI32m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #621 = DIVR_FpI32m64
  { 622,	7,	1,	0,	"DIVR_FpI32m80", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #622 = DIVR_FpI32m80
  { 623,	1,	0,	0,	"DIVR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0xf0000702ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #623 = DIVR_FrST0
  { 624,	7,	1,	0,	"DIVSDrm", 0|(1<<TID::MayLoad), 0x5e000b06ULL, NULL, NULL, NULL, OperandInfo30 },  // Inst #624 = DIVSDrm
  { 625,	7,	1,	0,	"DIVSDrm_Int", 0|(1<<TID::MayLoad), 0x5e000b06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #625 = DIVSDrm_Int
  { 626,	3,	1,	0,	"DIVSDrr", 0, 0x5e000b05ULL, NULL, NULL, NULL, OperandInfo31 },  // Inst #626 = DIVSDrr
  { 627,	3,	1,	0,	"DIVSDrr_Int", 0, 0x5e000b05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #627 = DIVSDrr_Int
  { 628,	7,	1,	0,	"DIVSSrm", 0|(1<<TID::MayLoad), 0x5e000c06ULL, NULL, NULL, NULL, OperandInfo32 },  // Inst #628 = DIVSSrm
  { 629,	7,	1,	0,	"DIVSSrm_Int", 0|(1<<TID::MayLoad), 0x5e000c06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #629 = DIVSSrm_Int
  { 630,	3,	1,	0,	"DIVSSrr", 0, 0x5e000c05ULL, NULL, NULL, NULL, OperandInfo33 },  // Inst #630 = DIVSSrr
  { 631,	3,	1,	0,	"DIVSSrr_Int", 0, 0x5e000c05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #631 = DIVSSrr_Int
  { 632,	5,	0,	0,	"DIV_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xd800001eULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #632 = DIV_F32m
  { 633,	5,	0,	0,	"DIV_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xdc00001eULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #633 = DIV_F64m
  { 634,	5,	0,	0,	"DIV_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xde00001eULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #634 = DIV_FI16m
  { 635,	5,	0,	0,	"DIV_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xda00001eULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #635 = DIV_FI32m
  { 636,	1,	0,	0,	"DIV_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0xf8000902ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #636 = DIV_FPrST0
  { 637,	1,	0,	0,	"DIV_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0xf0000302ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #637 = DIV_FST0r
  { 638,	3,	1,	0,	"DIV_Fp32", 0, 0x40000ULL, NULL, NULL, NULL, OperandInfo36 },  // Inst #638 = DIV_Fp32
  { 639,	7,	1,	0,	"DIV_Fp32m", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #639 = DIV_Fp32m
  { 640,	3,	1,	0,	"DIV_Fp64", 0, 0x40000ULL, NULL, NULL, NULL, OperandInfo38 },  // Inst #640 = DIV_Fp64
  { 641,	7,	1,	0,	"DIV_Fp64m", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #641 = DIV_Fp64m
  { 642,	7,	1,	0,	"DIV_Fp64m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #642 = DIV_Fp64m32
  { 643,	3,	1,	0,	"DIV_Fp80", 0, 0x40000ULL, NULL, NULL, NULL, OperandInfo40 },  // Inst #643 = DIV_Fp80
  { 644,	7,	1,	0,	"DIV_Fp80m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #644 = DIV_Fp80m32
  { 645,	7,	1,	0,	"DIV_Fp80m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #645 = DIV_Fp80m64
  { 646,	7,	1,	0,	"DIV_FpI16m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #646 = DIV_FpI16m32
  { 647,	7,	1,	0,	"DIV_FpI16m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #647 = DIV_FpI16m64
  { 648,	7,	1,	0,	"DIV_FpI16m80", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #648 = DIV_FpI16m80
  { 649,	7,	1,	0,	"DIV_FpI32m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #649 = DIV_FpI32m32
  { 650,	7,	1,	0,	"DIV_FpI32m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #650 = DIV_FpI32m64
  { 651,	7,	1,	0,	"DIV_FpI32m80", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #651 = DIV_FpI32m80
  { 652,	1,	0,	0,	"DIV_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0xf8000702ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #652 = DIV_FrST0
  { 653,	8,	1,	0,	"DPPDrmi", 0|(1<<TID::MayLoad), 0x41c02e46ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #653 = DPPDrmi
  { 654,	4,	1,	0,	"DPPDrri", 0|(1<<TID::Commutable), 0x41c02e45ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #654 = DPPDrri
  { 655,	8,	1,	0,	"DPPSrmi", 0|(1<<TID::MayLoad), 0x40c02e46ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #655 = DPPSrmi
  { 656,	4,	1,	0,	"DPPSrri", 0|(1<<TID::Commutable), 0x40c02e45ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #656 = DPPSrri
  { 657,	0,	0,	0,	"DS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0x3e000001ULL, NULL, NULL, NULL, 0 },  // Inst #657 = DS_PREFIX
  { 658,	1,	0,	0,	"EH_RETURN", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0xc3000001ULL, NULL, NULL, NULL, OperandInfo66 },  // Inst #658 = EH_RETURN
  { 659,	1,	0,	0,	"EH_RETURN64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0xc3000001ULL, NULL, NULL, NULL, OperandInfo67 },  // Inst #659 = EH_RETURN64
  { 660,	2,	0,	0,	"ENTER", 0|(1<<TID::UnmodeledSideEffects), 0xc8000001ULL, NULL, NULL, NULL, OperandInfo6 },  // Inst #660 = ENTER
  { 661,	0,	0,	0,	"ES_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0x26000001ULL, NULL, NULL, NULL, 0 },  // Inst #661 = ES_PREFIX
  { 662,	7,	0,	0,	"EXTRACTPSmr", 0|(1<<TID::MayStore), 0x17c02e44ULL, NULL, NULL, NULL, OperandInfo108 },  // Inst #662 = EXTRACTPSmr
  { 663,	3,	1,	0,	"EXTRACTPSrr", 0, 0x17c02e43ULL, NULL, NULL, NULL, OperandInfo109 },  // Inst #663 = EXTRACTPSrr
  { 664,	0,	0,	0,	"F2XM1", 0|(1<<TID::UnmodeledSideEffects), 0xf0000401ULL, NULL, NULL, NULL, 0 },  // Inst #664 = F2XM1
  { 665,	2,	0,	0,	"FARCALL16i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0x9a00606bULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo6 },  // Inst #665 = FARCALL16i
  { 666,	5,	0,	0,	"FARCALL16m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0xff00005bULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo34 },  // Inst #666 = FARCALL16m
  { 667,	2,	0,	0,	"FARCALL32i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0x9a00a02bULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo6 },  // Inst #667 = FARCALL32i
  { 668,	5,	0,	0,	"FARCALL32m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0xff00001bULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo34 },  // Inst #668 = FARCALL32m
  { 669,	5,	0,	0,	"FARCALL64", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0xff00101bULL, ImplicitList4, ImplicitList10, Barriers4, OperandInfo34 },  // Inst #669 = FARCALL64
  { 670,	2,	0,	0,	"FARJMP16i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0xea00606bULL, NULL, NULL, NULL, OperandInfo6 },  // Inst #670 = FARJMP16i
  { 671,	5,	0,	0,	"FARJMP16m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0xff00005dULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #671 = FARJMP16m
  { 672,	2,	0,	0,	"FARJMP32i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0xea00a02bULL, NULL, NULL, NULL, OperandInfo6 },  // Inst #672 = FARJMP32i
  { 673,	5,	0,	0,	"FARJMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0xff00001dULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #673 = FARJMP32m
  { 674,	5,	0,	0,	"FARJMP64", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0xff00101dULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #674 = FARJMP64
  { 675,	5,	0,	0,	"FBLDm", 0|(1<<TID::UnmodeledSideEffects), 0xdf00001cULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #675 = FBLDm
  { 676,	5,	1,	0,	"FBSTPm", 0|(1<<TID::UnmodeledSideEffects), 0xdf00001eULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #676 = FBSTPm
  { 677,	5,	0,	0,	"FCOM32m", 0|(1<<TID::UnmodeledSideEffects), 0xd800001aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #677 = FCOM32m
  { 678,	5,	0,	0,	"FCOM64m", 0|(1<<TID::UnmodeledSideEffects), 0xdc00001aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #678 = FCOM64m
  { 679,	5,	0,	0,	"FCOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0xd800001bULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #679 = FCOMP32m
  { 680,	5,	0,	0,	"FCOMP64m", 0|(1<<TID::UnmodeledSideEffects), 0xdc00001bULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #680 = FCOMP64m
  { 681,	0,	0,	0,	"FCOMPP", 0|(1<<TID::UnmodeledSideEffects), 0xd9000901ULL, NULL, NULL, NULL, 0 },  // Inst #681 = FCOMPP
  { 682,	0,	0,	0,	"FDECSTP", 0|(1<<TID::UnmodeledSideEffects), 0xf6000401ULL, NULL, NULL, NULL, 0 },  // Inst #682 = FDECSTP
  { 683,	1,	0,	0,	"FFREE", 0|(1<<TID::UnmodeledSideEffects), 0xc0000802ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #683 = FFREE
  { 684,	5,	0,	0,	"FICOM16m", 0|(1<<TID::UnmodeledSideEffects), 0xde00001aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #684 = FICOM16m
  { 685,	5,	0,	0,	"FICOM32m", 0|(1<<TID::UnmodeledSideEffects), 0xda00001aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #685 = FICOM32m
  { 686,	5,	0,	0,	"FICOMP16m", 0|(1<<TID::UnmodeledSideEffects), 0xde00001bULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #686 = FICOMP16m
  { 687,	5,	0,	0,	"FICOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0xda00001bULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #687 = FICOMP32m
  { 688,	0,	0,	0,	"FINCSTP", 0|(1<<TID::UnmodeledSideEffects), 0xf7000401ULL, NULL, NULL, NULL, 0 },  // Inst #688 = FINCSTP
  { 689,	5,	0,	0,	"FLDCW16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xd900001dULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #689 = FLDCW16m
  { 690,	5,	0,	0,	"FLDENVm", 0|(1<<TID::UnmodeledSideEffects), 0xd900001cULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #690 = FLDENVm
  { 691,	0,	0,	0,	"FLDL2E", 0|(1<<TID::UnmodeledSideEffects), 0xea000401ULL, NULL, NULL, NULL, 0 },  // Inst #691 = FLDL2E
  { 692,	0,	0,	0,	"FLDL2T", 0|(1<<TID::UnmodeledSideEffects), 0xe9000401ULL, NULL, NULL, NULL, 0 },  // Inst #692 = FLDL2T
  { 693,	0,	0,	0,	"FLDLG2", 0|(1<<TID::UnmodeledSideEffects), 0xec000401ULL, NULL, NULL, NULL, 0 },  // Inst #693 = FLDLG2
  { 694,	0,	0,	0,	"FLDLN2", 0|(1<<TID::UnmodeledSideEffects), 0xed000401ULL, NULL, NULL, NULL, 0 },  // Inst #694 = FLDLN2
  { 695,	0,	0,	0,	"FLDPI", 0|(1<<TID::UnmodeledSideEffects), 0xeb000401ULL, NULL, NULL, NULL, 0 },  // Inst #695 = FLDPI
  { 696,	0,	0,	0,	"FNCLEX", 0|(1<<TID::UnmodeledSideEffects), 0xe2000601ULL, NULL, NULL, NULL, 0 },  // Inst #696 = FNCLEX
  { 697,	0,	0,	0,	"FNINIT", 0|(1<<TID::UnmodeledSideEffects), 0xe3000601ULL, NULL, NULL, NULL, 0 },  // Inst #697 = FNINIT
  { 698,	0,	0,	0,	"FNOP", 0|(1<<TID::UnmodeledSideEffects), 0xd0000401ULL, NULL, NULL, NULL, 0 },  // Inst #698 = FNOP
  { 699,	5,	0,	0,	"FNSTCW16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xd900001fULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #699 = FNSTCW16m
  { 700,	0,	0,	0,	"FNSTSW8r", 0|(1<<TID::UnmodeledSideEffects), 0xe0000a01ULL, NULL, ImplicitList12, NULL, 0 },  // Inst #700 = FNSTSW8r
  { 701,	5,	1,	0,	"FNSTSWm", 0|(1<<TID::UnmodeledSideEffects), 0xdd00001fULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #701 = FNSTSWm
  { 702,	6,	0,	0,	"FP32_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, NULL, NULL, OperandInfo110 },  // Inst #702 = FP32_TO_INT16_IN_MEM
  { 703,	6,	0,	0,	"FP32_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, NULL, NULL, OperandInfo110 },  // Inst #703 = FP32_TO_INT32_IN_MEM
  { 704,	6,	0,	0,	"FP32_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, NULL, NULL, OperandInfo110 },  // Inst #704 = FP32_TO_INT64_IN_MEM
  { 705,	6,	0,	0,	"FP64_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, NULL, NULL, OperandInfo111 },  // Inst #705 = FP64_TO_INT16_IN_MEM
  { 706,	6,	0,	0,	"FP64_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, NULL, NULL, OperandInfo111 },  // Inst #706 = FP64_TO_INT32_IN_MEM
  { 707,	6,	0,	0,	"FP64_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, NULL, NULL, OperandInfo111 },  // Inst #707 = FP64_TO_INT64_IN_MEM
  { 708,	6,	0,	0,	"FP80_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, NULL, NULL, OperandInfo112 },  // Inst #708 = FP80_TO_INT16_IN_MEM
  { 709,	6,	0,	0,	"FP80_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, NULL, NULL, OperandInfo112 },  // Inst #709 = FP80_TO_INT32_IN_MEM
  { 710,	6,	0,	0,	"FP80_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, NULL, NULL, NULL, OperandInfo112 },  // Inst #710 = FP80_TO_INT64_IN_MEM
  { 711,	0,	0,	0,	"FPATAN", 0|(1<<TID::UnmodeledSideEffects), 0xf3000401ULL, NULL, NULL, NULL, 0 },  // Inst #711 = FPATAN
  { 712,	0,	0,	0,	"FPREM", 0|(1<<TID::UnmodeledSideEffects), 0xf8000401ULL, NULL, NULL, NULL, 0 },  // Inst #712 = FPREM
  { 713,	0,	0,	0,	"FPREM1", 0|(1<<TID::UnmodeledSideEffects), 0xf5000401ULL, NULL, NULL, NULL, 0 },  // Inst #713 = FPREM1
  { 714,	0,	0,	0,	"FPTAN", 0|(1<<TID::UnmodeledSideEffects), 0xf2000401ULL, NULL, NULL, NULL, 0 },  // Inst #714 = FPTAN
  { 715,	0,	0,	0,	"FRNDINT", 0|(1<<TID::UnmodeledSideEffects), 0xfc000401ULL, NULL, NULL, NULL, 0 },  // Inst #715 = FRNDINT
  { 716,	5,	1,	0,	"FRSTORm", 0|(1<<TID::UnmodeledSideEffects), 0xdd00001cULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #716 = FRSTORm
  { 717,	5,	1,	0,	"FSAVEm", 0|(1<<TID::UnmodeledSideEffects), 0xdd00001eULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #717 = FSAVEm
  { 718,	0,	0,	0,	"FSCALE", 0|(1<<TID::UnmodeledSideEffects), 0xfd000401ULL, NULL, NULL, NULL, 0 },  // Inst #718 = FSCALE
  { 719,	0,	0,	0,	"FSINCOS", 0|(1<<TID::UnmodeledSideEffects), 0xfb000401ULL, NULL, NULL, NULL, 0 },  // Inst #719 = FSINCOS
  { 720,	5,	1,	0,	"FSTENVm", 0|(1<<TID::UnmodeledSideEffects), 0xd900001eULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #720 = FSTENVm
  { 721,	6,	1,	0,	"FS_MOV32rm", 0|(1<<TID::MayLoad), 0x8b100006ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #721 = FS_MOV32rm
  { 722,	0,	0,	0,	"FS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0x64000001ULL, NULL, NULL, NULL, 0 },  // Inst #722 = FS_PREFIX
  { 723,	0,	0,	0,	"FXAM", 0|(1<<TID::UnmodeledSideEffects), 0xe5000401ULL, NULL, NULL, NULL, 0 },  // Inst #723 = FXAM
  { 724,	5,	0,	0,	"FXRSTOR", 0|(1<<TID::UnmodeledSideEffects), 0xae000119ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #724 = FXRSTOR
  { 725,	5,	1,	0,	"FXSAVE", 0|(1<<TID::UnmodeledSideEffects), 0xae000118ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #725 = FXSAVE
  { 726,	0,	0,	0,	"FXTRACT", 0|(1<<TID::UnmodeledSideEffects), 0xf4000401ULL, NULL, NULL, NULL, 0 },  // Inst #726 = FXTRACT
  { 727,	0,	0,	0,	"FYL2X", 0|(1<<TID::UnmodeledSideEffects), 0xf1000401ULL, NULL, NULL, NULL, 0 },  // Inst #727 = FYL2X
  { 728,	0,	0,	0,	"FYL2XP1", 0|(1<<TID::UnmodeledSideEffects), 0xf9000401ULL, NULL, NULL, NULL, 0 },  // Inst #728 = FYL2XP1
  { 729,	1,	1,	0,	"FpGET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0x70000ULL, NULL, NULL, NULL, OperandInfo113 },  // Inst #729 = FpGET_ST0_32
  { 730,	1,	1,	0,	"FpGET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0x70000ULL, NULL, NULL, NULL, OperandInfo114 },  // Inst #730 = FpGET_ST0_64
  { 731,	1,	1,	0,	"FpGET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0x70000ULL, NULL, NULL, NULL, OperandInfo115 },  // Inst #731 = FpGET_ST0_80
  { 732,	1,	1,	0,	"FpGET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0x70000ULL, NULL, NULL, NULL, OperandInfo113 },  // Inst #732 = FpGET_ST1_32
  { 733,	1,	1,	0,	"FpGET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0x70000ULL, NULL, NULL, NULL, OperandInfo114 },  // Inst #733 = FpGET_ST1_64
  { 734,	1,	1,	0,	"FpGET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0x70000ULL, NULL, NULL, NULL, OperandInfo115 },  // Inst #734 = FpGET_ST1_80
  { 735,	1,	0,	0,	"FpSET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0x70000ULL, NULL, ImplicitList23, NULL, OperandInfo113 },  // Inst #735 = FpSET_ST0_32
  { 736,	1,	0,	0,	"FpSET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0x70000ULL, NULL, ImplicitList23, NULL, OperandInfo114 },  // Inst #736 = FpSET_ST0_64
  { 737,	1,	0,	0,	"FpSET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0x70000ULL, NULL, ImplicitList23, NULL, OperandInfo115 },  // Inst #737 = FpSET_ST0_80
  { 738,	1,	0,	0,	"FpSET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0x70000ULL, NULL, ImplicitList24, NULL, OperandInfo113 },  // Inst #738 = FpSET_ST1_32
  { 739,	1,	0,	0,	"FpSET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0x70000ULL, NULL, ImplicitList24, NULL, OperandInfo114 },  // Inst #739 = FpSET_ST1_64
  { 740,	1,	0,	0,	"FpSET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0x70000ULL, NULL, ImplicitList24, NULL, OperandInfo115 },  // Inst #740 = FpSET_ST1_80
  { 741,	7,	1,	0,	"FsANDNPDrm", 0|(1<<TID::MayLoad), 0x55800146ULL, NULL, NULL, NULL, OperandInfo30 },  // Inst #741 = FsANDNPDrm
  { 742,	3,	1,	0,	"FsANDNPDrr", 0, 0x55800145ULL, NULL, NULL, NULL, OperandInfo31 },  // Inst #742 = FsANDNPDrr
  { 743,	7,	1,	0,	"FsANDNPSrm", 0|(1<<TID::MayLoad), 0x55400106ULL, NULL, NULL, NULL, OperandInfo32 },  // Inst #743 = FsANDNPSrm
  { 744,	3,	1,	0,	"FsANDNPSrr", 0, 0x55400105ULL, NULL, NULL, NULL, OperandInfo33 },  // Inst #744 = FsANDNPSrr
  { 745,	7,	1,	0,	"FsANDPDrm", 0|(1<<TID::MayLoad), 0x54800146ULL, NULL, NULL, NULL, OperandInfo30 },  // Inst #745 = FsANDPDrm
  { 746,	3,	1,	0,	"FsANDPDrr", 0|(1<<TID::Commutable), 0x54800145ULL, NULL, NULL, NULL, OperandInfo31 },  // Inst #746 = FsANDPDrr
  { 747,	7,	1,	0,	"FsANDPSrm", 0|(1<<TID::MayLoad), 0x54400106ULL, NULL, NULL, NULL, OperandInfo32 },  // Inst #747 = FsANDPSrm
  { 748,	3,	1,	0,	"FsANDPSrr", 0|(1<<TID::Commutable), 0x54400105ULL, NULL, NULL, NULL, OperandInfo33 },  // Inst #748 = FsANDPSrr
  { 749,	1,	1,	0,	"FsFLD0SD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0xef000160ULL, NULL, NULL, NULL, OperandInfo116 },  // Inst #749 = FsFLD0SD
  { 750,	1,	1,	0,	"FsFLD0SS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0xef000160ULL, NULL, NULL, NULL, OperandInfo117 },  // Inst #750 = FsFLD0SS
  { 751,	6,	1,	0,	"FsMOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x28800146ULL, NULL, NULL, NULL, OperandInfo94 },  // Inst #751 = FsMOVAPDrm
  { 752,	2,	1,	0,	"FsMOVAPDrr", 0, 0x28800145ULL, NULL, NULL, NULL, OperandInfo118 },  // Inst #752 = FsMOVAPDrr
  { 753,	6,	1,	0,	"FsMOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x28400106ULL, NULL, NULL, NULL, OperandInfo92 },  // Inst #753 = FsMOVAPSrm
  { 754,	2,	1,	0,	"FsMOVAPSrr", 0, 0x28400105ULL, NULL, NULL, NULL, OperandInfo119 },  // Inst #754 = FsMOVAPSrr
  { 755,	7,	1,	0,	"FsORPDrm", 0|(1<<TID::MayLoad), 0x56800146ULL, NULL, NULL, NULL, OperandInfo30 },  // Inst #755 = FsORPDrm
  { 756,	3,	1,	0,	"FsORPDrr", 0|(1<<TID::Commutable), 0x56800145ULL, NULL, NULL, NULL, OperandInfo31 },  // Inst #756 = FsORPDrr
  { 757,	7,	1,	0,	"FsORPSrm", 0|(1<<TID::MayLoad), 0x56400106ULL, NULL, NULL, NULL, OperandInfo32 },  // Inst #757 = FsORPSrm
  { 758,	3,	1,	0,	"FsORPSrr", 0|(1<<TID::Commutable), 0x56400105ULL, NULL, NULL, NULL, OperandInfo33 },  // Inst #758 = FsORPSrr
  { 759,	7,	1,	0,	"FsXORPDrm", 0|(1<<TID::MayLoad), 0x57800146ULL, NULL, NULL, NULL, OperandInfo30 },  // Inst #759 = FsXORPDrm
  { 760,	3,	1,	0,	"FsXORPDrr", 0|(1<<TID::Commutable), 0x57800145ULL, NULL, NULL, NULL, OperandInfo31 },  // Inst #760 = FsXORPDrr
  { 761,	7,	1,	0,	"FsXORPSrm", 0|(1<<TID::MayLoad), 0x57400106ULL, NULL, NULL, NULL, OperandInfo32 },  // Inst #761 = FsXORPSrm
  { 762,	3,	1,	0,	"FsXORPSrr", 0|(1<<TID::Commutable), 0x57400105ULL, NULL, NULL, NULL, OperandInfo33 },  // Inst #762 = FsXORPSrr
  { 763,	6,	1,	0,	"GS_MOV32rm", 0|(1<<TID::MayLoad), 0x8b200006ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #763 = GS_MOV32rm
  { 764,	0,	0,	0,	"GS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0x65000001ULL, NULL, NULL, NULL, 0 },  // Inst #764 = GS_PREFIX
  { 765,	7,	1,	0,	"HADDPDrm", 0|(1<<TID::MayLoad), 0x7c800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #765 = HADDPDrm
  { 766,	3,	1,	0,	"HADDPDrr", 0, 0x7c800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #766 = HADDPDrr
  { 767,	7,	1,	0,	"HADDPSrm", 0|(1<<TID::MayLoad), 0x7c800b06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #767 = HADDPSrm
  { 768,	3,	1,	0,	"HADDPSrr", 0, 0x7c800b05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #768 = HADDPSrr
  { 769,	0,	0,	0,	"HLT", 0|(1<<TID::UnmodeledSideEffects), 0xf4000001ULL, NULL, NULL, NULL, 0 },  // Inst #769 = HLT
  { 770,	7,	1,	0,	"HSUBPDrm", 0|(1<<TID::MayLoad), 0x7d800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #770 = HSUBPDrm
  { 771,	3,	1,	0,	"HSUBPDrr", 0, 0x7d800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #771 = HSUBPDrr
  { 772,	7,	1,	0,	"HSUBPSrm", 0|(1<<TID::MayLoad), 0x7d800b06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #772 = HSUBPSrm
  { 773,	3,	1,	0,	"HSUBPSrr", 0, 0x7d800b05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #773 = HSUBPSrr
  { 774,	5,	0,	0,	"IDIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xf700005fULL, ImplicitList20, ImplicitList21, Barriers1, OperandInfo34 },  // Inst #774 = IDIV16m
  { 775,	1,	0,	0,	"IDIV16r", 0|(1<<TID::UnmodeledSideEffects), 0xf7000057ULL, ImplicitList20, ImplicitList21, Barriers1, OperandInfo106 },  // Inst #775 = IDIV16r
  { 776,	5,	0,	0,	"IDIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xf700001fULL, ImplicitList14, ImplicitList18, Barriers6, OperandInfo34 },  // Inst #776 = IDIV32m
  { 777,	1,	0,	0,	"IDIV32r", 0|(1<<TID::UnmodeledSideEffects), 0xf7000017ULL, ImplicitList14, ImplicitList18, Barriers6, OperandInfo66 },  // Inst #777 = IDIV32r
  { 778,	5,	0,	0,	"IDIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xf700101fULL, ImplicitList19, ImplicitList17, Barriers1, OperandInfo34 },  // Inst #778 = IDIV64m
  { 779,	1,	0,	0,	"IDIV64r", 0|(1<<TID::UnmodeledSideEffects), 0xf7001017ULL, ImplicitList19, ImplicitList17, Barriers1, OperandInfo67 },  // Inst #779 = IDIV64r
  { 780,	5,	0,	0,	"IDIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xf600001fULL, ImplicitList12, ImplicitList22, Barriers1, OperandInfo34 },  // Inst #780 = IDIV8m
  { 781,	1,	0,	0,	"IDIV8r", 0|(1<<TID::UnmodeledSideEffects), 0xf6000017ULL, ImplicitList12, ImplicitList22, Barriers1, OperandInfo107 },  // Inst #781 = IDIV8r
  { 782,	5,	0,	0,	"ILD_F16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xdf000018ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #782 = ILD_F16m
  { 783,	5,	0,	0,	"ILD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xdb000018ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #783 = ILD_F32m
  { 784,	5,	0,	0,	"ILD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xdf00001dULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #784 = ILD_F64m
  { 785,	6,	1,	0,	"ILD_Fp16m32", 0|(1<<TID::MayLoad), 0x10000ULL, NULL, NULL, NULL, OperandInfo120 },  // Inst #785 = ILD_Fp16m32
  { 786,	6,	1,	0,	"ILD_Fp16m64", 0|(1<<TID::MayLoad), 0x10000ULL, NULL, NULL, NULL, OperandInfo121 },  // Inst #786 = ILD_Fp16m64
  { 787,	6,	1,	0,	"ILD_Fp16m80", 0|(1<<TID::MayLoad), 0x10000ULL, NULL, NULL, NULL, OperandInfo122 },  // Inst #787 = ILD_Fp16m80
  { 788,	6,	1,	0,	"ILD_Fp32m32", 0|(1<<TID::MayLoad), 0x10000ULL, NULL, NULL, NULL, OperandInfo120 },  // Inst #788 = ILD_Fp32m32
  { 789,	6,	1,	0,	"ILD_Fp32m64", 0|(1<<TID::MayLoad), 0x10000ULL, NULL, NULL, NULL, OperandInfo121 },  // Inst #789 = ILD_Fp32m64
  { 790,	6,	1,	0,	"ILD_Fp32m80", 0|(1<<TID::MayLoad), 0x10000ULL, NULL, NULL, NULL, OperandInfo122 },  // Inst #790 = ILD_Fp32m80
  { 791,	6,	1,	0,	"ILD_Fp64m32", 0|(1<<TID::MayLoad), 0x10000ULL, NULL, NULL, NULL, OperandInfo120 },  // Inst #791 = ILD_Fp64m32
  { 792,	6,	1,	0,	"ILD_Fp64m64", 0|(1<<TID::MayLoad), 0x10000ULL, NULL, NULL, NULL, OperandInfo121 },  // Inst #792 = ILD_Fp64m64
  { 793,	6,	1,	0,	"ILD_Fp64m80", 0|(1<<TID::MayLoad), 0x10000ULL, NULL, NULL, NULL, OperandInfo122 },  // Inst #793 = ILD_Fp64m80
  { 794,	5,	0,	0,	"IMUL16m", 0|(1<<TID::MayLoad), 0xf700005dULL, ImplicitList12, ImplicitList21, Barriers1, OperandInfo34 },  // Inst #794 = IMUL16m
  { 795,	1,	0,	0,	"IMUL16r", 0, 0xf7000055ULL, ImplicitList12, ImplicitList21, Barriers1, OperandInfo106 },  // Inst #795 = IMUL16r
  { 796,	7,	1,	0,	"IMUL16rm", 0|(1<<TID::MayLoad), 0xaf000146ULL, NULL, ImplicitList1, Barriers1, OperandInfo13 },  // Inst #796 = IMUL16rm
  { 797,	7,	1,	0,	"IMUL16rmi", 0|(1<<TID::MayLoad), 0x69006046ULL, NULL, ImplicitList1, Barriers1, OperandInfo123 },  // Inst #797 = IMUL16rmi
  { 798,	7,	1,	0,	"IMUL16rmi8", 0|(1<<TID::MayLoad), 0x6b002046ULL, NULL, ImplicitList1, Barriers1, OperandInfo123 },  // Inst #798 = IMUL16rmi8
  { 799,	3,	1,	0,	"IMUL16rr", 0|(1<<TID::Commutable), 0xaf000145ULL, NULL, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #799 = IMUL16rr
  { 800,	3,	1,	0,	"IMUL16rri", 0, 0x69006045ULL, NULL, ImplicitList1, Barriers1, OperandInfo124 },  // Inst #800 = IMUL16rri
  { 801,	3,	1,	0,	"IMUL16rri8", 0, 0x6b002045ULL, NULL, ImplicitList1, Barriers1, OperandInfo124 },  // Inst #801 = IMUL16rri8
  { 802,	5,	0,	0,	"IMUL32m", 0|(1<<TID::MayLoad), 0xf700001dULL, ImplicitList13, ImplicitList18, Barriers6, OperandInfo34 },  // Inst #802 = IMUL32m
  { 803,	1,	0,	0,	"IMUL32r", 0, 0xf7000015ULL, ImplicitList13, ImplicitList18, Barriers6, OperandInfo66 },  // Inst #803 = IMUL32r
  { 804,	7,	1,	0,	"IMUL32rm", 0|(1<<TID::MayLoad), 0xaf000106ULL, NULL, ImplicitList1, Barriers1, OperandInfo17 },  // Inst #804 = IMUL32rm
  { 805,	7,	1,	0,	"IMUL32rmi", 0|(1<<TID::MayLoad), 0x6900a006ULL, NULL, ImplicitList1, Barriers1, OperandInfo125 },  // Inst #805 = IMUL32rmi
  { 806,	7,	1,	0,	"IMUL32rmi8", 0|(1<<TID::MayLoad), 0x6b002006ULL, NULL, ImplicitList1, Barriers1, OperandInfo125 },  // Inst #806 = IMUL32rmi8
  { 807,	3,	1,	0,	"IMUL32rr", 0|(1<<TID::Commutable), 0xaf000105ULL, NULL, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #807 = IMUL32rr
  { 808,	3,	1,	0,	"IMUL32rri", 0, 0x6900a005ULL, NULL, ImplicitList1, Barriers1, OperandInfo126 },  // Inst #808 = IMUL32rri
  { 809,	3,	1,	0,	"IMUL32rri8", 0, 0x6b002005ULL, NULL, ImplicitList1, Barriers1, OperandInfo126 },  // Inst #809 = IMUL32rri8
  { 810,	5,	0,	0,	"IMUL64m", 0|(1<<TID::MayLoad), 0xf700101dULL, ImplicitList15, ImplicitList17, Barriers1, OperandInfo34 },  // Inst #810 = IMUL64m
  { 811,	1,	0,	0,	"IMUL64r", 0, 0xf7001015ULL, ImplicitList15, ImplicitList17, Barriers1, OperandInfo67 },  // Inst #811 = IMUL64r
  { 812,	7,	1,	0,	"IMUL64rm", 0|(1<<TID::MayLoad), 0xaf001106ULL, NULL, ImplicitList1, Barriers1, OperandInfo21 },  // Inst #812 = IMUL64rm
  { 813,	7,	1,	0,	"IMUL64rmi32", 0|(1<<TID::MayLoad), 0x6900b006ULL, NULL, ImplicitList1, Barriers1, OperandInfo127 },  // Inst #813 = IMUL64rmi32
  { 814,	7,	1,	0,	"IMUL64rmi8", 0|(1<<TID::MayLoad), 0x6b003006ULL, NULL, ImplicitList1, Barriers1, OperandInfo127 },  // Inst #814 = IMUL64rmi8
  { 815,	3,	1,	0,	"IMUL64rr", 0|(1<<TID::Commutable), 0xaf001105ULL, NULL, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #815 = IMUL64rr
  { 816,	3,	1,	0,	"IMUL64rri32", 0, 0x6900b005ULL, NULL, ImplicitList1, Barriers1, OperandInfo128 },  // Inst #816 = IMUL64rri32
  { 817,	3,	1,	0,	"IMUL64rri8", 0, 0x6b003005ULL, NULL, ImplicitList1, Barriers1, OperandInfo128 },  // Inst #817 = IMUL64rri8
  { 818,	5,	0,	0,	"IMUL8m", 0|(1<<TID::MayLoad), 0xf600001dULL, ImplicitList11, ImplicitList22, Barriers1, OperandInfo34 },  // Inst #818 = IMUL8m
  { 819,	1,	0,	0,	"IMUL8r", 0, 0xf6000015ULL, ImplicitList11, ImplicitList22, Barriers1, OperandInfo107 },  // Inst #819 = IMUL8r
  { 820,	0,	0,	0,	"IN16", 0|(1<<TID::UnmodeledSideEffects), 0x6d000041ULL, NULL, NULL, NULL, 0 },  // Inst #820 = IN16
  { 821,	1,	0,	0,	"IN16ri", 0|(1<<TID::UnmodeledSideEffects), 0xe5002041ULL, NULL, ImplicitList12, NULL, OperandInfo2 },  // Inst #821 = IN16ri
  { 822,	0,	0,	0,	"IN16rr", 0|(1<<TID::UnmodeledSideEffects), 0xed000041ULL, ImplicitList25, ImplicitList12, NULL, 0 },  // Inst #822 = IN16rr
  { 823,	0,	0,	0,	"IN32", 0|(1<<TID::UnmodeledSideEffects), 0x6d000001ULL, NULL, NULL, NULL, 0 },  // Inst #823 = IN32
  { 824,	1,	0,	0,	"IN32ri", 0|(1<<TID::UnmodeledSideEffects), 0xe5002001ULL, NULL, ImplicitList13, NULL, OperandInfo2 },  // Inst #824 = IN32ri
  { 825,	0,	0,	0,	"IN32rr", 0|(1<<TID::UnmodeledSideEffects), 0xed000001ULL, ImplicitList25, ImplicitList13, NULL, 0 },  // Inst #825 = IN32rr
  { 826,	0,	0,	0,	"IN8", 0|(1<<TID::UnmodeledSideEffects), 0x6c000001ULL, NULL, NULL, NULL, 0 },  // Inst #826 = IN8
  { 827,	1,	0,	0,	"IN8ri", 0|(1<<TID::UnmodeledSideEffects), 0xe4002001ULL, NULL, ImplicitList11, NULL, OperandInfo2 },  // Inst #827 = IN8ri
  { 828,	0,	0,	0,	"IN8rr", 0|(1<<TID::UnmodeledSideEffects), 0xec000001ULL, ImplicitList25, ImplicitList11, NULL, 0 },  // Inst #828 = IN8rr
  { 829,	5,	0,	0,	"INC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xff000058ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #829 = INC16m
  { 830,	2,	1,	0,	"INC16r", 0|(1<<TID::ConvertibleTo3Addr), 0x40000042ULL, NULL, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #830 = INC16r
  { 831,	5,	0,	0,	"INC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xff000018ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #831 = INC32m
  { 832,	2,	1,	0,	"INC32r", 0|(1<<TID::ConvertibleTo3Addr), 0x40000002ULL, NULL, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #832 = INC32r
  { 833,	5,	0,	0,	"INC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xff000058ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #833 = INC64_16m
  { 834,	2,	1,	0,	"INC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0xff000050ULL, NULL, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #834 = INC64_16r
  { 835,	5,	0,	0,	"INC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xff000018ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #835 = INC64_32m
  { 836,	2,	1,	0,	"INC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0xff000010ULL, NULL, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #836 = INC64_32r
  { 837,	5,	0,	0,	"INC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xff001018ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #837 = INC64m
  { 838,	2,	1,	0,	"INC64r", 0|(1<<TID::ConvertibleTo3Addr), 0xff001010ULL, NULL, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #838 = INC64r
  { 839,	5,	0,	0,	"INC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xfe000018ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #839 = INC8m
  { 840,	2,	1,	0,	"INC8r", 0, 0xfe000010ULL, NULL, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #840 = INC8r
  { 841,	8,	1,	0,	"INSERTPSrm", 0|(1<<TID::MayLoad), 0x21c02e46ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #841 = INSERTPSrm
  { 842,	4,	1,	0,	"INSERTPSrr", 0, 0x21c02e45ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #842 = INSERTPSrr
  { 843,	1,	0,	0,	"INT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xcd002001ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #843 = INT
  { 844,	0,	0,	0,	"INT3", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xcc000001ULL, NULL, NULL, NULL, 0 },  // Inst #844 = INT3
  { 845,	0,	0,	0,	"INTO", 0|(1<<TID::UnmodeledSideEffects), 0xce000001ULL, ImplicitList1, NULL, NULL, 0 },  // Inst #845 = INTO
  { 846,	0,	0,	0,	"INVD", 0|(1<<TID::UnmodeledSideEffects), 0x8000101ULL, NULL, NULL, NULL, 0 },  // Inst #846 = INVD
  { 847,	0,	0,	0,	"INVEPT", 0|(1<<TID::UnmodeledSideEffects), 0x80000d41ULL, NULL, NULL, NULL, 0 },  // Inst #847 = INVEPT
  { 848,	5,	0,	0,	"INVLPG", 0|(1<<TID::UnmodeledSideEffects), 0x100011fULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #848 = INVLPG
  { 849,	0,	0,	0,	"INVVPID", 0|(1<<TID::UnmodeledSideEffects), 0x81000d41ULL, NULL, NULL, NULL, 0 },  // Inst #849 = INVVPID
  { 850,	0,	0,	0,	"IRET16", 0|(1<<TID::UnmodeledSideEffects), 0xcf000041ULL, NULL, NULL, NULL, 0 },  // Inst #850 = IRET16
  { 851,	0,	0,	0,	"IRET32", 0|(1<<TID::UnmodeledSideEffects), 0xcf000001ULL, NULL, NULL, NULL, 0 },  // Inst #851 = IRET32
  { 852,	0,	0,	0,	"IRET64", 0|(1<<TID::UnmodeledSideEffects), 0xcf001001ULL, NULL, NULL, NULL, 0 },  // Inst #852 = IRET64
  { 853,	5,	0,	0,	"ISTT_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xdf000019ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #853 = ISTT_FP16m
  { 854,	5,	0,	0,	"ISTT_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xdb000019ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #854 = ISTT_FP32m
  { 855,	5,	0,	0,	"ISTT_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xdd000019ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #855 = ISTT_FP64m
  { 856,	6,	0,	0,	"ISTT_Fp16m32", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo110 },  // Inst #856 = ISTT_Fp16m32
  { 857,	6,	0,	0,	"ISTT_Fp16m64", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo111 },  // Inst #857 = ISTT_Fp16m64
  { 858,	6,	0,	0,	"ISTT_Fp16m80", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo112 },  // Inst #858 = ISTT_Fp16m80
  { 859,	6,	0,	0,	"ISTT_Fp32m32", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo110 },  // Inst #859 = ISTT_Fp32m32
  { 860,	6,	0,	0,	"ISTT_Fp32m64", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo111 },  // Inst #860 = ISTT_Fp32m64
  { 861,	6,	0,	0,	"ISTT_Fp32m80", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo112 },  // Inst #861 = ISTT_Fp32m80
  { 862,	6,	0,	0,	"ISTT_Fp64m32", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo110 },  // Inst #862 = ISTT_Fp64m32
  { 863,	6,	0,	0,	"ISTT_Fp64m64", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo111 },  // Inst #863 = ISTT_Fp64m64
  { 864,	6,	0,	0,	"ISTT_Fp64m80", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo112 },  // Inst #864 = ISTT_Fp64m80
  { 865,	5,	0,	0,	"IST_F16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xdf00001aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #865 = IST_F16m
  { 866,	5,	0,	0,	"IST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xdb00001aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #866 = IST_F32m
  { 867,	5,	0,	0,	"IST_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xdf00001bULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #867 = IST_FP16m
  { 868,	5,	0,	0,	"IST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xdb00001bULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #868 = IST_FP32m
  { 869,	5,	0,	0,	"IST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xdf00001fULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #869 = IST_FP64m
  { 870,	6,	0,	0,	"IST_Fp16m32", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo110 },  // Inst #870 = IST_Fp16m32
  { 871,	6,	0,	0,	"IST_Fp16m64", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo111 },  // Inst #871 = IST_Fp16m64
  { 872,	6,	0,	0,	"IST_Fp16m80", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo112 },  // Inst #872 = IST_Fp16m80
  { 873,	6,	0,	0,	"IST_Fp32m32", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo110 },  // Inst #873 = IST_Fp32m32
  { 874,	6,	0,	0,	"IST_Fp32m64", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo111 },  // Inst #874 = IST_Fp32m64
  { 875,	6,	0,	0,	"IST_Fp32m80", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo112 },  // Inst #875 = IST_Fp32m80
  { 876,	6,	0,	0,	"IST_Fp64m32", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo110 },  // Inst #876 = IST_Fp64m32
  { 877,	6,	0,	0,	"IST_Fp64m64", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo111 },  // Inst #877 = IST_Fp64m64
  { 878,	6,	0,	0,	"IST_Fp64m80", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo112 },  // Inst #878 = IST_Fp64m80
  { 879,	8,	1,	0,	"Int_CMPSDrm", 0|(1<<TID::MayLoad), 0xc2002b06ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #879 = Int_CMPSDrm
  { 880,	4,	1,	0,	"Int_CMPSDrr", 0, 0xc2002b05ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #880 = Int_CMPSDrr
  { 881,	8,	1,	0,	"Int_CMPSSrm", 0|(1<<TID::MayLoad), 0xc2002c06ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #881 = Int_CMPSSrm
  { 882,	4,	1,	0,	"Int_CMPSSrr", 0, 0xc2002c05ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #882 = Int_CMPSSrr
  { 883,	6,	0,	0,	"Int_COMISDrm", 0|(1<<TID::MayLoad), 0x2f800146ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #883 = Int_COMISDrm
  { 884,	2,	0,	0,	"Int_COMISDrr", 0, 0x2f800145ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #884 = Int_COMISDrr
  { 885,	6,	0,	0,	"Int_COMISSrm", 0|(1<<TID::MayLoad), 0x2f400106ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #885 = Int_COMISSrm
  { 886,	2,	0,	0,	"Int_COMISSrr", 0, 0x2f400105ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #886 = Int_COMISSrr
  { 887,	6,	1,	0,	"Int_CVTDQ2PDrm", 0|(1<<TID::MayLoad), 0xe6000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #887 = Int_CVTDQ2PDrm
  { 888,	2,	1,	0,	"Int_CVTDQ2PDrr", 0, 0xe6000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #888 = Int_CVTDQ2PDrr
  { 889,	6,	1,	0,	"Int_CVTDQ2PSrm", 0|(1<<TID::MayLoad), 0x5b000106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #889 = Int_CVTDQ2PSrm
  { 890,	2,	1,	0,	"Int_CVTDQ2PSrr", 0, 0x5b000105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #890 = Int_CVTDQ2PSrr
  { 891,	6,	1,	0,	"Int_CVTPD2DQrm", 0|(1<<TID::MayLoad), 0xe6000b06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #891 = Int_CVTPD2DQrm
  { 892,	2,	1,	0,	"Int_CVTPD2DQrr", 0, 0xe6000b05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #892 = Int_CVTPD2DQrr
  { 893,	6,	1,	0,	"Int_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0x2d800146ULL, NULL, NULL, NULL, OperandInfo129 },  // Inst #893 = Int_CVTPD2PIrm
  { 894,	2,	1,	0,	"Int_CVTPD2PIrr", 0, 0x2d800145ULL, NULL, NULL, NULL, OperandInfo130 },  // Inst #894 = Int_CVTPD2PIrr
  { 895,	6,	1,	0,	"Int_CVTPD2PSrm", 0|(1<<TID::MayLoad), 0x5a800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #895 = Int_CVTPD2PSrm
  { 896,	2,	1,	0,	"Int_CVTPD2PSrr", 0, 0x5a800145ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #896 = Int_CVTPD2PSrr
  { 897,	6,	1,	0,	"Int_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0x2a800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #897 = Int_CVTPI2PDrm
  { 898,	2,	1,	0,	"Int_CVTPI2PDrr", 0, 0x2a800145ULL, NULL, NULL, NULL, OperandInfo131 },  // Inst #898 = Int_CVTPI2PDrr
  { 899,	7,	1,	0,	"Int_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0x2a400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #899 = Int_CVTPI2PSrm
  { 900,	3,	1,	0,	"Int_CVTPI2PSrr", 0, 0x2a400105ULL, NULL, NULL, NULL, OperandInfo132 },  // Inst #900 = Int_CVTPI2PSrr
  { 901,	6,	1,	0,	"Int_CVTPS2DQrm", 0|(1<<TID::MayLoad), 0x5b800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #901 = Int_CVTPS2DQrm
  { 902,	2,	1,	0,	"Int_CVTPS2DQrr", 0, 0x5b800145ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #902 = Int_CVTPS2DQrr
  { 903,	6,	1,	0,	"Int_CVTPS2PDrm", 0|(1<<TID::MayLoad), 0x5a000106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #903 = Int_CVTPS2PDrm
  { 904,	2,	1,	0,	"Int_CVTPS2PDrr", 0, 0x5a000105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #904 = Int_CVTPS2PDrr
  { 905,	6,	1,	0,	"Int_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0x2d400106ULL, NULL, NULL, NULL, OperandInfo129 },  // Inst #905 = Int_CVTPS2PIrm
  { 906,	2,	1,	0,	"Int_CVTPS2PIrr", 0, 0x2d400105ULL, NULL, NULL, NULL, OperandInfo130 },  // Inst #906 = Int_CVTPS2PIrr
  { 907,	6,	1,	0,	"Int_CVTSD2SI64rm", 0|(1<<TID::MayLoad), 0x2d001b06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #907 = Int_CVTSD2SI64rm
  { 908,	2,	1,	0,	"Int_CVTSD2SI64rr", 0, 0x2d001b05ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #908 = Int_CVTSD2SI64rr
  { 909,	6,	1,	0,	"Int_CVTSD2SIrm", 0|(1<<TID::MayLoad), 0x2d000b06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #909 = Int_CVTSD2SIrm
  { 910,	2,	1,	0,	"Int_CVTSD2SIrr", 0, 0x2d000b05ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #910 = Int_CVTSD2SIrr
  { 911,	7,	1,	0,	"Int_CVTSD2SSrm", 0|(1<<TID::MayLoad), 0x5a000c06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #911 = Int_CVTSD2SSrm
  { 912,	3,	1,	0,	"Int_CVTSD2SSrr", 0, 0x5a000c05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #912 = Int_CVTSD2SSrr
  { 913,	7,	1,	0,	"Int_CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0x2a001b06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #913 = Int_CVTSI2SD64rm
  { 914,	3,	1,	0,	"Int_CVTSI2SD64rr", 0, 0x2a001b05ULL, NULL, NULL, NULL, OperandInfo134 },  // Inst #914 = Int_CVTSI2SD64rr
  { 915,	7,	1,	0,	"Int_CVTSI2SDrm", 0|(1<<TID::MayLoad), 0x2a000b06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #915 = Int_CVTSI2SDrm
  { 916,	3,	1,	0,	"Int_CVTSI2SDrr", 0, 0x2a000b05ULL, NULL, NULL, NULL, OperandInfo135 },  // Inst #916 = Int_CVTSI2SDrr
  { 917,	7,	1,	0,	"Int_CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0x2a001c06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #917 = Int_CVTSI2SS64rm
  { 918,	3,	1,	0,	"Int_CVTSI2SS64rr", 0, 0x2a001c05ULL, NULL, NULL, NULL, OperandInfo134 },  // Inst #918 = Int_CVTSI2SS64rr
  { 919,	7,	1,	0,	"Int_CVTSI2SSrm", 0|(1<<TID::MayLoad), 0x2a000c06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #919 = Int_CVTSI2SSrm
  { 920,	3,	1,	0,	"Int_CVTSI2SSrr", 0, 0x2a000c05ULL, NULL, NULL, NULL, OperandInfo135 },  // Inst #920 = Int_CVTSI2SSrr
  { 921,	7,	1,	0,	"Int_CVTSS2SDrm", 0|(1<<TID::MayLoad), 0x5a000c06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #921 = Int_CVTSS2SDrm
  { 922,	3,	1,	0,	"Int_CVTSS2SDrr", 0, 0x5a000c05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #922 = Int_CVTSS2SDrr
  { 923,	6,	1,	0,	"Int_CVTSS2SI64rm", 0|(1<<TID::MayLoad), 0x2d001c06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #923 = Int_CVTSS2SI64rm
  { 924,	2,	1,	0,	"Int_CVTSS2SI64rr", 0, 0x2d001c05ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #924 = Int_CVTSS2SI64rr
  { 925,	6,	1,	0,	"Int_CVTSS2SIrm", 0|(1<<TID::MayLoad), 0x2d000c06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #925 = Int_CVTSS2SIrm
  { 926,	2,	1,	0,	"Int_CVTSS2SIrr", 0, 0x2d000c05ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #926 = Int_CVTSS2SIrr
  { 927,	6,	1,	0,	"Int_CVTTPD2DQrm", 0|(1<<TID::MayLoad), 0xe6800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #927 = Int_CVTTPD2DQrm
  { 928,	2,	1,	0,	"Int_CVTTPD2DQrr", 0, 0xe6800145ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #928 = Int_CVTTPD2DQrr
  { 929,	6,	1,	0,	"Int_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0x2c800146ULL, NULL, NULL, NULL, OperandInfo129 },  // Inst #929 = Int_CVTTPD2PIrm
  { 930,	2,	1,	0,	"Int_CVTTPD2PIrr", 0, 0x2c800145ULL, NULL, NULL, NULL, OperandInfo130 },  // Inst #930 = Int_CVTTPD2PIrr
  { 931,	6,	1,	0,	"Int_CVTTPS2DQrm", 0|(1<<TID::MayLoad), 0x5b000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #931 = Int_CVTTPS2DQrm
  { 932,	2,	1,	0,	"Int_CVTTPS2DQrr", 0, 0x5b000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #932 = Int_CVTTPS2DQrr
  { 933,	6,	1,	0,	"Int_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0x2c400106ULL, NULL, NULL, NULL, OperandInfo129 },  // Inst #933 = Int_CVTTPS2PIrm
  { 934,	2,	1,	0,	"Int_CVTTPS2PIrr", 0, 0x2c400105ULL, NULL, NULL, NULL, OperandInfo130 },  // Inst #934 = Int_CVTTPS2PIrr
  { 935,	6,	1,	0,	"Int_CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0x2c001b06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #935 = Int_CVTTSD2SI64rm
  { 936,	2,	1,	0,	"Int_CVTTSD2SI64rr", 0, 0x2c001b05ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #936 = Int_CVTTSD2SI64rr
  { 937,	6,	1,	0,	"Int_CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0x2c000b06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #937 = Int_CVTTSD2SIrm
  { 938,	2,	1,	0,	"Int_CVTTSD2SIrr", 0, 0x2c000b05ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #938 = Int_CVTTSD2SIrr
  { 939,	6,	1,	0,	"Int_CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0x2c001c06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #939 = Int_CVTTSS2SI64rm
  { 940,	2,	1,	0,	"Int_CVTTSS2SI64rr", 0, 0x2c001c05ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #940 = Int_CVTTSS2SI64rr
  { 941,	6,	1,	0,	"Int_CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0x2c000c06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #941 = Int_CVTTSS2SIrm
  { 942,	2,	1,	0,	"Int_CVTTSS2SIrr", 0, 0x2c000c05ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #942 = Int_CVTTSS2SIrr
  { 943,	0,	0,	0,	"Int_MemBarrier", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, 0 },  // Inst #943 = Int_MemBarrier
  { 944,	1,	0,	0,	"Int_MemBarrierNoSSE64", 0|(1<<TID::UnmodeledSideEffects), 0x9081011ULL, NULL, ImplicitList2, NULL, OperandInfo67 },  // Inst #944 = Int_MemBarrierNoSSE64
  { 945,	6,	0,	0,	"Int_UCOMISDrm", 0|(1<<TID::MayLoad), 0x2e800146ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #945 = Int_UCOMISDrm
  { 946,	2,	0,	0,	"Int_UCOMISDrr", 0, 0x2e800145ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #946 = Int_UCOMISDrr
  { 947,	6,	0,	0,	"Int_UCOMISSrm", 0|(1<<TID::MayLoad), 0x2e400106ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #947 = Int_UCOMISSrm
  { 948,	2,	0,	0,	"Int_UCOMISSrr", 0, 0x2e400105ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #948 = Int_UCOMISSrr
  { 949,	8,	1,	0,	"Int_VCMPSDrm", 0|(1<<TID::MayLoad), 0x5c2002b06ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #949 = Int_VCMPSDrm
  { 950,	4,	1,	0,	"Int_VCMPSDrr", 0, 0x5c2002b05ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #950 = Int_VCMPSDrr
  { 951,	8,	1,	0,	"Int_VCMPSSrm", 0|(1<<TID::MayLoad), 0x5c2002c06ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #951 = Int_VCMPSSrm
  { 952,	4,	1,	0,	"Int_VCMPSSrr", 0, 0x5c2002c05ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #952 = Int_VCMPSSrr
  { 953,	6,	0,	0,	"Int_VCOMISDrm", 0|(1<<TID::MayLoad), 0x12f800046ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #953 = Int_VCOMISDrm
  { 954,	2,	0,	0,	"Int_VCOMISDrr", 0, 0x12f800045ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #954 = Int_VCOMISDrr
  { 955,	6,	0,	0,	"Int_VCOMISSrm", 0|(1<<TID::MayLoad), 0x12f400006ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #955 = Int_VCOMISSrm
  { 956,	2,	0,	0,	"Int_VCOMISSrr", 0, 0x12f400005ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #956 = Int_VCOMISSrr
  { 957,	6,	1,	0,	"Int_VCVTDQ2PDrm", 0|(1<<TID::MayLoad), 0x1e6000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #957 = Int_VCVTDQ2PDrm
  { 958,	2,	1,	0,	"Int_VCVTDQ2PDrr", 0, 0x1e6000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #958 = Int_VCVTDQ2PDrr
  { 959,	6,	1,	0,	"Int_VCVTDQ2PSrm", 0|(1<<TID::MayLoad), 0x15b000106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #959 = Int_VCVTDQ2PSrm
  { 960,	2,	1,	0,	"Int_VCVTDQ2PSrr", 0, 0x15b000105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #960 = Int_VCVTDQ2PSrr
  { 961,	6,	1,	0,	"Int_VCVTPD2DQrm", 0|(1<<TID::MayLoad), 0x1e6000b06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #961 = Int_VCVTPD2DQrm
  { 962,	2,	1,	0,	"Int_VCVTPD2DQrr", 0, 0x1e6000b05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #962 = Int_VCVTPD2DQrr
  { 963,	6,	1,	0,	"Int_VCVTPD2PSrm", 0|(1<<TID::MayLoad), 0x5a800046ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #963 = Int_VCVTPD2PSrm
  { 964,	2,	1,	0,	"Int_VCVTPD2PSrr", 0, 0x5a800045ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #964 = Int_VCVTPD2PSrr
  { 965,	6,	1,	0,	"Int_VCVTPS2DQrm", 0|(1<<TID::MayLoad), 0x15b800046ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #965 = Int_VCVTPS2DQrm
  { 966,	2,	1,	0,	"Int_VCVTPS2DQrr", 0, 0x15b800045ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #966 = Int_VCVTPS2DQrr
  { 967,	6,	1,	0,	"Int_VCVTPS2PDrm", 0|(1<<TID::MayLoad), 0x15a000006ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #967 = Int_VCVTPS2PDrm
  { 968,	2,	1,	0,	"Int_VCVTPS2PDrr", 0, 0x15a000005ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #968 = Int_VCVTPS2PDrr
  { 969,	6,	1,	0,	"Int_VCVTSD2SI64rm", 0|(1<<TID::MayLoad), 0x32d000b06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #969 = Int_VCVTSD2SI64rm
  { 970,	2,	1,	0,	"Int_VCVTSD2SI64rr", 0, 0x32d000b05ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #970 = Int_VCVTSD2SI64rr
  { 971,	6,	1,	0,	"Int_VCVTSD2SIrm", 0|(1<<TID::MayLoad), 0x12d000b06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #971 = Int_VCVTSD2SIrm
  { 972,	2,	1,	0,	"Int_VCVTSD2SIrr", 0, 0x12d000b05ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #972 = Int_VCVTSD2SIrr
  { 973,	7,	1,	0,	"Int_VCVTSD2SSrm", 0|(1<<TID::MayLoad), 0x55a000c06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #973 = Int_VCVTSD2SSrm
  { 974,	3,	1,	0,	"Int_VCVTSD2SSrr", 0, 0x55a000c05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #974 = Int_VCVTSD2SSrr
  { 975,	7,	1,	0,	"Int_VCVTSI2SD64rm", 0|(1<<TID::MayLoad), 0x72a000b06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #975 = Int_VCVTSI2SD64rm
  { 976,	3,	1,	0,	"Int_VCVTSI2SD64rr", 0, 0x72a000b05ULL, NULL, NULL, NULL, OperandInfo139 },  // Inst #976 = Int_VCVTSI2SD64rr
  { 977,	7,	1,	0,	"Int_VCVTSI2SDrm", 0|(1<<TID::MayLoad), 0x52a000b06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #977 = Int_VCVTSI2SDrm
  { 978,	3,	1,	0,	"Int_VCVTSI2SDrr", 0, 0x52a000b05ULL, NULL, NULL, NULL, OperandInfo140 },  // Inst #978 = Int_VCVTSI2SDrr
  { 979,	7,	1,	0,	"Int_VCVTSI2SS64rm", 0|(1<<TID::MayLoad), 0x72a000c06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #979 = Int_VCVTSI2SS64rm
  { 980,	3,	1,	0,	"Int_VCVTSI2SS64rr", 0, 0x72a000c05ULL, NULL, NULL, NULL, OperandInfo139 },  // Inst #980 = Int_VCVTSI2SS64rr
  { 981,	7,	1,	0,	"Int_VCVTSI2SSrm", 0|(1<<TID::MayLoad), 0x52a000c06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #981 = Int_VCVTSI2SSrm
  { 982,	3,	1,	0,	"Int_VCVTSI2SSrr", 0, 0x52a000c05ULL, NULL, NULL, NULL, OperandInfo140 },  // Inst #982 = Int_VCVTSI2SSrr
  { 983,	7,	1,	0,	"Int_VCVTSS2SDrm", 0|(1<<TID::MayLoad), 0x55a000c06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #983 = Int_VCVTSS2SDrm
  { 984,	3,	1,	0,	"Int_VCVTSS2SDrr", 0, 0x55a000c05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #984 = Int_VCVTSS2SDrr
  { 985,	6,	1,	0,	"Int_VCVTSS2SI64rm", 0|(1<<TID::MayLoad), 0x32d000c06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #985 = Int_VCVTSS2SI64rm
  { 986,	2,	1,	0,	"Int_VCVTSS2SI64rr", 0, 0x32d000c05ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #986 = Int_VCVTSS2SI64rr
  { 987,	6,	1,	0,	"Int_VCVTSS2SIrm", 0|(1<<TID::MayLoad), 0x12d000c06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #987 = Int_VCVTSS2SIrm
  { 988,	2,	1,	0,	"Int_VCVTSS2SIrr", 0, 0x12d000c05ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #988 = Int_VCVTSS2SIrr
  { 989,	6,	1,	0,	"Int_VCVTTPD2DQrm", 0|(1<<TID::MayLoad), 0x1e6800046ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #989 = Int_VCVTTPD2DQrm
  { 990,	2,	1,	0,	"Int_VCVTTPD2DQrr", 0, 0x1e6800045ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #990 = Int_VCVTTPD2DQrr
  { 991,	6,	1,	0,	"Int_VCVTTPS2DQrm", 0|(1<<TID::MayLoad), 0x15b000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #991 = Int_VCVTTPS2DQrm
  { 992,	2,	1,	0,	"Int_VCVTTPS2DQrr", 0, 0x15b000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #992 = Int_VCVTTPS2DQrr
  { 993,	6,	1,	0,	"Int_VCVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0x32c000b06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #993 = Int_VCVTTSD2SI64rm
  { 994,	2,	1,	0,	"Int_VCVTTSD2SI64rr", 0, 0x32c000b05ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #994 = Int_VCVTTSD2SI64rr
  { 995,	6,	1,	0,	"Int_VCVTTSD2SIrm", 0|(1<<TID::MayLoad), 0x12c000b06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #995 = Int_VCVTTSD2SIrm
  { 996,	2,	1,	0,	"Int_VCVTTSD2SIrr", 0, 0x12c000b05ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #996 = Int_VCVTTSD2SIrr
  { 997,	6,	1,	0,	"Int_VCVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0x32c000c06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #997 = Int_VCVTTSS2SI64rm
  { 998,	2,	1,	0,	"Int_VCVTTSS2SI64rr", 0, 0x32c000c05ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #998 = Int_VCVTTSS2SI64rr
  { 999,	6,	1,	0,	"Int_VCVTTSS2SIrm", 0|(1<<TID::MayLoad), 0x12c000c06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #999 = Int_VCVTTSS2SIrm
  { 1000,	2,	1,	0,	"Int_VCVTTSS2SIrr", 0, 0x12c000c05ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #1000 = Int_VCVTTSS2SIrr
  { 1001,	6,	0,	0,	"Int_VUCOMISDrm", 0|(1<<TID::MayLoad), 0x12e800046ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #1001 = Int_VUCOMISDrm
  { 1002,	2,	0,	0,	"Int_VUCOMISDrr", 0, 0x12e800045ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #1002 = Int_VUCOMISDrr
  { 1003,	6,	0,	0,	"Int_VUCOMISSrm", 0|(1<<TID::MayLoad), 0x12e400006ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #1003 = Int_VUCOMISSrm
  { 1004,	2,	0,	0,	"Int_VUCOMISSrr", 0, 0x12e400005ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #1004 = Int_VUCOMISSrr
  { 1005,	1,	0,	0,	"JAE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x73004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1005 = JAE_1
  { 1006,	1,	0,	0,	"JAE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8300c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1006 = JAE_4
  { 1007,	1,	0,	0,	"JA_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x77004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1007 = JA_1
  { 1008,	1,	0,	0,	"JA_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8700c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1008 = JA_4
  { 1009,	1,	0,	0,	"JBE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x76004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1009 = JBE_1
  { 1010,	1,	0,	0,	"JBE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8600c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1010 = JBE_4
  { 1011,	1,	0,	0,	"JB_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x72004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1011 = JB_1
  { 1012,	1,	0,	0,	"JB_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8200c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1012 = JB_4
  { 1013,	1,	0,	0,	"JCXZ8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0xe3004001ULL, ImplicitList26, NULL, NULL, OperandInfo2 },  // Inst #1013 = JCXZ8
  { 1014,	1,	0,	0,	"JE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x74004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1014 = JE_1
  { 1015,	1,	0,	0,	"JE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8400c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1015 = JE_4
  { 1016,	1,	0,	0,	"JGE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x7d004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1016 = JGE_1
  { 1017,	1,	0,	0,	"JGE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8d00c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1017 = JGE_4
  { 1018,	1,	0,	0,	"JG_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x7f004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1018 = JG_1
  { 1019,	1,	0,	0,	"JG_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8f00c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1019 = JG_4
  { 1020,	1,	0,	0,	"JLE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x7e004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1020 = JLE_1
  { 1021,	1,	0,	0,	"JLE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8e00c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1021 = JLE_4
  { 1022,	1,	0,	0,	"JL_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x7c004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1022 = JL_1
  { 1023,	1,	0,	0,	"JL_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8c00c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1023 = JL_4
  { 1024,	5,	0,	0,	"JMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0xff00001cULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1024 = JMP32m
  { 1025,	1,	0,	0,	"JMP32r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0xff000014ULL, NULL, NULL, NULL, OperandInfo66 },  // Inst #1025 = JMP32r
  { 1026,	5,	0,	0,	"JMP64m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0xff00001cULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1026 = JMP64m
  { 1027,	1,	0,	0,	"JMP64pcrel32", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0xe9000001ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #1027 = JMP64pcrel32
  { 1028,	1,	0,	0,	"JMP64r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0xff000014ULL, NULL, NULL, NULL, OperandInfo67 },  // Inst #1028 = JMP64r
  { 1029,	1,	0,	0,	"JMP_1", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0xeb004001ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #1029 = JMP_1
  { 1030,	1,	0,	0,	"JMP_4", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0xe900c001ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #1030 = JMP_4
  { 1031,	1,	0,	0,	"JNE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x75004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1031 = JNE_1
  { 1032,	1,	0,	0,	"JNE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8500c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1032 = JNE_4
  { 1033,	1,	0,	0,	"JNO_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x71004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1033 = JNO_1
  { 1034,	1,	0,	0,	"JNO_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8100c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1034 = JNO_4
  { 1035,	1,	0,	0,	"JNP_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x7b004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1035 = JNP_1
  { 1036,	1,	0,	0,	"JNP_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8b00c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1036 = JNP_4
  { 1037,	1,	0,	0,	"JNS_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x79004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1037 = JNS_1
  { 1038,	1,	0,	0,	"JNS_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8900c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1038 = JNS_4
  { 1039,	1,	0,	0,	"JO_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x70004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1039 = JO_1
  { 1040,	1,	0,	0,	"JO_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8000c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1040 = JO_4
  { 1041,	1,	0,	0,	"JP_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x7a004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1041 = JP_1
  { 1042,	1,	0,	0,	"JP_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8a00c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1042 = JP_4
  { 1043,	1,	0,	0,	"JS_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x78004001ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1043 = JS_1
  { 1044,	1,	0,	0,	"JS_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0x8800c101ULL, ImplicitList1, NULL, NULL, OperandInfo2 },  // Inst #1044 = JS_4
  { 1045,	0,	0,	0,	"LAHF", 0, 0x9f000001ULL, ImplicitList1, ImplicitList27, NULL, 0 },  // Inst #1045 = LAHF
  { 1046,	6,	1,	0,	"LAR16rm", 0|(1<<TID::UnmodeledSideEffects), 0x2000146ULL, NULL, NULL, NULL, OperandInfo55 },  // Inst #1046 = LAR16rm
  { 1047,	2,	1,	0,	"LAR16rr", 0|(1<<TID::UnmodeledSideEffects), 0x2000145ULL, NULL, NULL, NULL, OperandInfo56 },  // Inst #1047 = LAR16rr
  { 1048,	6,	1,	0,	"LAR32rm", 0|(1<<TID::UnmodeledSideEffects), 0x2000106ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #1048 = LAR32rm
  { 1049,	2,	1,	0,	"LAR32rr", 0|(1<<TID::UnmodeledSideEffects), 0x2000105ULL, NULL, NULL, NULL, OperandInfo58 },  // Inst #1049 = LAR32rr
  { 1050,	6,	1,	0,	"LAR64rm", 0|(1<<TID::UnmodeledSideEffects), 0x2001106ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1050 = LAR64rm
  { 1051,	2,	1,	0,	"LAR64rr", 0|(1<<TID::UnmodeledSideEffects), 0x2001105ULL, NULL, NULL, NULL, OperandInfo141 },  // Inst #1051 = LAR64rr
  { 1052,	6,	0,	0,	"LCMPXCHG16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xb1080144ULL, ImplicitList12, ImplicitList28, Barriers1, OperandInfo11 },  // Inst #1052 = LCMPXCHG16
  { 1053,	6,	0,	0,	"LCMPXCHG32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xb1080104ULL, ImplicitList13, ImplicitList29, Barriers1, OperandInfo15 },  // Inst #1053 = LCMPXCHG32
  { 1054,	6,	0,	0,	"LCMPXCHG64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xb1081104ULL, ImplicitList15, ImplicitList30, Barriers1, OperandInfo19 },  // Inst #1054 = LCMPXCHG64
  { 1055,	6,	0,	0,	"LCMPXCHG8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xb0080104ULL, ImplicitList11, ImplicitList31, Barriers1, OperandInfo24 },  // Inst #1055 = LCMPXCHG8
  { 1056,	5,	0,	0,	"LCMPXCHG8B", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc7080119ULL, ImplicitList6, ImplicitList18, Barriers6, OperandInfo34 },  // Inst #1056 = LCMPXCHG8B
  { 1057,	6,	1,	0,	"LDDQUrm", 0|(1<<TID::MayLoad), 0xf0800b06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1057 = LDDQUrm
  { 1058,	5,	0,	0,	"LDMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xae40011aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1058 = LDMXCSR
  { 1059,	6,	1,	0,	"LDS16rm", 0|(1<<TID::UnmodeledSideEffects), 0xc5000046ULL, NULL, NULL, NULL, OperandInfo55 },  // Inst #1059 = LDS16rm
  { 1060,	6,	1,	0,	"LDS32rm", 0|(1<<TID::UnmodeledSideEffects), 0xc5000006ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #1060 = LDS32rm
  { 1061,	0,	0,	0,	"LD_F0", 0|(1<<TID::UnmodeledSideEffects), 0xee000401ULL, NULL, NULL, NULL, 0 },  // Inst #1061 = LD_F0
  { 1062,	0,	0,	0,	"LD_F1", 0|(1<<TID::UnmodeledSideEffects), 0xe8000401ULL, NULL, NULL, NULL, 0 },  // Inst #1062 = LD_F1
  { 1063,	5,	0,	0,	"LD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xd9000018ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1063 = LD_F32m
  { 1064,	5,	0,	0,	"LD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xdd000018ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1064 = LD_F64m
  { 1065,	5,	0,	0,	"LD_F80m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xdb00001dULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1065 = LD_F80m
  { 1066,	1,	1,	0,	"LD_Fp032", 0|(1<<TID::Rematerializable), 0x10000ULL, NULL, NULL, NULL, OperandInfo113 },  // Inst #1066 = LD_Fp032
  { 1067,	1,	1,	0,	"LD_Fp064", 0|(1<<TID::Rematerializable), 0x10000ULL, NULL, NULL, NULL, OperandInfo114 },  // Inst #1067 = LD_Fp064
  { 1068,	1,	1,	0,	"LD_Fp080", 0|(1<<TID::Rematerializable), 0x10000ULL, NULL, NULL, NULL, OperandInfo115 },  // Inst #1068 = LD_Fp080
  { 1069,	1,	1,	0,	"LD_Fp132", 0|(1<<TID::Rematerializable), 0x10000ULL, NULL, NULL, NULL, OperandInfo113 },  // Inst #1069 = LD_Fp132
  { 1070,	1,	1,	0,	"LD_Fp164", 0|(1<<TID::Rematerializable), 0x10000ULL, NULL, NULL, NULL, OperandInfo114 },  // Inst #1070 = LD_Fp164
  { 1071,	1,	1,	0,	"LD_Fp180", 0|(1<<TID::Rematerializable), 0x10000ULL, NULL, NULL, NULL, OperandInfo115 },  // Inst #1071 = LD_Fp180
  { 1072,	6,	1,	0,	"LD_Fp32m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10000ULL, NULL, NULL, NULL, OperandInfo120 },  // Inst #1072 = LD_Fp32m
  { 1073,	6,	1,	0,	"LD_Fp32m64", 0|(1<<TID::MayLoad), 0x10000ULL, NULL, NULL, NULL, OperandInfo121 },  // Inst #1073 = LD_Fp32m64
  { 1074,	6,	1,	0,	"LD_Fp32m80", 0|(1<<TID::MayLoad), 0x10000ULL, NULL, NULL, NULL, OperandInfo122 },  // Inst #1074 = LD_Fp32m80
  { 1075,	6,	1,	0,	"LD_Fp64m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x10000ULL, NULL, NULL, NULL, OperandInfo121 },  // Inst #1075 = LD_Fp64m
  { 1076,	6,	1,	0,	"LD_Fp64m80", 0|(1<<TID::MayLoad), 0x10000ULL, NULL, NULL, NULL, OperandInfo122 },  // Inst #1076 = LD_Fp64m80
  { 1077,	6,	1,	0,	"LD_Fp80m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10000ULL, NULL, NULL, NULL, OperandInfo122 },  // Inst #1077 = LD_Fp80m
  { 1078,	1,	0,	0,	"LD_Frr", 0|(1<<TID::UnmodeledSideEffects), 0xc0000402ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #1078 = LD_Frr
  { 1079,	6,	1,	0,	"LEA16r", 0, 0x8d000046ULL, NULL, NULL, NULL, OperandInfo55 },  // Inst #1079 = LEA16r
  { 1080,	6,	1,	0,	"LEA32r", 0|(1<<TID::Rematerializable), 0x8d000006ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #1080 = LEA32r
  { 1081,	6,	1,	0,	"LEA64_32r", 0, 0x8d000006ULL, NULL, NULL, NULL, OperandInfo142 },  // Inst #1081 = LEA64_32r
  { 1082,	6,	1,	0,	"LEA64r", 0|(1<<TID::Rematerializable), 0x8d001006ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1082 = LEA64r
  { 1083,	0,	0,	0,	"LEAVE", 0|(1<<TID::MayLoad), 0xc9000001ULL, ImplicitList32, ImplicitList32, NULL, 0 },  // Inst #1083 = LEAVE
  { 1084,	0,	0,	0,	"LEAVE64", 0|(1<<TID::MayLoad), 0xc9000001ULL, ImplicitList33, ImplicitList33, NULL, 0 },  // Inst #1084 = LEAVE64
  { 1085,	6,	1,	0,	"LES16rm", 0|(1<<TID::UnmodeledSideEffects), 0xc4000046ULL, NULL, NULL, NULL, OperandInfo55 },  // Inst #1085 = LES16rm
  { 1086,	6,	1,	0,	"LES32rm", 0|(1<<TID::UnmodeledSideEffects), 0xc4000006ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #1086 = LES32rm
  { 1087,	0,	0,	0,	"LFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xae000127ULL, NULL, NULL, NULL, 0 },  // Inst #1087 = LFENCE
  { 1088,	6,	1,	0,	"LFS16rm", 0|(1<<TID::UnmodeledSideEffects), 0xb4000146ULL, NULL, NULL, NULL, OperandInfo55 },  // Inst #1088 = LFS16rm
  { 1089,	6,	1,	0,	"LFS32rm", 0|(1<<TID::UnmodeledSideEffects), 0xb4000106ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #1089 = LFS32rm
  { 1090,	6,	1,	0,	"LFS64rm", 0|(1<<TID::UnmodeledSideEffects), 0xb4001106ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1090 = LFS64rm
  { 1091,	5,	0,	0,	"LGDTm", 0|(1<<TID::UnmodeledSideEffects), 0x100011aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1091 = LGDTm
  { 1092,	6,	1,	0,	"LGS16rm", 0|(1<<TID::UnmodeledSideEffects), 0xb5000146ULL, NULL, NULL, NULL, OperandInfo55 },  // Inst #1092 = LGS16rm
  { 1093,	6,	1,	0,	"LGS32rm", 0|(1<<TID::UnmodeledSideEffects), 0xb5000106ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #1093 = LGS32rm
  { 1094,	6,	1,	0,	"LGS64rm", 0|(1<<TID::UnmodeledSideEffects), 0xb5001106ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1094 = LGS64rm
  { 1095,	5,	0,	0,	"LIDTm", 0|(1<<TID::UnmodeledSideEffects), 0x100011bULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1095 = LIDTm
  { 1096,	5,	0,	0,	"LLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0x11aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1096 = LLDT16m
  { 1097,	1,	0,	0,	"LLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0x112ULL, NULL, NULL, NULL, OperandInfo106 },  // Inst #1097 = LLDT16r
  { 1098,	5,	0,	0,	"LMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0x100011eULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1098 = LMSW16m
  { 1099,	1,	0,	0,	"LMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0x1000116ULL, NULL, NULL, NULL, OperandInfo106 },  // Inst #1099 = LMSW16r
  { 1100,	6,	0,	0,	"LOCK_ADD16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x81086018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1100 = LOCK_ADD16mi
  { 1101,	6,	0,	0,	"LOCK_ADD16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x83082058ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1101 = LOCK_ADD16mi8
  { 1102,	6,	0,	0,	"LOCK_ADD16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x1080044ULL, NULL, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #1102 = LOCK_ADD16mr
  { 1103,	6,	0,	0,	"LOCK_ADD32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x8108a018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1103 = LOCK_ADD32mi
  { 1104,	6,	0,	0,	"LOCK_ADD32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x83082018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1104 = LOCK_ADD32mi8
  { 1105,	6,	0,	0,	"LOCK_ADD32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x1080004ULL, NULL, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #1105 = LOCK_ADD32mr
  { 1106,	6,	0,	0,	"LOCK_ADD64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x8108b018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1106 = LOCK_ADD64mi32
  { 1107,	6,	0,	0,	"LOCK_ADD64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x83083018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1107 = LOCK_ADD64mi8
  { 1108,	6,	0,	0,	"LOCK_ADD64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x1081004ULL, NULL, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #1108 = LOCK_ADD64mr
  { 1109,	6,	0,	0,	"LOCK_ADD8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x80082018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1109 = LOCK_ADD8mi
  { 1110,	6,	0,	0,	"LOCK_ADD8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x80004ULL, NULL, ImplicitList1, Barriers1, OperandInfo24 },  // Inst #1110 = LOCK_ADD8mr
  { 1111,	5,	0,	0,	"LOCK_DEC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xff080059ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #1111 = LOCK_DEC16m
  { 1112,	5,	0,	0,	"LOCK_DEC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xff080019ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #1112 = LOCK_DEC32m
  { 1113,	5,	0,	0,	"LOCK_DEC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xff081019ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #1113 = LOCK_DEC64m
  { 1114,	5,	0,	0,	"LOCK_DEC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xfe080019ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #1114 = LOCK_DEC8m
  { 1115,	5,	0,	0,	"LOCK_INC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xff080058ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #1115 = LOCK_INC16m
  { 1116,	5,	0,	0,	"LOCK_INC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xff080018ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #1116 = LOCK_INC32m
  { 1117,	5,	0,	0,	"LOCK_INC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xff081018ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #1117 = LOCK_INC64m
  { 1118,	5,	0,	0,	"LOCK_INC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xfe080018ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #1118 = LOCK_INC8m
  { 1119,	0,	0,	0,	"LOCK_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0xf0000001ULL, NULL, NULL, NULL, 0 },  // Inst #1119 = LOCK_PREFIX
  { 1120,	6,	0,	0,	"LOCK_SUB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x8108605dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1120 = LOCK_SUB16mi
  { 1121,	6,	0,	0,	"LOCK_SUB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x8308205dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1121 = LOCK_SUB16mi8
  { 1122,	6,	0,	0,	"LOCK_SUB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x29080044ULL, NULL, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #1122 = LOCK_SUB16mr
  { 1123,	6,	0,	0,	"LOCK_SUB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x8108a01dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1123 = LOCK_SUB32mi
  { 1124,	6,	0,	0,	"LOCK_SUB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x8308201dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1124 = LOCK_SUB32mi8
  { 1125,	6,	0,	0,	"LOCK_SUB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x29080004ULL, NULL, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #1125 = LOCK_SUB32mr
  { 1126,	6,	0,	0,	"LOCK_SUB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x8108b01dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1126 = LOCK_SUB64mi32
  { 1127,	6,	0,	0,	"LOCK_SUB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x8308301dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1127 = LOCK_SUB64mi8
  { 1128,	6,	0,	0,	"LOCK_SUB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x29081004ULL, NULL, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #1128 = LOCK_SUB64mr
  { 1129,	6,	0,	0,	"LOCK_SUB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x8008201dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1129 = LOCK_SUB8mi
  { 1130,	6,	0,	0,	"LOCK_SUB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x28080004ULL, NULL, ImplicitList1, Barriers1, OperandInfo24 },  // Inst #1130 = LOCK_SUB8mr
  { 1131,	0,	0,	0,	"LODSB", 0|(1<<TID::UnmodeledSideEffects), 0xac000001ULL, NULL, NULL, NULL, 0 },  // Inst #1131 = LODSB
  { 1132,	0,	0,	0,	"LODSD", 0|(1<<TID::UnmodeledSideEffects), 0xad000001ULL, NULL, NULL, NULL, 0 },  // Inst #1132 = LODSD
  { 1133,	0,	0,	0,	"LODSQ", 0|(1<<TID::UnmodeledSideEffects), 0xad001001ULL, NULL, NULL, NULL, 0 },  // Inst #1133 = LODSQ
  { 1134,	0,	0,	0,	"LODSW", 0|(1<<TID::UnmodeledSideEffects), 0xad000041ULL, NULL, NULL, NULL, 0 },  // Inst #1134 = LODSW
  { 1135,	1,	0,	0,	"LOOP", 0|(1<<TID::UnmodeledSideEffects), 0xe2004001ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #1135 = LOOP
  { 1136,	1,	0,	0,	"LOOPE", 0|(1<<TID::UnmodeledSideEffects), 0xe1004001ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #1136 = LOOPE
  { 1137,	1,	0,	0,	"LOOPNE", 0|(1<<TID::UnmodeledSideEffects), 0xe0004001ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #1137 = LOOPNE
  { 1138,	0,	0,	0,	"LRET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0xcb070001ULL, NULL, NULL, NULL, 0 },  // Inst #1138 = LRET
  { 1139,	1,	0,	0,	"LRETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0xca076001ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #1139 = LRETI
  { 1140,	6,	1,	0,	"LSL16rm", 0|(1<<TID::UnmodeledSideEffects), 0x3000146ULL, NULL, NULL, NULL, OperandInfo55 },  // Inst #1140 = LSL16rm
  { 1141,	2,	1,	0,	"LSL16rr", 0|(1<<TID::UnmodeledSideEffects), 0x3000145ULL, NULL, NULL, NULL, OperandInfo56 },  // Inst #1141 = LSL16rr
  { 1142,	6,	1,	0,	"LSL32rm", 0|(1<<TID::UnmodeledSideEffects), 0x3000106ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #1142 = LSL32rm
  { 1143,	2,	1,	0,	"LSL32rr", 0|(1<<TID::UnmodeledSideEffects), 0x3000105ULL, NULL, NULL, NULL, OperandInfo58 },  // Inst #1143 = LSL32rr
  { 1144,	6,	1,	0,	"LSL64rm", 0|(1<<TID::UnmodeledSideEffects), 0x3001106ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1144 = LSL64rm
  { 1145,	2,	1,	0,	"LSL64rr", 0|(1<<TID::UnmodeledSideEffects), 0x3001105ULL, NULL, NULL, NULL, OperandInfo60 },  // Inst #1145 = LSL64rr
  { 1146,	6,	1,	0,	"LSS16rm", 0|(1<<TID::UnmodeledSideEffects), 0xb2000146ULL, NULL, NULL, NULL, OperandInfo55 },  // Inst #1146 = LSS16rm
  { 1147,	6,	1,	0,	"LSS32rm", 0|(1<<TID::UnmodeledSideEffects), 0xb2000106ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #1147 = LSS32rm
  { 1148,	6,	1,	0,	"LSS64rm", 0|(1<<TID::UnmodeledSideEffects), 0xb2001106ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1148 = LSS64rm
  { 1149,	5,	0,	0,	"LTRm", 0|(1<<TID::UnmodeledSideEffects), 0x11bULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1149 = LTRm
  { 1150,	1,	0,	0,	"LTRr", 0|(1<<TID::UnmodeledSideEffects), 0x113ULL, NULL, NULL, NULL, OperandInfo106 },  // Inst #1150 = LTRr
  { 1151,	7,	1,	0,	"LXADD16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc1080146ULL, NULL, ImplicitList1, Barriers1, OperandInfo13 },  // Inst #1151 = LXADD16
  { 1152,	7,	1,	0,	"LXADD32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc1080106ULL, NULL, ImplicitList1, Barriers1, OperandInfo17 },  // Inst #1152 = LXADD32
  { 1153,	7,	1,	0,	"LXADD64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc1081106ULL, NULL, ImplicitList1, Barriers1, OperandInfo21 },  // Inst #1153 = LXADD64
  { 1154,	7,	1,	0,	"LXADD8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc0080106ULL, NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #1154 = LXADD8
  { 1155,	2,	0,	0,	"MASKMOVDQU", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xf7c00145ULL, ImplicitList34, NULL, NULL, OperandInfo43 },  // Inst #1155 = MASKMOVDQU
  { 1156,	2,	0,	0,	"MASKMOVDQU64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xf7c00145ULL, ImplicitList35, NULL, NULL, OperandInfo43 },  // Inst #1156 = MASKMOVDQU64
  { 1157,	7,	1,	0,	"MAXPDrm", 0|(1<<TID::MayLoad), 0x5f800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1157 = MAXPDrm
  { 1158,	7,	1,	0,	"MAXPDrm_Int", 0|(1<<TID::MayLoad), 0x5f800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1158 = MAXPDrm_Int
  { 1159,	3,	1,	0,	"MAXPDrr", 0, 0x5f800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1159 = MAXPDrr
  { 1160,	3,	1,	0,	"MAXPDrr_Int", 0, 0x5f800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1160 = MAXPDrr_Int
  { 1161,	7,	1,	0,	"MAXPSrm", 0|(1<<TID::MayLoad), 0x5f400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1161 = MAXPSrm
  { 1162,	7,	1,	0,	"MAXPSrm_Int", 0|(1<<TID::MayLoad), 0x5f400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1162 = MAXPSrm_Int
  { 1163,	3,	1,	0,	"MAXPSrr", 0, 0x5f400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1163 = MAXPSrr
  { 1164,	3,	1,	0,	"MAXPSrr_Int", 0, 0x5f400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1164 = MAXPSrr_Int
  { 1165,	7,	1,	0,	"MAXSDrm", 0|(1<<TID::MayLoad), 0x5f000b06ULL, NULL, NULL, NULL, OperandInfo30 },  // Inst #1165 = MAXSDrm
  { 1166,	7,	1,	0,	"MAXSDrm_Int", 0|(1<<TID::MayLoad), 0x5f000b06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1166 = MAXSDrm_Int
  { 1167,	3,	1,	0,	"MAXSDrr", 0, 0x5f000b05ULL, NULL, NULL, NULL, OperandInfo31 },  // Inst #1167 = MAXSDrr
  { 1168,	3,	1,	0,	"MAXSDrr_Int", 0, 0x5f000b05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1168 = MAXSDrr_Int
  { 1169,	7,	1,	0,	"MAXSSrm", 0|(1<<TID::MayLoad), 0x5f000c06ULL, NULL, NULL, NULL, OperandInfo32 },  // Inst #1169 = MAXSSrm
  { 1170,	7,	1,	0,	"MAXSSrm_Int", 0|(1<<TID::MayLoad), 0x5f000c06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1170 = MAXSSrm_Int
  { 1171,	3,	1,	0,	"MAXSSrr", 0, 0x5f000c05ULL, NULL, NULL, NULL, OperandInfo33 },  // Inst #1171 = MAXSSrr
  { 1172,	3,	1,	0,	"MAXSSrr_Int", 0, 0x5f000c05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1172 = MAXSSrr_Int
  { 1173,	0,	0,	0,	"MFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xae000128ULL, NULL, NULL, NULL, 0 },  // Inst #1173 = MFENCE
  { 1174,	0,	0,	0,	"MINGW_ALLOCA", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList2, ImplicitList36, Barriers1, 0 },  // Inst #1174 = MINGW_ALLOCA
  { 1175,	7,	1,	0,	"MINPDrm", 0|(1<<TID::MayLoad), 0x5d800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1175 = MINPDrm
  { 1176,	7,	1,	0,	"MINPDrm_Int", 0|(1<<TID::MayLoad), 0x5d800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1176 = MINPDrm_Int
  { 1177,	3,	1,	0,	"MINPDrr", 0, 0x5d800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1177 = MINPDrr
  { 1178,	3,	1,	0,	"MINPDrr_Int", 0, 0x5d800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1178 = MINPDrr_Int
  { 1179,	7,	1,	0,	"MINPSrm", 0|(1<<TID::MayLoad), 0x5d400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1179 = MINPSrm
  { 1180,	7,	1,	0,	"MINPSrm_Int", 0|(1<<TID::MayLoad), 0x5d400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1180 = MINPSrm_Int
  { 1181,	3,	1,	0,	"MINPSrr", 0, 0x5d400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1181 = MINPSrr
  { 1182,	3,	1,	0,	"MINPSrr_Int", 0, 0x5d400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1182 = MINPSrr_Int
  { 1183,	7,	1,	0,	"MINSDrm", 0|(1<<TID::MayLoad), 0x5d000b06ULL, NULL, NULL, NULL, OperandInfo30 },  // Inst #1183 = MINSDrm
  { 1184,	7,	1,	0,	"MINSDrm_Int", 0|(1<<TID::MayLoad), 0x5d000b06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1184 = MINSDrm_Int
  { 1185,	3,	1,	0,	"MINSDrr", 0, 0x5d000b05ULL, NULL, NULL, NULL, OperandInfo31 },  // Inst #1185 = MINSDrr
  { 1186,	3,	1,	0,	"MINSDrr_Int", 0, 0x5d000b05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1186 = MINSDrr_Int
  { 1187,	7,	1,	0,	"MINSSrm", 0|(1<<TID::MayLoad), 0x5d000c06ULL, NULL, NULL, NULL, OperandInfo32 },  // Inst #1187 = MINSSrm
  { 1188,	7,	1,	0,	"MINSSrm_Int", 0|(1<<TID::MayLoad), 0x5d000c06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1188 = MINSSrm_Int
  { 1189,	3,	1,	0,	"MINSSrr", 0, 0x5d000c05ULL, NULL, NULL, NULL, OperandInfo33 },  // Inst #1189 = MINSSrr
  { 1190,	3,	1,	0,	"MINSSrr_Int", 0, 0x5d000c05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1190 = MINSSrr_Int
  { 1191,	6,	1,	0,	"MMX_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0x2d000146ULL, NULL, NULL, NULL, OperandInfo129 },  // Inst #1191 = MMX_CVTPD2PIrm
  { 1192,	2,	1,	0,	"MMX_CVTPD2PIrr", 0, 0x2d000145ULL, NULL, NULL, NULL, OperandInfo130 },  // Inst #1192 = MMX_CVTPD2PIrr
  { 1193,	6,	1,	0,	"MMX_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0x2a000146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1193 = MMX_CVTPI2PDrm
  { 1194,	2,	1,	0,	"MMX_CVTPI2PDrr", 0, 0x2a000145ULL, NULL, NULL, NULL, OperandInfo131 },  // Inst #1194 = MMX_CVTPI2PDrr
  { 1195,	6,	1,	0,	"MMX_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0x2a000106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1195 = MMX_CVTPI2PSrm
  { 1196,	2,	1,	0,	"MMX_CVTPI2PSrr", 0, 0x2a000105ULL, NULL, NULL, NULL, OperandInfo131 },  // Inst #1196 = MMX_CVTPI2PSrr
  { 1197,	6,	1,	0,	"MMX_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0x2d000106ULL, NULL, NULL, NULL, OperandInfo129 },  // Inst #1197 = MMX_CVTPS2PIrm
  { 1198,	2,	1,	0,	"MMX_CVTPS2PIrr", 0, 0x2d000105ULL, NULL, NULL, NULL, OperandInfo130 },  // Inst #1198 = MMX_CVTPS2PIrr
  { 1199,	6,	1,	0,	"MMX_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0x2c000146ULL, NULL, NULL, NULL, OperandInfo129 },  // Inst #1199 = MMX_CVTTPD2PIrm
  { 1200,	2,	1,	0,	"MMX_CVTTPD2PIrr", 0, 0x2c000145ULL, NULL, NULL, NULL, OperandInfo130 },  // Inst #1200 = MMX_CVTTPD2PIrr
  { 1201,	6,	1,	0,	"MMX_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0x2c000106ULL, NULL, NULL, NULL, OperandInfo129 },  // Inst #1201 = MMX_CVTTPS2PIrm
  { 1202,	2,	1,	0,	"MMX_CVTTPS2PIrr", 0, 0x2c000105ULL, NULL, NULL, NULL, OperandInfo130 },  // Inst #1202 = MMX_CVTTPS2PIrr
  { 1203,	0,	0,	0,	"MMX_EMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x77000101ULL, NULL, NULL, NULL, 0 },  // Inst #1203 = MMX_EMMS
  { 1204,	0,	0,	0,	"MMX_FEMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xe000101ULL, NULL, NULL, NULL, 0 },  // Inst #1204 = MMX_FEMMS
  { 1205,	2,	0,	0,	"MMX_MASKMOVQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xf7000105ULL, ImplicitList34, NULL, NULL, OperandInfo143 },  // Inst #1205 = MMX_MASKMOVQ
  { 1206,	2,	0,	0,	"MMX_MASKMOVQ64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xf7000105ULL, ImplicitList35, NULL, NULL, OperandInfo143 },  // Inst #1206 = MMX_MASKMOVQ64
  { 1207,	2,	1,	0,	"MMX_MOVD64from64rr", 0, 0x7e001103ULL, NULL, NULL, NULL, OperandInfo144 },  // Inst #1207 = MMX_MOVD64from64rr
  { 1208,	2,	0,	0,	"MMX_MOVD64grr", 0|(1<<TID::UnmodeledSideEffects), 0x7e000103ULL, NULL, NULL, NULL, OperandInfo145 },  // Inst #1208 = MMX_MOVD64grr
  { 1209,	6,	0,	0,	"MMX_MOVD64mr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x7e000104ULL, NULL, NULL, NULL, OperandInfo146 },  // Inst #1209 = MMX_MOVD64mr
  { 1210,	6,	1,	0,	"MMX_MOVD64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x6e000106ULL, NULL, NULL, NULL, OperandInfo129 },  // Inst #1210 = MMX_MOVD64rm
  { 1211,	2,	1,	0,	"MMX_MOVD64rr", 0, 0x6e000105ULL, NULL, NULL, NULL, OperandInfo147 },  // Inst #1211 = MMX_MOVD64rr
  { 1212,	2,	1,	0,	"MMX_MOVD64rrv164", 0, 0x6e001105ULL, NULL, NULL, NULL, OperandInfo148 },  // Inst #1212 = MMX_MOVD64rrv164
  { 1213,	2,	1,	0,	"MMX_MOVD64to64rr", 0, 0x6e001105ULL, NULL, NULL, NULL, OperandInfo148 },  // Inst #1213 = MMX_MOVD64to64rr
  { 1214,	2,	1,	0,	"MMX_MOVDQ2Qrr", 0, 0xd6002b05ULL, NULL, NULL, NULL, OperandInfo130 },  // Inst #1214 = MMX_MOVDQ2Qrr
  { 1215,	2,	1,	0,	"MMX_MOVFR642Qrr", 0|(1<<TID::UnmodeledSideEffects), 0xd6002b05ULL, NULL, NULL, NULL, OperandInfo149 },  // Inst #1215 = MMX_MOVFR642Qrr
  { 1216,	6,	0,	0,	"MMX_MOVNTQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xe7000104ULL, NULL, NULL, NULL, OperandInfo146 },  // Inst #1216 = MMX_MOVNTQmr
  { 1217,	2,	1,	0,	"MMX_MOVQ2DQrr", 0, 0xd6002c05ULL, NULL, NULL, NULL, OperandInfo131 },  // Inst #1217 = MMX_MOVQ2DQrr
  { 1218,	2,	1,	0,	"MMX_MOVQ2FR64rr", 0, 0xd6002c05ULL, NULL, NULL, NULL, OperandInfo150 },  // Inst #1218 = MMX_MOVQ2FR64rr
  { 1219,	6,	0,	0,	"MMX_MOVQ64mr", 0|(1<<TID::MayStore), 0x7f000104ULL, NULL, NULL, NULL, OperandInfo146 },  // Inst #1219 = MMX_MOVQ64mr
  { 1220,	6,	1,	0,	"MMX_MOVQ64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x6f000106ULL, NULL, NULL, NULL, OperandInfo129 },  // Inst #1220 = MMX_MOVQ64rm
  { 1221,	2,	1,	0,	"MMX_MOVQ64rr", 0, 0x6f000105ULL, NULL, NULL, NULL, OperandInfo143 },  // Inst #1221 = MMX_MOVQ64rr
  { 1222,	6,	1,	0,	"MMX_MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0x6e000106ULL, NULL, NULL, NULL, OperandInfo129 },  // Inst #1222 = MMX_MOVZDI2PDIrm
  { 1223,	2,	1,	0,	"MMX_MOVZDI2PDIrr", 0, 0x6e000105ULL, NULL, NULL, NULL, OperandInfo147 },  // Inst #1223 = MMX_MOVZDI2PDIrr
  { 1224,	7,	1,	0,	"MMX_PACKSSDWrm", 0|(1<<TID::MayLoad), 0x6b000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1224 = MMX_PACKSSDWrm
  { 1225,	3,	1,	0,	"MMX_PACKSSDWrr", 0, 0x6b000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1225 = MMX_PACKSSDWrr
  { 1226,	7,	1,	0,	"MMX_PACKSSWBrm", 0|(1<<TID::MayLoad), 0x63000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1226 = MMX_PACKSSWBrm
  { 1227,	3,	1,	0,	"MMX_PACKSSWBrr", 0, 0x63000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1227 = MMX_PACKSSWBrr
  { 1228,	7,	1,	0,	"MMX_PACKUSWBrm", 0|(1<<TID::MayLoad), 0x67000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1228 = MMX_PACKUSWBrm
  { 1229,	3,	1,	0,	"MMX_PACKUSWBrr", 0, 0x67000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1229 = MMX_PACKUSWBrr
  { 1230,	7,	1,	0,	"MMX_PADDBrm", 0|(1<<TID::MayLoad), 0xfc000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1230 = MMX_PADDBrm
  { 1231,	3,	1,	0,	"MMX_PADDBrr", 0|(1<<TID::Commutable), 0xfc000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1231 = MMX_PADDBrr
  { 1232,	7,	1,	0,	"MMX_PADDDrm", 0|(1<<TID::MayLoad), 0xfe000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1232 = MMX_PADDDrm
  { 1233,	3,	1,	0,	"MMX_PADDDrr", 0|(1<<TID::Commutable), 0xfe000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1233 = MMX_PADDDrr
  { 1234,	7,	1,	0,	"MMX_PADDQrm", 0|(1<<TID::MayLoad), 0xd4000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1234 = MMX_PADDQrm
  { 1235,	3,	1,	0,	"MMX_PADDQrr", 0|(1<<TID::Commutable), 0xd4000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1235 = MMX_PADDQrr
  { 1236,	7,	1,	0,	"MMX_PADDSBrm", 0|(1<<TID::MayLoad), 0xec000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1236 = MMX_PADDSBrm
  { 1237,	3,	1,	0,	"MMX_PADDSBrr", 0|(1<<TID::Commutable), 0xec000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1237 = MMX_PADDSBrr
  { 1238,	7,	1,	0,	"MMX_PADDSWrm", 0|(1<<TID::MayLoad), 0xed000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1238 = MMX_PADDSWrm
  { 1239,	3,	1,	0,	"MMX_PADDSWrr", 0|(1<<TID::Commutable), 0xed000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1239 = MMX_PADDSWrr
  { 1240,	7,	1,	0,	"MMX_PADDUSBrm", 0|(1<<TID::MayLoad), 0xdc000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1240 = MMX_PADDUSBrm
  { 1241,	3,	1,	0,	"MMX_PADDUSBrr", 0|(1<<TID::Commutable), 0xdc000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1241 = MMX_PADDUSBrr
  { 1242,	7,	1,	0,	"MMX_PADDUSWrm", 0|(1<<TID::MayLoad), 0xdd000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1242 = MMX_PADDUSWrm
  { 1243,	3,	1,	0,	"MMX_PADDUSWrr", 0|(1<<TID::Commutable), 0xdd000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1243 = MMX_PADDUSWrr
  { 1244,	7,	1,	0,	"MMX_PADDWrm", 0|(1<<TID::MayLoad), 0xfd000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1244 = MMX_PADDWrm
  { 1245,	3,	1,	0,	"MMX_PADDWrr", 0|(1<<TID::Commutable), 0xfd000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1245 = MMX_PADDWrr
  { 1246,	7,	1,	0,	"MMX_PANDNrm", 0|(1<<TID::MayLoad), 0xdf000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1246 = MMX_PANDNrm
  { 1247,	3,	1,	0,	"MMX_PANDNrr", 0, 0xdf000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1247 = MMX_PANDNrr
  { 1248,	7,	1,	0,	"MMX_PANDrm", 0|(1<<TID::MayLoad), 0xdb000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1248 = MMX_PANDrm
  { 1249,	3,	1,	0,	"MMX_PANDrr", 0|(1<<TID::Commutable), 0xdb000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1249 = MMX_PANDrr
  { 1250,	7,	1,	0,	"MMX_PAVGBrm", 0|(1<<TID::MayLoad), 0xe0000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1250 = MMX_PAVGBrm
  { 1251,	3,	1,	0,	"MMX_PAVGBrr", 0|(1<<TID::Commutable), 0xe0000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1251 = MMX_PAVGBrr
  { 1252,	7,	1,	0,	"MMX_PAVGWrm", 0|(1<<TID::MayLoad), 0xe3000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1252 = MMX_PAVGWrm
  { 1253,	3,	1,	0,	"MMX_PAVGWrr", 0|(1<<TID::Commutable), 0xe3000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1253 = MMX_PAVGWrr
  { 1254,	7,	1,	0,	"MMX_PCMPEQBrm", 0|(1<<TID::MayLoad), 0x74000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1254 = MMX_PCMPEQBrm
  { 1255,	3,	1,	0,	"MMX_PCMPEQBrr", 0, 0x74000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1255 = MMX_PCMPEQBrr
  { 1256,	7,	1,	0,	"MMX_PCMPEQDrm", 0|(1<<TID::MayLoad), 0x76000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1256 = MMX_PCMPEQDrm
  { 1257,	3,	1,	0,	"MMX_PCMPEQDrr", 0, 0x76000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1257 = MMX_PCMPEQDrr
  { 1258,	7,	1,	0,	"MMX_PCMPEQWrm", 0|(1<<TID::MayLoad), 0x75000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1258 = MMX_PCMPEQWrm
  { 1259,	3,	1,	0,	"MMX_PCMPEQWrr", 0, 0x75000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1259 = MMX_PCMPEQWrr
  { 1260,	7,	1,	0,	"MMX_PCMPGTBrm", 0|(1<<TID::MayLoad), 0x64000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1260 = MMX_PCMPGTBrm
  { 1261,	3,	1,	0,	"MMX_PCMPGTBrr", 0, 0x64000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1261 = MMX_PCMPGTBrr
  { 1262,	7,	1,	0,	"MMX_PCMPGTDrm", 0|(1<<TID::MayLoad), 0x66000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1262 = MMX_PCMPGTDrm
  { 1263,	3,	1,	0,	"MMX_PCMPGTDrr", 0, 0x66000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1263 = MMX_PCMPGTDrr
  { 1264,	7,	1,	0,	"MMX_PCMPGTWrm", 0|(1<<TID::MayLoad), 0x65000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1264 = MMX_PCMPGTWrm
  { 1265,	3,	1,	0,	"MMX_PCMPGTWrr", 0, 0x65000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1265 = MMX_PCMPGTWrr
  { 1266,	3,	1,	0,	"MMX_PEXTRWri", 0, 0xc5002105ULL, NULL, NULL, NULL, OperandInfo153 },  // Inst #1266 = MMX_PEXTRWri
  { 1267,	8,	1,	0,	"MMX_PINSRWrmi", 0|(1<<TID::MayLoad), 0xc4002106ULL, NULL, NULL, NULL, OperandInfo154 },  // Inst #1267 = MMX_PINSRWrmi
  { 1268,	4,	1,	0,	"MMX_PINSRWrri", 0, 0xc4002105ULL, NULL, NULL, NULL, OperandInfo155 },  // Inst #1268 = MMX_PINSRWrri
  { 1269,	7,	1,	0,	"MMX_PMADDWDrm", 0|(1<<TID::MayLoad), 0xf5000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1269 = MMX_PMADDWDrm
  { 1270,	3,	1,	0,	"MMX_PMADDWDrr", 0|(1<<TID::Commutable), 0xf5000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1270 = MMX_PMADDWDrr
  { 1271,	7,	1,	0,	"MMX_PMAXSWrm", 0|(1<<TID::MayLoad), 0xee000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1271 = MMX_PMAXSWrm
  { 1272,	3,	1,	0,	"MMX_PMAXSWrr", 0|(1<<TID::Commutable), 0xee000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1272 = MMX_PMAXSWrr
  { 1273,	7,	1,	0,	"MMX_PMAXUBrm", 0|(1<<TID::MayLoad), 0xde000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1273 = MMX_PMAXUBrm
  { 1274,	3,	1,	0,	"MMX_PMAXUBrr", 0|(1<<TID::Commutable), 0xde000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1274 = MMX_PMAXUBrr
  { 1275,	7,	1,	0,	"MMX_PMINSWrm", 0|(1<<TID::MayLoad), 0xea000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1275 = MMX_PMINSWrm
  { 1276,	3,	1,	0,	"MMX_PMINSWrr", 0|(1<<TID::Commutable), 0xea000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1276 = MMX_PMINSWrr
  { 1277,	7,	1,	0,	"MMX_PMINUBrm", 0|(1<<TID::MayLoad), 0xda000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1277 = MMX_PMINUBrm
  { 1278,	3,	1,	0,	"MMX_PMINUBrr", 0|(1<<TID::Commutable), 0xda000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1278 = MMX_PMINUBrr
  { 1279,	2,	1,	0,	"MMX_PMOVMSKBrr", 0, 0xd7000105ULL, NULL, NULL, NULL, OperandInfo145 },  // Inst #1279 = MMX_PMOVMSKBrr
  { 1280,	7,	1,	0,	"MMX_PMULHUWrm", 0|(1<<TID::MayLoad), 0xe4000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1280 = MMX_PMULHUWrm
  { 1281,	3,	1,	0,	"MMX_PMULHUWrr", 0|(1<<TID::Commutable), 0xe4000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1281 = MMX_PMULHUWrr
  { 1282,	7,	1,	0,	"MMX_PMULHWrm", 0|(1<<TID::MayLoad), 0xe5000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1282 = MMX_PMULHWrm
  { 1283,	3,	1,	0,	"MMX_PMULHWrr", 0|(1<<TID::Commutable), 0xe5000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1283 = MMX_PMULHWrr
  { 1284,	7,	1,	0,	"MMX_PMULLWrm", 0|(1<<TID::MayLoad), 0xd5000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1284 = MMX_PMULLWrm
  { 1285,	3,	1,	0,	"MMX_PMULLWrr", 0|(1<<TID::Commutable), 0xd5000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1285 = MMX_PMULLWrr
  { 1286,	7,	1,	0,	"MMX_PMULUDQrm", 0|(1<<TID::MayLoad), 0xf4000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1286 = MMX_PMULUDQrm
  { 1287,	3,	1,	0,	"MMX_PMULUDQrr", 0|(1<<TID::Commutable), 0xf4000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1287 = MMX_PMULUDQrr
  { 1288,	7,	1,	0,	"MMX_PORrm", 0|(1<<TID::MayLoad), 0xeb000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1288 = MMX_PORrm
  { 1289,	3,	1,	0,	"MMX_PORrr", 0|(1<<TID::Commutable), 0xeb000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1289 = MMX_PORrr
  { 1290,	7,	1,	0,	"MMX_PSADBWrm", 0|(1<<TID::MayLoad), 0xf6000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1290 = MMX_PSADBWrm
  { 1291,	3,	1,	0,	"MMX_PSADBWrr", 0|(1<<TID::Commutable), 0xf6000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1291 = MMX_PSADBWrr
  { 1292,	7,	1,	0,	"MMX_PSHUFWmi", 0|(1<<TID::MayLoad), 0x70002106ULL, NULL, NULL, NULL, OperandInfo156 },  // Inst #1292 = MMX_PSHUFWmi
  { 1293,	3,	1,	0,	"MMX_PSHUFWri", 0, 0x70002105ULL, NULL, NULL, NULL, OperandInfo157 },  // Inst #1293 = MMX_PSHUFWri
  { 1294,	3,	1,	0,	"MMX_PSLLDri", 0, 0x72002116ULL, NULL, NULL, NULL, OperandInfo158 },  // Inst #1294 = MMX_PSLLDri
  { 1295,	7,	1,	0,	"MMX_PSLLDrm", 0|(1<<TID::MayLoad), 0xf2000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1295 = MMX_PSLLDrm
  { 1296,	3,	1,	0,	"MMX_PSLLDrr", 0, 0xf2000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1296 = MMX_PSLLDrr
  { 1297,	3,	1,	0,	"MMX_PSLLQri", 0, 0x73002116ULL, NULL, NULL, NULL, OperandInfo158 },  // Inst #1297 = MMX_PSLLQri
  { 1298,	7,	1,	0,	"MMX_PSLLQrm", 0|(1<<TID::MayLoad), 0xf3000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1298 = MMX_PSLLQrm
  { 1299,	3,	1,	0,	"MMX_PSLLQrr", 0, 0xf3000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1299 = MMX_PSLLQrr
  { 1300,	3,	1,	0,	"MMX_PSLLWri", 0, 0x71002116ULL, NULL, NULL, NULL, OperandInfo158 },  // Inst #1300 = MMX_PSLLWri
  { 1301,	7,	1,	0,	"MMX_PSLLWrm", 0|(1<<TID::MayLoad), 0xf1000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1301 = MMX_PSLLWrm
  { 1302,	3,	1,	0,	"MMX_PSLLWrr", 0, 0xf1000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1302 = MMX_PSLLWrr
  { 1303,	3,	1,	0,	"MMX_PSRADri", 0, 0x72002114ULL, NULL, NULL, NULL, OperandInfo158 },  // Inst #1303 = MMX_PSRADri
  { 1304,	7,	1,	0,	"MMX_PSRADrm", 0|(1<<TID::MayLoad), 0xe2000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1304 = MMX_PSRADrm
  { 1305,	3,	1,	0,	"MMX_PSRADrr", 0, 0xe2000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1305 = MMX_PSRADrr
  { 1306,	3,	1,	0,	"MMX_PSRAWri", 0, 0x71002114ULL, NULL, NULL, NULL, OperandInfo158 },  // Inst #1306 = MMX_PSRAWri
  { 1307,	7,	1,	0,	"MMX_PSRAWrm", 0|(1<<TID::MayLoad), 0xe1000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1307 = MMX_PSRAWrm
  { 1308,	3,	1,	0,	"MMX_PSRAWrr", 0, 0xe1000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1308 = MMX_PSRAWrr
  { 1309,	3,	1,	0,	"MMX_PSRLDri", 0, 0x72002112ULL, NULL, NULL, NULL, OperandInfo158 },  // Inst #1309 = MMX_PSRLDri
  { 1310,	7,	1,	0,	"MMX_PSRLDrm", 0|(1<<TID::MayLoad), 0xd2000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1310 = MMX_PSRLDrm
  { 1311,	3,	1,	0,	"MMX_PSRLDrr", 0, 0xd2000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1311 = MMX_PSRLDrr
  { 1312,	3,	1,	0,	"MMX_PSRLQri", 0, 0x73002112ULL, NULL, NULL, NULL, OperandInfo158 },  // Inst #1312 = MMX_PSRLQri
  { 1313,	7,	1,	0,	"MMX_PSRLQrm", 0|(1<<TID::MayLoad), 0xd3000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1313 = MMX_PSRLQrm
  { 1314,	3,	1,	0,	"MMX_PSRLQrr", 0, 0xd3000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1314 = MMX_PSRLQrr
  { 1315,	3,	1,	0,	"MMX_PSRLWri", 0, 0x71002112ULL, NULL, NULL, NULL, OperandInfo158 },  // Inst #1315 = MMX_PSRLWri
  { 1316,	7,	1,	0,	"MMX_PSRLWrm", 0|(1<<TID::MayLoad), 0xd1000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1316 = MMX_PSRLWrm
  { 1317,	3,	1,	0,	"MMX_PSRLWrr", 0, 0xd1000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1317 = MMX_PSRLWrr
  { 1318,	7,	1,	0,	"MMX_PSUBBrm", 0|(1<<TID::MayLoad), 0xf8000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1318 = MMX_PSUBBrm
  { 1319,	3,	1,	0,	"MMX_PSUBBrr", 0, 0xf8000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1319 = MMX_PSUBBrr
  { 1320,	7,	1,	0,	"MMX_PSUBDrm", 0|(1<<TID::MayLoad), 0xfa000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1320 = MMX_PSUBDrm
  { 1321,	3,	1,	0,	"MMX_PSUBDrr", 0, 0xfa000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1321 = MMX_PSUBDrr
  { 1322,	7,	1,	0,	"MMX_PSUBQrm", 0|(1<<TID::MayLoad), 0xfb000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1322 = MMX_PSUBQrm
  { 1323,	3,	1,	0,	"MMX_PSUBQrr", 0, 0xfb000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1323 = MMX_PSUBQrr
  { 1324,	7,	1,	0,	"MMX_PSUBSBrm", 0|(1<<TID::MayLoad), 0xe8000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1324 = MMX_PSUBSBrm
  { 1325,	3,	1,	0,	"MMX_PSUBSBrr", 0, 0xe8000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1325 = MMX_PSUBSBrr
  { 1326,	7,	1,	0,	"MMX_PSUBSWrm", 0|(1<<TID::MayLoad), 0xe9000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1326 = MMX_PSUBSWrm
  { 1327,	3,	1,	0,	"MMX_PSUBSWrr", 0, 0xe9000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1327 = MMX_PSUBSWrr
  { 1328,	7,	1,	0,	"MMX_PSUBUSBrm", 0|(1<<TID::MayLoad), 0xd8000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1328 = MMX_PSUBUSBrm
  { 1329,	3,	1,	0,	"MMX_PSUBUSBrr", 0, 0xd8000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1329 = MMX_PSUBUSBrr
  { 1330,	7,	1,	0,	"MMX_PSUBUSWrm", 0|(1<<TID::MayLoad), 0xd9000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1330 = MMX_PSUBUSWrm
  { 1331,	3,	1,	0,	"MMX_PSUBUSWrr", 0, 0xd9000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1331 = MMX_PSUBUSWrr
  { 1332,	7,	1,	0,	"MMX_PSUBWrm", 0|(1<<TID::MayLoad), 0xf9000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1332 = MMX_PSUBWrm
  { 1333,	3,	1,	0,	"MMX_PSUBWrr", 0, 0xf9000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1333 = MMX_PSUBWrr
  { 1334,	7,	1,	0,	"MMX_PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0x68000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1334 = MMX_PUNPCKHBWrm
  { 1335,	3,	1,	0,	"MMX_PUNPCKHBWrr", 0, 0x68000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1335 = MMX_PUNPCKHBWrr
  { 1336,	7,	1,	0,	"MMX_PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0x6a000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1336 = MMX_PUNPCKHDQrm
  { 1337,	3,	1,	0,	"MMX_PUNPCKHDQrr", 0, 0x6a000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1337 = MMX_PUNPCKHDQrr
  { 1338,	7,	1,	0,	"MMX_PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0x69000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1338 = MMX_PUNPCKHWDrm
  { 1339,	3,	1,	0,	"MMX_PUNPCKHWDrr", 0, 0x69000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1339 = MMX_PUNPCKHWDrr
  { 1340,	7,	1,	0,	"MMX_PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0x60000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1340 = MMX_PUNPCKLBWrm
  { 1341,	3,	1,	0,	"MMX_PUNPCKLBWrr", 0, 0x60000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1341 = MMX_PUNPCKLBWrr
  { 1342,	7,	1,	0,	"MMX_PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0x62000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1342 = MMX_PUNPCKLDQrm
  { 1343,	3,	1,	0,	"MMX_PUNPCKLDQrr", 0, 0x62000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1343 = MMX_PUNPCKLDQrr
  { 1344,	7,	1,	0,	"MMX_PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0x61000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1344 = MMX_PUNPCKLWDrm
  { 1345,	3,	1,	0,	"MMX_PUNPCKLWDrr", 0, 0x61000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1345 = MMX_PUNPCKLWDrr
  { 1346,	7,	1,	0,	"MMX_PXORrm", 0|(1<<TID::MayLoad), 0xef000106ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1346 = MMX_PXORrm
  { 1347,	3,	1,	0,	"MMX_PXORrr", 0|(1<<TID::Commutable), 0xef000105ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1347 = MMX_PXORrr
  { 1348,	1,	1,	0,	"MMX_V_SET0", 0|(1<<TID::Rematerializable), 0xef000120ULL, NULL, NULL, NULL, OperandInfo159 },  // Inst #1348 = MMX_V_SET0
  { 1349,	1,	1,	0,	"MMX_V_SETALLONES", 0|(1<<TID::Rematerializable), 0x76000120ULL, NULL, NULL, NULL, OperandInfo159 },  // Inst #1349 = MMX_V_SETALLONES
  { 1350,	0,	0,	0,	"MONITOR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x1000125ULL, NULL, NULL, NULL, 0 },  // Inst #1350 = MONITOR
  { 1351,	1,	1,	0,	"MOV16ao16", 0|(1<<TID::UnmodeledSideEffects), 0xa300a041ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #1351 = MOV16ao16
  { 1352,	6,	0,	0,	"MOV16mi", 0|(1<<TID::MayStore), 0xc7006058ULL, NULL, NULL, NULL, OperandInfo10 },  // Inst #1352 = MOV16mi
  { 1353,	6,	0,	0,	"MOV16mr", 0|(1<<TID::MayStore), 0x89000044ULL, NULL, NULL, NULL, OperandInfo11 },  // Inst #1353 = MOV16mr
  { 1354,	6,	1,	0,	"MOV16ms", 0|(1<<TID::UnmodeledSideEffects), 0x8c000044ULL, NULL, NULL, NULL, OperandInfo160 },  // Inst #1354 = MOV16ms
  { 1355,	1,	0,	0,	"MOV16o16a", 0|(1<<TID::UnmodeledSideEffects), 0xa100a041ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #1355 = MOV16o16a
  { 1356,	1,	1,	0,	"MOV16r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0x31000060ULL, NULL, ImplicitList1, Barriers1, OperandInfo106 },  // Inst #1356 = MOV16r0
  { 1357,	2,	1,	0,	"MOV16ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0xb8006042ULL, NULL, NULL, NULL, OperandInfo63 },  // Inst #1357 = MOV16ri
  { 1358,	6,	1,	0,	"MOV16rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x8b000046ULL, NULL, NULL, NULL, OperandInfo55 },  // Inst #1358 = MOV16rm
  { 1359,	2,	1,	0,	"MOV16rr", 0, 0x89000043ULL, NULL, NULL, NULL, OperandInfo56 },  // Inst #1359 = MOV16rr
  { 1360,	2,	1,	0,	"MOV16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x8b000045ULL, NULL, NULL, NULL, OperandInfo56 },  // Inst #1360 = MOV16rr_REV
  { 1361,	2,	1,	0,	"MOV16rs", 0|(1<<TID::UnmodeledSideEffects), 0x8c000043ULL, NULL, NULL, NULL, OperandInfo161 },  // Inst #1361 = MOV16rs
  { 1362,	6,	1,	0,	"MOV16sm", 0|(1<<TID::UnmodeledSideEffects), 0x8e000046ULL, NULL, NULL, NULL, OperandInfo162 },  // Inst #1362 = MOV16sm
  { 1363,	2,	1,	0,	"MOV16sr", 0|(1<<TID::UnmodeledSideEffects), 0x8e000045ULL, NULL, NULL, NULL, OperandInfo163 },  // Inst #1363 = MOV16sr
  { 1364,	1,	1,	0,	"MOV32ao32", 0|(1<<TID::UnmodeledSideEffects), 0xa300a001ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #1364 = MOV32ao32
  { 1365,	2,	1,	0,	"MOV32cr", 0|(1<<TID::UnmodeledSideEffects), 0x22000105ULL, NULL, NULL, NULL, OperandInfo164 },  // Inst #1365 = MOV32cr
  { 1366,	2,	1,	0,	"MOV32dr", 0|(1<<TID::UnmodeledSideEffects), 0x23000105ULL, NULL, NULL, NULL, OperandInfo165 },  // Inst #1366 = MOV32dr
  { 1367,	6,	0,	0,	"MOV32mi", 0|(1<<TID::MayStore), 0xc700a018ULL, NULL, NULL, NULL, OperandInfo10 },  // Inst #1367 = MOV32mi
  { 1368,	6,	0,	0,	"MOV32mr", 0|(1<<TID::MayStore), 0x89000004ULL, NULL, NULL, NULL, OperandInfo15 },  // Inst #1368 = MOV32mr
  { 1369,	6,	0,	0,	"MOV32mr_TC", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x89000004ULL, NULL, NULL, NULL, OperandInfo166 },  // Inst #1369 = MOV32mr_TC
  { 1370,	6,	1,	0,	"MOV32ms", 0|(1<<TID::UnmodeledSideEffects), 0x8c000004ULL, NULL, NULL, NULL, OperandInfo160 },  // Inst #1370 = MOV32ms
  { 1371,	1,	0,	0,	"MOV32o32a", 0|(1<<TID::UnmodeledSideEffects), 0xa100a001ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #1371 = MOV32o32a
  { 1372,	1,	1,	0,	"MOV32r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0x31000020ULL, NULL, ImplicitList1, Barriers1, OperandInfo66 },  // Inst #1372 = MOV32r0
  { 1373,	2,	1,	0,	"MOV32rc", 0|(1<<TID::UnmodeledSideEffects), 0x20000103ULL, NULL, NULL, NULL, OperandInfo167 },  // Inst #1373 = MOV32rc
  { 1374,	2,	1,	0,	"MOV32rd", 0|(1<<TID::UnmodeledSideEffects), 0x21000103ULL, NULL, NULL, NULL, OperandInfo168 },  // Inst #1374 = MOV32rd
  { 1375,	2,	1,	0,	"MOV32ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0xb800a002ULL, NULL, NULL, NULL, OperandInfo64 },  // Inst #1375 = MOV32ri
  { 1376,	6,	1,	0,	"MOV32rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x8b000006ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #1376 = MOV32rm
  { 1377,	6,	1,	0,	"MOV32rm_TC", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0x8b000006ULL, NULL, NULL, NULL, OperandInfo169 },  // Inst #1377 = MOV32rm_TC
  { 1378,	2,	1,	0,	"MOV32rr", 0, 0x89000003ULL, NULL, NULL, NULL, OperandInfo58 },  // Inst #1378 = MOV32rr
  { 1379,	2,	1,	0,	"MOV32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x8b000005ULL, NULL, NULL, NULL, OperandInfo58 },  // Inst #1379 = MOV32rr_REV
  { 1380,	2,	1,	0,	"MOV32rr_TC", 0, 0x89000003ULL, NULL, NULL, NULL, OperandInfo170 },  // Inst #1380 = MOV32rr_TC
  { 1381,	2,	1,	0,	"MOV32rs", 0|(1<<TID::UnmodeledSideEffects), 0x8c000003ULL, NULL, NULL, NULL, OperandInfo171 },  // Inst #1381 = MOV32rs
  { 1382,	6,	1,	0,	"MOV32sm", 0|(1<<TID::UnmodeledSideEffects), 0x8e000006ULL, NULL, NULL, NULL, OperandInfo162 },  // Inst #1382 = MOV32sm
  { 1383,	2,	1,	0,	"MOV32sr", 0|(1<<TID::UnmodeledSideEffects), 0x8e000005ULL, NULL, NULL, NULL, OperandInfo172 },  // Inst #1383 = MOV32sr
  { 1384,	6,	1,	0,	"MOV64FSrm", 0|(1<<TID::MayLoad), 0x8b101006ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1384 = MOV64FSrm
  { 1385,	6,	1,	0,	"MOV64GSrm", 0|(1<<TID::MayLoad), 0x8b201006ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1385 = MOV64GSrm
  { 1386,	2,	1,	0,	"MOV64cr", 0|(1<<TID::UnmodeledSideEffects), 0x22000105ULL, NULL, NULL, NULL, OperandInfo173 },  // Inst #1386 = MOV64cr
  { 1387,	2,	1,	0,	"MOV64dr", 0|(1<<TID::UnmodeledSideEffects), 0x23000105ULL, NULL, NULL, NULL, OperandInfo174 },  // Inst #1387 = MOV64dr
  { 1388,	6,	0,	0,	"MOV64mi32", 0|(1<<TID::MayStore), 0xc700b018ULL, NULL, NULL, NULL, OperandInfo10 },  // Inst #1388 = MOV64mi32
  { 1389,	6,	0,	0,	"MOV64mr", 0|(1<<TID::MayStore), 0x89001004ULL, NULL, NULL, NULL, OperandInfo19 },  // Inst #1389 = MOV64mr
  { 1390,	6,	0,	0,	"MOV64mr_TC", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x89001004ULL, NULL, NULL, NULL, OperandInfo175 },  // Inst #1390 = MOV64mr_TC
  { 1391,	6,	1,	0,	"MOV64ms", 0|(1<<TID::UnmodeledSideEffects), 0x8c001004ULL, NULL, NULL, NULL, OperandInfo160 },  // Inst #1391 = MOV64ms
  { 1392,	1,	1,	0,	"MOV64r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0x31000020ULL, NULL, ImplicitList1, Barriers1, OperandInfo67 },  // Inst #1392 = MOV64r0
  { 1393,	2,	1,	0,	"MOV64rc", 0|(1<<TID::UnmodeledSideEffects), 0x20000103ULL, NULL, NULL, NULL, OperandInfo176 },  // Inst #1393 = MOV64rc
  { 1394,	2,	1,	0,	"MOV64rd", 0|(1<<TID::UnmodeledSideEffects), 0x21000103ULL, NULL, NULL, NULL, OperandInfo177 },  // Inst #1394 = MOV64rd
  { 1395,	2,	1,	0,	"MOV64ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0xb800f002ULL, NULL, NULL, NULL, OperandInfo65 },  // Inst #1395 = MOV64ri
  { 1396,	2,	1,	0,	"MOV64ri32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0xc700b010ULL, NULL, NULL, NULL, OperandInfo65 },  // Inst #1396 = MOV64ri32
  { 1397,	2,	1,	0,	"MOV64ri64i32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0xb800a002ULL, NULL, NULL, NULL, OperandInfo65 },  // Inst #1397 = MOV64ri64i32
  { 1398,	2,	1,	0,	"MOV64ri_alt", 0|(1<<TID::UnmodeledSideEffects), 0xb800f002ULL, NULL, NULL, NULL, OperandInfo65 },  // Inst #1398 = MOV64ri_alt
  { 1399,	6,	1,	0,	"MOV64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x8b001006ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1399 = MOV64rm
  { 1400,	6,	1,	0,	"MOV64rm_TC", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0x8b001006ULL, NULL, NULL, NULL, OperandInfo178 },  // Inst #1400 = MOV64rm_TC
  { 1401,	2,	1,	0,	"MOV64rr", 0, 0x89001003ULL, NULL, NULL, NULL, OperandInfo60 },  // Inst #1401 = MOV64rr
  { 1402,	2,	1,	0,	"MOV64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x8b001005ULL, NULL, NULL, NULL, OperandInfo60 },  // Inst #1402 = MOV64rr_REV
  { 1403,	2,	1,	0,	"MOV64rr_TC", 0, 0x89001003ULL, NULL, NULL, NULL, OperandInfo179 },  // Inst #1403 = MOV64rr_TC
  { 1404,	2,	1,	0,	"MOV64rs", 0|(1<<TID::UnmodeledSideEffects), 0x8c001003ULL, NULL, NULL, NULL, OperandInfo180 },  // Inst #1404 = MOV64rs
  { 1405,	6,	1,	0,	"MOV64sm", 0|(1<<TID::UnmodeledSideEffects), 0x8e001006ULL, NULL, NULL, NULL, OperandInfo162 },  // Inst #1405 = MOV64sm
  { 1406,	2,	1,	0,	"MOV64sr", 0|(1<<TID::UnmodeledSideEffects), 0x8e001005ULL, NULL, NULL, NULL, OperandInfo181 },  // Inst #1406 = MOV64sr
  { 1407,	2,	1,	0,	"MOV64toPQIrr", 0, 0x6e801145ULL, NULL, NULL, NULL, OperandInfo182 },  // Inst #1407 = MOV64toPQIrr
  { 1408,	6,	1,	0,	"MOV64toSDrm", 0|(1<<TID::MayLoad), 0x7e400c06ULL, NULL, NULL, NULL, OperandInfo94 },  // Inst #1408 = MOV64toSDrm
  { 1409,	2,	1,	0,	"MOV64toSDrr", 0, 0x6e801145ULL, NULL, NULL, NULL, OperandInfo95 },  // Inst #1409 = MOV64toSDrr
  { 1410,	1,	1,	0,	"MOV8ao8", 0|(1<<TID::UnmodeledSideEffects), 0xa200a001ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #1410 = MOV8ao8
  { 1411,	6,	0,	0,	"MOV8mi", 0|(1<<TID::MayStore), 0xc6002018ULL, NULL, NULL, NULL, OperandInfo10 },  // Inst #1411 = MOV8mi
  { 1412,	6,	0,	0,	"MOV8mr", 0|(1<<TID::MayStore), 0x88000004ULL, NULL, NULL, NULL, OperandInfo24 },  // Inst #1412 = MOV8mr
  { 1413,	6,	0,	0,	"MOV8mr_NOREX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x88000004ULL, NULL, NULL, NULL, OperandInfo183 },  // Inst #1413 = MOV8mr_NOREX
  { 1414,	1,	0,	0,	"MOV8o8a", 0|(1<<TID::UnmodeledSideEffects), 0xa000a001ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #1414 = MOV8o8a
  { 1415,	1,	1,	0,	"MOV8r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0x30000020ULL, NULL, ImplicitList1, Barriers1, OperandInfo107 },  // Inst #1415 = MOV8r0
  { 1416,	2,	1,	0,	"MOV8ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0xb0002002ULL, NULL, NULL, NULL, OperandInfo81 },  // Inst #1416 = MOV8ri
  { 1417,	6,	1,	0,	"MOV8rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x8a000006ULL, NULL, NULL, NULL, OperandInfo82 },  // Inst #1417 = MOV8rm
  { 1418,	6,	1,	0,	"MOV8rm_NOREX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0x8a000006ULL, NULL, NULL, NULL, OperandInfo184 },  // Inst #1418 = MOV8rm_NOREX
  { 1419,	2,	1,	0,	"MOV8rr", 0, 0x88000003ULL, NULL, NULL, NULL, OperandInfo83 },  // Inst #1419 = MOV8rr
  { 1420,	2,	1,	0,	"MOV8rr_NOREX", 0, 0x88000003ULL, NULL, NULL, NULL, OperandInfo185 },  // Inst #1420 = MOV8rr_NOREX
  { 1421,	2,	1,	0,	"MOV8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x8a000005ULL, NULL, NULL, NULL, OperandInfo83 },  // Inst #1421 = MOV8rr_REV
  { 1422,	6,	0,	0,	"MOVAPDmr", 0|(1<<TID::MayStore), 0x29800144ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1422 = MOVAPDmr
  { 1423,	6,	1,	0,	"MOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x28800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1423 = MOVAPDrm
  { 1424,	2,	1,	0,	"MOVAPDrr", 0, 0x28800145ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1424 = MOVAPDrr
  { 1425,	6,	0,	0,	"MOVAPSmr", 0|(1<<TID::MayStore), 0x29400104ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1425 = MOVAPSmr
  { 1426,	6,	1,	0,	"MOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x28400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1426 = MOVAPSrm
  { 1427,	2,	1,	0,	"MOVAPSrr", 0, 0x28400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1427 = MOVAPSrr
  { 1428,	6,	1,	0,	"MOVDDUPrm", 0|(1<<TID::MayLoad), 0x12800b06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1428 = MOVDDUPrm
  { 1429,	2,	1,	0,	"MOVDDUPrr", 0, 0x12800b05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1429 = MOVDDUPrr
  { 1430,	6,	1,	0,	"MOVDI2PDIrm", 0|(1<<TID::MayLoad), 0x6e800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1430 = MOVDI2PDIrm
  { 1431,	2,	1,	0,	"MOVDI2PDIrr", 0, 0x6e800145ULL, NULL, NULL, NULL, OperandInfo187 },  // Inst #1431 = MOVDI2PDIrr
  { 1432,	6,	1,	0,	"MOVDI2SSrm", 0|(1<<TID::MayLoad), 0x6e800146ULL, NULL, NULL, NULL, OperandInfo92 },  // Inst #1432 = MOVDI2SSrm
  { 1433,	2,	1,	0,	"MOVDI2SSrr", 0, 0x6e800145ULL, NULL, NULL, NULL, OperandInfo98 },  // Inst #1433 = MOVDI2SSrr
  { 1434,	6,	0,	0,	"MOVDQAmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x7fc00144ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1434 = MOVDQAmr
  { 1435,	6,	1,	0,	"MOVDQArm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x6fc00146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1435 = MOVDQArm
  { 1436,	2,	1,	0,	"MOVDQArr", 0, 0x6fc00145ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1436 = MOVDQArr
  { 1437,	6,	0,	0,	"MOVDQUmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x7fc00c04ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1437 = MOVDQUmr
  { 1438,	6,	0,	0,	"MOVDQUmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x7fc00c04ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1438 = MOVDQUmr_Int
  { 1439,	6,	1,	0,	"MOVDQUrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x6fc00c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1439 = MOVDQUrm
  { 1440,	6,	1,	0,	"MOVDQUrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x6fc00c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1440 = MOVDQUrm_Int
  { 1441,	3,	1,	0,	"MOVHLPSrr", 0, 0x12400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1441 = MOVHLPSrr
  { 1442,	6,	0,	0,	"MOVHPDmr", 0|(1<<TID::MayStore), 0x17800144ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1442 = MOVHPDmr
  { 1443,	7,	1,	0,	"MOVHPDrm", 0|(1<<TID::MayLoad), 0x16800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1443 = MOVHPDrm
  { 1444,	6,	0,	0,	"MOVHPSmr", 0|(1<<TID::MayStore), 0x17400104ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1444 = MOVHPSmr
  { 1445,	7,	1,	0,	"MOVHPSrm", 0|(1<<TID::MayLoad), 0x16400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1445 = MOVHPSrm
  { 1446,	3,	1,	0,	"MOVLHPSrr", 0, 0x16400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1446 = MOVLHPSrr
  { 1447,	6,	0,	0,	"MOVLPDmr", 0|(1<<TID::MayStore), 0x13800144ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1447 = MOVLPDmr
  { 1448,	7,	1,	0,	"MOVLPDrm", 0|(1<<TID::MayLoad), 0x12800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1448 = MOVLPDrm
  { 1449,	6,	0,	0,	"MOVLPSmr", 0|(1<<TID::MayStore), 0x13400104ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1449 = MOVLPSmr
  { 1450,	7,	1,	0,	"MOVLPSrm", 0|(1<<TID::MayLoad), 0x12400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1450 = MOVLPSrm
  { 1451,	6,	0,	0,	"MOVLQ128mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xd6800144ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1451 = MOVLQ128mr
  { 1452,	2,	1,	0,	"MOVMSKPDrr", 0, 0x50800145ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #1452 = MOVMSKPDrr
  { 1453,	2,	1,	0,	"MOVMSKPSrr", 0, 0x50400105ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #1453 = MOVMSKPSrr
  { 1454,	6,	1,	0,	"MOVNTDQArm", 0|(1<<TID::MayLoad), 0x2ac00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1454 = MOVNTDQArm
  { 1455,	6,	0,	0,	"MOVNTDQ_64mr", 0|(1<<TID::MayStore), 0xe7800144ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1455 = MOVNTDQ_64mr
  { 1456,	6,	0,	0,	"MOVNTDQmr", 0|(1<<TID::MayStore), 0xe7c00144ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1456 = MOVNTDQmr
  { 1457,	6,	0,	0,	"MOVNTDQmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xe7c00144ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1457 = MOVNTDQmr_Int
  { 1458,	6,	0,	0,	"MOVNTI_64mr", 0|(1<<TID::MayStore), 0xc3001104ULL, NULL, NULL, NULL, OperandInfo19 },  // Inst #1458 = MOVNTI_64mr
  { 1459,	6,	0,	0,	"MOVNTImr", 0|(1<<TID::MayStore), 0xc3000104ULL, NULL, NULL, NULL, OperandInfo15 },  // Inst #1459 = MOVNTImr
  { 1460,	6,	0,	0,	"MOVNTImr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xc3000104ULL, NULL, NULL, NULL, OperandInfo15 },  // Inst #1460 = MOVNTImr_Int
  { 1461,	6,	0,	0,	"MOVNTPDmr", 0|(1<<TID::MayStore), 0x2b800144ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1461 = MOVNTPDmr
  { 1462,	6,	0,	0,	"MOVNTPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x2b800144ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1462 = MOVNTPDmr_Int
  { 1463,	6,	0,	0,	"MOVNTPSmr", 0|(1<<TID::MayStore), 0x2b400104ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1463 = MOVNTPSmr
  { 1464,	6,	0,	0,	"MOVNTPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x2b400104ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1464 = MOVNTPSmr_Int
  { 1465,	2,	1,	0,	"MOVPC32r", 0|(1<<TID::NotDuplicable), 0xe800a000ULL, ImplicitList2, NULL, NULL, OperandInfo64 },  // Inst #1465 = MOVPC32r
  { 1466,	6,	0,	0,	"MOVPDI2DImr", 0|(1<<TID::MayStore), 0x7e800144ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1466 = MOVPDI2DImr
  { 1467,	2,	1,	0,	"MOVPDI2DIrr", 0, 0x7e800143ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #1467 = MOVPDI2DIrr
  { 1468,	6,	0,	0,	"MOVPQI2QImr", 0|(1<<TID::MayStore), 0xd6800144ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1468 = MOVPQI2QImr
  { 1469,	2,	1,	0,	"MOVPQIto64rr", 0, 0x7e801143ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #1469 = MOVPQIto64rr
  { 1470,	6,	1,	0,	"MOVQI2PQIrm", 0|(1<<TID::MayLoad), 0x7e000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1470 = MOVQI2PQIrm
  { 1471,	2,	1,	0,	"MOVQxrxr", 0|(1<<TID::UnmodeledSideEffects), 0x7e000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1471 = MOVQxrxr
  { 1472,	0,	0,	0,	"MOVSB", 0|(1<<TID::UnmodeledSideEffects), 0xa4000001ULL, ImplicitList37, ImplicitList38, NULL, 0 },  // Inst #1472 = MOVSB
  { 1473,	0,	0,	0,	"MOVSD", 0|(1<<TID::UnmodeledSideEffects), 0xa5000001ULL, ImplicitList37, ImplicitList38, NULL, 0 },  // Inst #1473 = MOVSD
  { 1474,	6,	0,	0,	"MOVSDmr", 0|(1<<TID::MayStore), 0x11000b04ULL, NULL, NULL, NULL, OperandInfo188 },  // Inst #1474 = MOVSDmr
  { 1475,	6,	1,	0,	"MOVSDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x10000b06ULL, NULL, NULL, NULL, OperandInfo94 },  // Inst #1475 = MOVSDrm
  { 1476,	3,	1,	0,	"MOVSDrr", 0, 0x10000b05ULL, NULL, NULL, NULL, OperandInfo189 },  // Inst #1476 = MOVSDrr
  { 1477,	6,	0,	0,	"MOVSDto64mr", 0|(1<<TID::MayStore), 0x7e801144ULL, NULL, NULL, NULL, OperandInfo188 },  // Inst #1477 = MOVSDto64mr
  { 1478,	2,	1,	0,	"MOVSDto64rr", 0, 0x7e801143ULL, NULL, NULL, NULL, OperandInfo102 },  // Inst #1478 = MOVSDto64rr
  { 1479,	6,	1,	0,	"MOVSHDUPrm", 0|(1<<TID::MayLoad), 0x16400c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1479 = MOVSHDUPrm
  { 1480,	2,	1,	0,	"MOVSHDUPrr", 0, 0x16400c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1480 = MOVSHDUPrr
  { 1481,	6,	1,	0,	"MOVSLDUPrm", 0|(1<<TID::MayLoad), 0x12400c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1481 = MOVSLDUPrm
  { 1482,	2,	1,	0,	"MOVSLDUPrr", 0, 0x12400c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1482 = MOVSLDUPrr
  { 1483,	0,	0,	0,	"MOVSQ", 0|(1<<TID::UnmodeledSideEffects), 0xa5001001ULL, ImplicitList37, ImplicitList38, NULL, 0 },  // Inst #1483 = MOVSQ
  { 1484,	6,	0,	0,	"MOVSS2DImr", 0|(1<<TID::MayStore), 0x7e800144ULL, NULL, NULL, NULL, OperandInfo190 },  // Inst #1484 = MOVSS2DImr
  { 1485,	2,	1,	0,	"MOVSS2DIrr", 0, 0x7e800143ULL, NULL, NULL, NULL, OperandInfo101 },  // Inst #1485 = MOVSS2DIrr
  { 1486,	6,	0,	0,	"MOVSSmr", 0|(1<<TID::MayStore), 0x11000c04ULL, NULL, NULL, NULL, OperandInfo190 },  // Inst #1486 = MOVSSmr
  { 1487,	6,	1,	0,	"MOVSSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x10000c06ULL, NULL, NULL, NULL, OperandInfo92 },  // Inst #1487 = MOVSSrm
  { 1488,	3,	1,	0,	"MOVSSrr", 0, 0x10000c05ULL, NULL, NULL, NULL, OperandInfo191 },  // Inst #1488 = MOVSSrr
  { 1489,	0,	0,	0,	"MOVSW", 0|(1<<TID::UnmodeledSideEffects), 0xa5000041ULL, ImplicitList37, ImplicitList38, NULL, 0 },  // Inst #1489 = MOVSW
  { 1490,	6,	1,	0,	"MOVSX16rm8", 0|(1<<TID::MayLoad), 0xbe000106ULL, NULL, NULL, NULL, OperandInfo55 },  // Inst #1490 = MOVSX16rm8
  { 1491,	6,	1,	0,	"MOVSX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0xbe000146ULL, NULL, NULL, NULL, OperandInfo55 },  // Inst #1491 = MOVSX16rm8W
  { 1492,	2,	1,	0,	"MOVSX16rr8", 0, 0xbe000105ULL, NULL, NULL, NULL, OperandInfo192 },  // Inst #1492 = MOVSX16rr8
  { 1493,	2,	1,	0,	"MOVSX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0xbe000145ULL, NULL, NULL, NULL, OperandInfo192 },  // Inst #1493 = MOVSX16rr8W
  { 1494,	6,	1,	0,	"MOVSX32rm16", 0|(1<<TID::MayLoad), 0xbf000106ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #1494 = MOVSX32rm16
  { 1495,	6,	1,	0,	"MOVSX32rm8", 0|(1<<TID::MayLoad), 0xbe000106ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #1495 = MOVSX32rm8
  { 1496,	2,	1,	0,	"MOVSX32rr16", 0, 0xbf000105ULL, NULL, NULL, NULL, OperandInfo193 },  // Inst #1496 = MOVSX32rr16
  { 1497,	2,	1,	0,	"MOVSX32rr8", 0, 0xbe000105ULL, NULL, NULL, NULL, OperandInfo194 },  // Inst #1497 = MOVSX32rr8
  { 1498,	6,	1,	0,	"MOVSX64rm16", 0|(1<<TID::MayLoad), 0xbf001106ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1498 = MOVSX64rm16
  { 1499,	6,	1,	0,	"MOVSX64rm32", 0|(1<<TID::MayLoad), 0x63001006ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1499 = MOVSX64rm32
  { 1500,	6,	1,	0,	"MOVSX64rm8", 0|(1<<TID::MayLoad), 0xbe001106ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1500 = MOVSX64rm8
  { 1501,	2,	1,	0,	"MOVSX64rr16", 0, 0xbf001105ULL, NULL, NULL, NULL, OperandInfo195 },  // Inst #1501 = MOVSX64rr16
  { 1502,	2,	1,	0,	"MOVSX64rr32", 0, 0x63001005ULL, NULL, NULL, NULL, OperandInfo141 },  // Inst #1502 = MOVSX64rr32
  { 1503,	2,	1,	0,	"MOVSX64rr8", 0, 0xbe001105ULL, NULL, NULL, NULL, OperandInfo196 },  // Inst #1503 = MOVSX64rr8
  { 1504,	6,	0,	0,	"MOVUPDmr", 0|(1<<TID::MayStore), 0x11800144ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1504 = MOVUPDmr
  { 1505,	6,	0,	0,	"MOVUPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x11800144ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1505 = MOVUPDmr_Int
  { 1506,	6,	1,	0,	"MOVUPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1506 = MOVUPDrm
  { 1507,	6,	1,	0,	"MOVUPDrm_Int", 0|(1<<TID::MayLoad), 0x10800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1507 = MOVUPDrm_Int
  { 1508,	2,	1,	0,	"MOVUPDrr", 0, 0x10800145ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1508 = MOVUPDrr
  { 1509,	6,	0,	0,	"MOVUPSmr", 0|(1<<TID::MayStore), 0x11400104ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1509 = MOVUPSmr
  { 1510,	6,	0,	0,	"MOVUPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x11400104ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #1510 = MOVUPSmr_Int
  { 1511,	6,	1,	0,	"MOVUPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x10400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1511 = MOVUPSrm
  { 1512,	6,	1,	0,	"MOVUPSrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x10400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1512 = MOVUPSrm_Int
  { 1513,	2,	1,	0,	"MOVUPSrr", 0, 0x10400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1513 = MOVUPSrr
  { 1514,	6,	1,	0,	"MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0x6e800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1514 = MOVZDI2PDIrm
  { 1515,	2,	1,	0,	"MOVZDI2PDIrr", 0, 0x6e800145ULL, NULL, NULL, NULL, OperandInfo187 },  // Inst #1515 = MOVZDI2PDIrr
  { 1516,	6,	1,	0,	"MOVZPQILo2PQIrm", 0|(1<<TID::MayLoad), 0x7e000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1516 = MOVZPQILo2PQIrm
  { 1517,	2,	1,	0,	"MOVZPQILo2PQIrr", 0, 0x7e000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1517 = MOVZPQILo2PQIrr
  { 1518,	6,	1,	0,	"MOVZQI2PQIrm", 0|(1<<TID::MayLoad), 0x7e000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1518 = MOVZQI2PQIrm
  { 1519,	2,	1,	0,	"MOVZQI2PQIrr", 0, 0x6e801145ULL, NULL, NULL, NULL, OperandInfo182 },  // Inst #1519 = MOVZQI2PQIrr
  { 1520,	6,	1,	0,	"MOVZX16rm8", 0|(1<<TID::MayLoad), 0xb6000106ULL, NULL, NULL, NULL, OperandInfo55 },  // Inst #1520 = MOVZX16rm8
  { 1521,	6,	1,	0,	"MOVZX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0xb6000146ULL, NULL, NULL, NULL, OperandInfo55 },  // Inst #1521 = MOVZX16rm8W
  { 1522,	2,	1,	0,	"MOVZX16rr8", 0, 0xb6000105ULL, NULL, NULL, NULL, OperandInfo192 },  // Inst #1522 = MOVZX16rr8
  { 1523,	2,	1,	0,	"MOVZX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0xb6000145ULL, NULL, NULL, NULL, OperandInfo192 },  // Inst #1523 = MOVZX16rr8W
  { 1524,	6,	1,	0,	"MOVZX32_NOREXrm8", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xb6000106ULL, NULL, NULL, NULL, OperandInfo197 },  // Inst #1524 = MOVZX32_NOREXrm8
  { 1525,	2,	1,	0,	"MOVZX32_NOREXrr8", 0|(1<<TID::UnmodeledSideEffects), 0xb6000105ULL, NULL, NULL, NULL, OperandInfo198 },  // Inst #1525 = MOVZX32_NOREXrr8
  { 1526,	6,	1,	0,	"MOVZX32rm16", 0|(1<<TID::MayLoad), 0xb7000106ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #1526 = MOVZX32rm16
  { 1527,	6,	1,	0,	"MOVZX32rm8", 0|(1<<TID::MayLoad), 0xb6000106ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #1527 = MOVZX32rm8
  { 1528,	2,	1,	0,	"MOVZX32rr16", 0, 0xb7000105ULL, NULL, NULL, NULL, OperandInfo193 },  // Inst #1528 = MOVZX32rr16
  { 1529,	2,	1,	0,	"MOVZX32rr8", 0, 0xb6000105ULL, NULL, NULL, NULL, OperandInfo194 },  // Inst #1529 = MOVZX32rr8
  { 1530,	6,	1,	0,	"MOVZX64rm16", 0|(1<<TID::MayLoad), 0xb7000106ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1530 = MOVZX64rm16
  { 1531,	6,	1,	0,	"MOVZX64rm16_Q", 0|(1<<TID::UnmodeledSideEffects), 0xb7001106ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1531 = MOVZX64rm16_Q
  { 1532,	6,	1,	0,	"MOVZX64rm32", 0|(1<<TID::MayLoad), 0x8b000006ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1532 = MOVZX64rm32
  { 1533,	6,	1,	0,	"MOVZX64rm8", 0|(1<<TID::MayLoad), 0xb6000106ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1533 = MOVZX64rm8
  { 1534,	6,	1,	0,	"MOVZX64rm8_Q", 0|(1<<TID::UnmodeledSideEffects), 0xb6001106ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1534 = MOVZX64rm8_Q
  { 1535,	2,	1,	0,	"MOVZX64rr16", 0, 0xb7000105ULL, NULL, NULL, NULL, OperandInfo195 },  // Inst #1535 = MOVZX64rr16
  { 1536,	2,	1,	0,	"MOVZX64rr16_Q", 0|(1<<TID::UnmodeledSideEffects), 0xb7001105ULL, NULL, NULL, NULL, OperandInfo195 },  // Inst #1536 = MOVZX64rr16_Q
  { 1537,	2,	1,	0,	"MOVZX64rr32", 0, 0x89000003ULL, NULL, NULL, NULL, OperandInfo141 },  // Inst #1537 = MOVZX64rr32
  { 1538,	2,	1,	0,	"MOVZX64rr8", 0, 0xb6000105ULL, NULL, NULL, NULL, OperandInfo196 },  // Inst #1538 = MOVZX64rr8
  { 1539,	2,	1,	0,	"MOVZX64rr8_Q", 0|(1<<TID::UnmodeledSideEffects), 0xb6001105ULL, NULL, NULL, NULL, OperandInfo196 },  // Inst #1539 = MOVZX64rr8_Q
  { 1540,	2,	1,	0,	"MOV_Fp3232", 0, 0x70000ULL, NULL, NULL, NULL, OperandInfo7 },  // Inst #1540 = MOV_Fp3232
  { 1541,	2,	1,	0,	"MOV_Fp3264", 0, 0x70000ULL, NULL, NULL, NULL, OperandInfo199 },  // Inst #1541 = MOV_Fp3264
  { 1542,	2,	1,	0,	"MOV_Fp3280", 0, 0x70000ULL, NULL, NULL, NULL, OperandInfo200 },  // Inst #1542 = MOV_Fp3280
  { 1543,	2,	1,	0,	"MOV_Fp6432", 0, 0x70000ULL, NULL, NULL, NULL, OperandInfo201 },  // Inst #1543 = MOV_Fp6432
  { 1544,	2,	1,	0,	"MOV_Fp6464", 0, 0x70000ULL, NULL, NULL, NULL, OperandInfo8 },  // Inst #1544 = MOV_Fp6464
  { 1545,	2,	1,	0,	"MOV_Fp6480", 0, 0x70000ULL, NULL, NULL, NULL, OperandInfo202 },  // Inst #1545 = MOV_Fp6480
  { 1546,	2,	1,	0,	"MOV_Fp8032", 0, 0x70000ULL, NULL, NULL, NULL, OperandInfo203 },  // Inst #1546 = MOV_Fp8032
  { 1547,	2,	1,	0,	"MOV_Fp8064", 0, 0x70000ULL, NULL, NULL, NULL, OperandInfo204 },  // Inst #1547 = MOV_Fp8064
  { 1548,	2,	1,	0,	"MOV_Fp8080", 0, 0x70000ULL, NULL, NULL, NULL, OperandInfo9 },  // Inst #1548 = MOV_Fp8080
  { 1549,	8,	1,	0,	"MPSADBWrmi", 0|(1<<TID::MayLoad), 0x42c02e46ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #1549 = MPSADBWrmi
  { 1550,	4,	1,	0,	"MPSADBWrri", 0, 0x42c02e45ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #1550 = MPSADBWrri
  { 1551,	5,	0,	0,	"MUL16m", 0|(1<<TID::MayLoad), 0xf700005cULL, ImplicitList12, ImplicitList21, Barriers1, OperandInfo34 },  // Inst #1551 = MUL16m
  { 1552,	1,	0,	0,	"MUL16r", 0, 0xf7000054ULL, ImplicitList12, ImplicitList21, Barriers1, OperandInfo106 },  // Inst #1552 = MUL16r
  { 1553,	5,	0,	0,	"MUL32m", 0|(1<<TID::MayLoad), 0xf700001cULL, ImplicitList13, ImplicitList18, Barriers6, OperandInfo34 },  // Inst #1553 = MUL32m
  { 1554,	1,	0,	0,	"MUL32r", 0, 0xf7000014ULL, ImplicitList13, ImplicitList18, Barriers6, OperandInfo66 },  // Inst #1554 = MUL32r
  { 1555,	5,	0,	0,	"MUL64m", 0|(1<<TID::MayLoad), 0xf700101cULL, ImplicitList15, ImplicitList17, Barriers1, OperandInfo34 },  // Inst #1555 = MUL64m
  { 1556,	1,	0,	0,	"MUL64r", 0, 0xf7001014ULL, ImplicitList15, ImplicitList17, Barriers1, OperandInfo67 },  // Inst #1556 = MUL64r
  { 1557,	5,	0,	0,	"MUL8m", 0|(1<<TID::MayLoad), 0xf600001cULL, ImplicitList11, ImplicitList22, Barriers1, OperandInfo34 },  // Inst #1557 = MUL8m
  { 1558,	1,	0,	0,	"MUL8r", 0, 0xf6000014ULL, ImplicitList11, ImplicitList22, Barriers1, OperandInfo107 },  // Inst #1558 = MUL8r
  { 1559,	7,	1,	0,	"MULPDrm", 0|(1<<TID::MayLoad), 0x59800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1559 = MULPDrm
  { 1560,	3,	1,	0,	"MULPDrr", 0|(1<<TID::Commutable), 0x59800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1560 = MULPDrr
  { 1561,	7,	1,	0,	"MULPSrm", 0|(1<<TID::MayLoad), 0x59400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1561 = MULPSrm
  { 1562,	3,	1,	0,	"MULPSrr", 0|(1<<TID::Commutable), 0x59400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1562 = MULPSrr
  { 1563,	7,	1,	0,	"MULSDrm", 0|(1<<TID::MayLoad), 0x59000b06ULL, NULL, NULL, NULL, OperandInfo30 },  // Inst #1563 = MULSDrm
  { 1564,	7,	1,	0,	"MULSDrm_Int", 0|(1<<TID::MayLoad), 0x59000b06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1564 = MULSDrm_Int
  { 1565,	3,	1,	0,	"MULSDrr", 0|(1<<TID::Commutable), 0x59000b05ULL, NULL, NULL, NULL, OperandInfo31 },  // Inst #1565 = MULSDrr
  { 1566,	3,	1,	0,	"MULSDrr_Int", 0, 0x59000b05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1566 = MULSDrr_Int
  { 1567,	7,	1,	0,	"MULSSrm", 0|(1<<TID::MayLoad), 0x59000c06ULL, NULL, NULL, NULL, OperandInfo32 },  // Inst #1567 = MULSSrm
  { 1568,	7,	1,	0,	"MULSSrm_Int", 0|(1<<TID::MayLoad), 0x59000c06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1568 = MULSSrm_Int
  { 1569,	3,	1,	0,	"MULSSrr", 0|(1<<TID::Commutable), 0x59000c05ULL, NULL, NULL, NULL, OperandInfo33 },  // Inst #1569 = MULSSrr
  { 1570,	3,	1,	0,	"MULSSrr_Int", 0, 0x59000c05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1570 = MULSSrr_Int
  { 1571,	5,	0,	0,	"MUL_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xd8000019ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1571 = MUL_F32m
  { 1572,	5,	0,	0,	"MUL_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xdc000019ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1572 = MUL_F64m
  { 1573,	5,	0,	0,	"MUL_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xde000019ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1573 = MUL_FI16m
  { 1574,	5,	0,	0,	"MUL_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xda000019ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1574 = MUL_FI32m
  { 1575,	1,	0,	0,	"MUL_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0xc8000902ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #1575 = MUL_FPrST0
  { 1576,	1,	0,	0,	"MUL_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0xc8000302ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #1576 = MUL_FST0r
  { 1577,	3,	1,	0,	"MUL_Fp32", 0, 0x40000ULL, NULL, NULL, NULL, OperandInfo36 },  // Inst #1577 = MUL_Fp32
  { 1578,	7,	1,	0,	"MUL_Fp32m", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #1578 = MUL_Fp32m
  { 1579,	3,	1,	0,	"MUL_Fp64", 0, 0x40000ULL, NULL, NULL, NULL, OperandInfo38 },  // Inst #1579 = MUL_Fp64
  { 1580,	7,	1,	0,	"MUL_Fp64m", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #1580 = MUL_Fp64m
  { 1581,	7,	1,	0,	"MUL_Fp64m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #1581 = MUL_Fp64m32
  { 1582,	3,	1,	0,	"MUL_Fp80", 0, 0x40000ULL, NULL, NULL, NULL, OperandInfo40 },  // Inst #1582 = MUL_Fp80
  { 1583,	7,	1,	0,	"MUL_Fp80m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #1583 = MUL_Fp80m32
  { 1584,	7,	1,	0,	"MUL_Fp80m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #1584 = MUL_Fp80m64
  { 1585,	7,	1,	0,	"MUL_FpI16m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #1585 = MUL_FpI16m32
  { 1586,	7,	1,	0,	"MUL_FpI16m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #1586 = MUL_FpI16m64
  { 1587,	7,	1,	0,	"MUL_FpI16m80", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #1587 = MUL_FpI16m80
  { 1588,	7,	1,	0,	"MUL_FpI32m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #1588 = MUL_FpI32m32
  { 1589,	7,	1,	0,	"MUL_FpI32m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #1589 = MUL_FpI32m64
  { 1590,	7,	1,	0,	"MUL_FpI32m80", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #1590 = MUL_FpI32m80
  { 1591,	1,	0,	0,	"MUL_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0xc8000702ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #1591 = MUL_FrST0
  { 1592,	0,	0,	0,	"MWAIT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x1000126ULL, NULL, NULL, NULL, 0 },  // Inst #1592 = MWAIT
  { 1593,	5,	0,	0,	"NEG16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xf700005bULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #1593 = NEG16m
  { 1594,	2,	1,	0,	"NEG16r", 0, 0xf7000053ULL, NULL, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #1594 = NEG16r
  { 1595,	5,	0,	0,	"NEG32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xf700001bULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #1595 = NEG32m
  { 1596,	2,	1,	0,	"NEG32r", 0, 0xf7000013ULL, NULL, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #1596 = NEG32r
  { 1597,	5,	0,	0,	"NEG64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xf700101bULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #1597 = NEG64m
  { 1598,	2,	1,	0,	"NEG64r", 0, 0xf7001013ULL, NULL, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #1598 = NEG64r
  { 1599,	5,	0,	0,	"NEG8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xf600001bULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #1599 = NEG8m
  { 1600,	2,	1,	0,	"NEG8r", 0, 0xf6000013ULL, NULL, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #1600 = NEG8r
  { 1601,	0,	0,	0,	"NOOP", 0, 0x90000001ULL, NULL, NULL, NULL, 0 },  // Inst #1601 = NOOP
  { 1602,	5,	0,	0,	"NOOPL", 0, 0x1f000118ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1602 = NOOPL
  { 1603,	5,	0,	0,	"NOOPW", 0, 0x1f000158ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1603 = NOOPW
  { 1604,	5,	0,	0,	"NOT16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xf700005aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1604 = NOT16m
  { 1605,	2,	1,	0,	"NOT16r", 0, 0xf7000052ULL, NULL, NULL, NULL, OperandInfo104 },  // Inst #1605 = NOT16r
  { 1606,	5,	0,	0,	"NOT32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xf700001aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1606 = NOT32m
  { 1607,	2,	1,	0,	"NOT32r", 0, 0xf7000012ULL, NULL, NULL, NULL, OperandInfo61 },  // Inst #1607 = NOT32r
  { 1608,	5,	0,	0,	"NOT64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xf700101aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1608 = NOT64m
  { 1609,	2,	1,	0,	"NOT64r", 0, 0xf7001012ULL, NULL, NULL, NULL, OperandInfo62 },  // Inst #1609 = NOT64r
  { 1610,	5,	0,	0,	"NOT8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xf600001aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1610 = NOT8m
  { 1611,	2,	1,	0,	"NOT8r", 0, 0xf6000012ULL, NULL, NULL, NULL, OperandInfo105 },  // Inst #1611 = NOT8r
  { 1612,	1,	0,	0,	"OR16i16", 0|(1<<TID::UnmodeledSideEffects), 0xd006041ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #1612 = OR16i16
  { 1613,	6,	0,	0,	"OR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x81006059ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1613 = OR16mi
  { 1614,	6,	0,	0,	"OR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x83002059ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1614 = OR16mi8
  { 1615,	6,	0,	0,	"OR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x9000044ULL, NULL, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #1615 = OR16mr
  { 1616,	3,	1,	0,	"OR16ri", 0, 0x81006051ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #1616 = OR16ri
  { 1617,	3,	1,	0,	"OR16ri8", 0, 0x83002051ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #1617 = OR16ri8
  { 1618,	7,	1,	0,	"OR16rm", 0|(1<<TID::MayLoad), 0xb000046ULL, NULL, ImplicitList1, Barriers1, OperandInfo13 },  // Inst #1618 = OR16rm
  { 1619,	3,	1,	0,	"OR16rr", 0|(1<<TID::Commutable), 0x9000043ULL, NULL, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #1619 = OR16rr
  { 1620,	3,	1,	0,	"OR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0xb000045ULL, NULL, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #1620 = OR16rr_REV
  { 1621,	1,	0,	0,	"OR32i32", 0|(1<<TID::UnmodeledSideEffects), 0xd00a001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #1621 = OR32i32
  { 1622,	6,	0,	0,	"OR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100a019ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1622 = OR32mi
  { 1623,	6,	0,	0,	"OR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x83002019ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1623 = OR32mi8
  { 1624,	6,	0,	0,	"OR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x9000004ULL, NULL, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #1624 = OR32mr
  { 1625,	6,	0,	0,	"OR32mrLocked", 0|(1<<TID::UnmodeledSideEffects), 0x9080004ULL, NULL, NULL, NULL, OperandInfo15 },  // Inst #1625 = OR32mrLocked
  { 1626,	3,	1,	0,	"OR32ri", 0, 0x8100a011ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #1626 = OR32ri
  { 1627,	3,	1,	0,	"OR32ri8", 0, 0x83002011ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #1627 = OR32ri8
  { 1628,	7,	1,	0,	"OR32rm", 0|(1<<TID::MayLoad), 0xb000006ULL, NULL, ImplicitList1, Barriers1, OperandInfo17 },  // Inst #1628 = OR32rm
  { 1629,	3,	1,	0,	"OR32rr", 0|(1<<TID::Commutable), 0x9000003ULL, NULL, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #1629 = OR32rr
  { 1630,	3,	1,	0,	"OR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0xb000005ULL, NULL, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #1630 = OR32rr_REV
  { 1631,	1,	0,	0,	"OR64i32", 0|(1<<TID::UnmodeledSideEffects), 0xd00b001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #1631 = OR64i32
  { 1632,	6,	0,	0,	"OR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100b019ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1632 = OR64mi32
  { 1633,	6,	0,	0,	"OR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x83003019ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1633 = OR64mi8
  { 1634,	6,	0,	0,	"OR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x9001004ULL, NULL, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #1634 = OR64mr
  { 1635,	3,	1,	0,	"OR64ri32", 0, 0x8100b011ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #1635 = OR64ri32
  { 1636,	3,	1,	0,	"OR64ri8", 0, 0x83003011ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #1636 = OR64ri8
  { 1637,	7,	1,	0,	"OR64rm", 0|(1<<TID::MayLoad), 0xb001006ULL, NULL, ImplicitList1, Barriers1, OperandInfo21 },  // Inst #1637 = OR64rm
  { 1638,	3,	1,	0,	"OR64rr", 0|(1<<TID::Commutable), 0x9001003ULL, NULL, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #1638 = OR64rr
  { 1639,	3,	1,	0,	"OR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0xb001005ULL, NULL, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #1639 = OR64rr_REV
  { 1640,	1,	0,	0,	"OR8i8", 0|(1<<TID::UnmodeledSideEffects), 0xc002001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #1640 = OR8i8
  { 1641,	6,	0,	0,	"OR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x80002019ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #1641 = OR8mi
  { 1642,	6,	0,	0,	"OR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8000004ULL, NULL, ImplicitList1, Barriers1, OperandInfo24 },  // Inst #1642 = OR8mr
  { 1643,	3,	1,	0,	"OR8ri", 0, 0x80002011ULL, NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #1643 = OR8ri
  { 1644,	7,	1,	0,	"OR8rm", 0|(1<<TID::MayLoad), 0xa000006ULL, NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #1644 = OR8rm
  { 1645,	3,	1,	0,	"OR8rr", 0|(1<<TID::Commutable), 0x8000003ULL, NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #1645 = OR8rr
  { 1646,	3,	1,	0,	"OR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0xa000005ULL, NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #1646 = OR8rr_REV
  { 1647,	7,	1,	0,	"ORPDrm", 0|(1<<TID::MayLoad), 0x56800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1647 = ORPDrm
  { 1648,	3,	1,	0,	"ORPDrr", 0|(1<<TID::Commutable), 0x56800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1648 = ORPDrr
  { 1649,	7,	1,	0,	"ORPSrm", 0|(1<<TID::MayLoad), 0x56400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1649 = ORPSrm
  { 1650,	3,	1,	0,	"ORPSrr", 0|(1<<TID::Commutable), 0x56400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1650 = ORPSrr
  { 1651,	1,	0,	0,	"OUT16ir", 0|(1<<TID::UnmodeledSideEffects), 0xe7002041ULL, ImplicitList12, NULL, NULL, OperandInfo2 },  // Inst #1651 = OUT16ir
  { 1652,	0,	0,	0,	"OUT16rr", 0|(1<<TID::UnmodeledSideEffects), 0xef000041ULL, ImplicitList39, NULL, NULL, 0 },  // Inst #1652 = OUT16rr
  { 1653,	1,	0,	0,	"OUT32ir", 0|(1<<TID::UnmodeledSideEffects), 0xe7002001ULL, ImplicitList13, NULL, NULL, OperandInfo2 },  // Inst #1653 = OUT32ir
  { 1654,	0,	0,	0,	"OUT32rr", 0|(1<<TID::UnmodeledSideEffects), 0xef000001ULL, ImplicitList40, NULL, NULL, 0 },  // Inst #1654 = OUT32rr
  { 1655,	1,	0,	0,	"OUT8ir", 0|(1<<TID::UnmodeledSideEffects), 0xe6002001ULL, ImplicitList11, NULL, NULL, OperandInfo2 },  // Inst #1655 = OUT8ir
  { 1656,	0,	0,	0,	"OUT8rr", 0|(1<<TID::UnmodeledSideEffects), 0xee000001ULL, ImplicitList41, NULL, NULL, 0 },  // Inst #1656 = OUT8rr
  { 1657,	0,	0,	0,	"OUTSB", 0|(1<<TID::UnmodeledSideEffects), 0x6e000001ULL, NULL, NULL, NULL, 0 },  // Inst #1657 = OUTSB
  { 1658,	0,	0,	0,	"OUTSD", 0|(1<<TID::UnmodeledSideEffects), 0x6f000001ULL, NULL, NULL, NULL, 0 },  // Inst #1658 = OUTSD
  { 1659,	0,	0,	0,	"OUTSW", 0|(1<<TID::UnmodeledSideEffects), 0x6f000041ULL, NULL, NULL, NULL, 0 },  // Inst #1659 = OUTSW
  { 1660,	6,	1,	0,	"PABSBrm128", 0|(1<<TID::MayLoad), 0x1cc02d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1660 = PABSBrm128
  { 1661,	6,	1,	0,	"PABSBrm64", 0|(1<<TID::MayLoad), 0x1cc02d06ULL, NULL, NULL, NULL, OperandInfo129 },  // Inst #1661 = PABSBrm64
  { 1662,	2,	1,	0,	"PABSBrr128", 0, 0x1cc02d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1662 = PABSBrr128
  { 1663,	2,	1,	0,	"PABSBrr64", 0, 0x1cc02d05ULL, NULL, NULL, NULL, OperandInfo143 },  // Inst #1663 = PABSBrr64
  { 1664,	6,	1,	0,	"PABSDrm128", 0|(1<<TID::MayLoad), 0x1ec02d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1664 = PABSDrm128
  { 1665,	6,	1,	0,	"PABSDrm64", 0|(1<<TID::MayLoad), 0x1ec02d06ULL, NULL, NULL, NULL, OperandInfo129 },  // Inst #1665 = PABSDrm64
  { 1666,	2,	1,	0,	"PABSDrr128", 0, 0x1ec02d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1666 = PABSDrr128
  { 1667,	2,	1,	0,	"PABSDrr64", 0, 0x1ec02d05ULL, NULL, NULL, NULL, OperandInfo143 },  // Inst #1667 = PABSDrr64
  { 1668,	6,	1,	0,	"PABSWrm128", 0|(1<<TID::MayLoad), 0x1dc02d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1668 = PABSWrm128
  { 1669,	6,	1,	0,	"PABSWrm64", 0|(1<<TID::MayLoad), 0x1dc02d06ULL, NULL, NULL, NULL, OperandInfo129 },  // Inst #1669 = PABSWrm64
  { 1670,	2,	1,	0,	"PABSWrr128", 0, 0x1dc02d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1670 = PABSWrr128
  { 1671,	2,	1,	0,	"PABSWrr64", 0, 0x1dc02d05ULL, NULL, NULL, NULL, OperandInfo143 },  // Inst #1671 = PABSWrr64
  { 1672,	7,	1,	0,	"PACKSSDWrm", 0|(1<<TID::MayLoad), 0x6bc00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1672 = PACKSSDWrm
  { 1673,	3,	1,	0,	"PACKSSDWrr", 0, 0x6bc00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1673 = PACKSSDWrr
  { 1674,	7,	1,	0,	"PACKSSWBrm", 0|(1<<TID::MayLoad), 0x63c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1674 = PACKSSWBrm
  { 1675,	3,	1,	0,	"PACKSSWBrr", 0, 0x63c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1675 = PACKSSWBrr
  { 1676,	7,	1,	0,	"PACKUSDWrm", 0|(1<<TID::MayLoad), 0x2bc00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1676 = PACKUSDWrm
  { 1677,	3,	1,	0,	"PACKUSDWrr", 0, 0x2bc00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1677 = PACKUSDWrr
  { 1678,	7,	1,	0,	"PACKUSWBrm", 0|(1<<TID::MayLoad), 0x67c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1678 = PACKUSWBrm
  { 1679,	3,	1,	0,	"PACKUSWBrr", 0, 0x67c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1679 = PACKUSWBrr
  { 1680,	7,	1,	0,	"PADDBrm", 0|(1<<TID::MayLoad), 0xfcc00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1680 = PADDBrm
  { 1681,	3,	1,	0,	"PADDBrr", 0|(1<<TID::Commutable), 0xfcc00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1681 = PADDBrr
  { 1682,	7,	1,	0,	"PADDDrm", 0|(1<<TID::MayLoad), 0xfec00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1682 = PADDDrm
  { 1683,	3,	1,	0,	"PADDDrr", 0|(1<<TID::Commutable), 0xfec00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1683 = PADDDrr
  { 1684,	7,	1,	0,	"PADDQrm", 0|(1<<TID::MayLoad), 0xd4c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1684 = PADDQrm
  { 1685,	3,	1,	0,	"PADDQrr", 0|(1<<TID::Commutable), 0xd4c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1685 = PADDQrr
  { 1686,	7,	1,	0,	"PADDSBrm", 0|(1<<TID::MayLoad), 0xecc00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1686 = PADDSBrm
  { 1687,	3,	1,	0,	"PADDSBrr", 0|(1<<TID::Commutable), 0xecc00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1687 = PADDSBrr
  { 1688,	7,	1,	0,	"PADDSWrm", 0|(1<<TID::MayLoad), 0xedc00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1688 = PADDSWrm
  { 1689,	3,	1,	0,	"PADDSWrr", 0|(1<<TID::Commutable), 0xedc00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1689 = PADDSWrr
  { 1690,	7,	1,	0,	"PADDUSBrm", 0|(1<<TID::MayLoad), 0xdcc00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1690 = PADDUSBrm
  { 1691,	3,	1,	0,	"PADDUSBrr", 0|(1<<TID::Commutable), 0xdcc00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1691 = PADDUSBrr
  { 1692,	7,	1,	0,	"PADDUSWrm", 0|(1<<TID::MayLoad), 0xddc00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1692 = PADDUSWrm
  { 1693,	3,	1,	0,	"PADDUSWrr", 0|(1<<TID::Commutable), 0xddc00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1693 = PADDUSWrr
  { 1694,	7,	1,	0,	"PADDWrm", 0|(1<<TID::MayLoad), 0xfdc00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1694 = PADDWrm
  { 1695,	3,	1,	0,	"PADDWrr", 0|(1<<TID::Commutable), 0xfdc00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1695 = PADDWrr
  { 1696,	8,	1,	0,	"PALIGNR128rm", 0|(1<<TID::UnmodeledSideEffects), 0xfc02e46ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #1696 = PALIGNR128rm
  { 1697,	4,	1,	0,	"PALIGNR128rr", 0|(1<<TID::UnmodeledSideEffects), 0xfc02e45ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #1697 = PALIGNR128rr
  { 1698,	8,	1,	0,	"PALIGNR64rm", 0|(1<<TID::UnmodeledSideEffects), 0xfc02e06ULL, NULL, NULL, NULL, OperandInfo154 },  // Inst #1698 = PALIGNR64rm
  { 1699,	4,	1,	0,	"PALIGNR64rr", 0|(1<<TID::UnmodeledSideEffects), 0xfc02e05ULL, NULL, NULL, NULL, OperandInfo205 },  // Inst #1699 = PALIGNR64rr
  { 1700,	7,	1,	0,	"PANDNrm", 0|(1<<TID::MayLoad), 0xdfc00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1700 = PANDNrm
  { 1701,	3,	1,	0,	"PANDNrr", 0, 0xdfc00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1701 = PANDNrr
  { 1702,	7,	1,	0,	"PANDrm", 0|(1<<TID::MayLoad), 0xdbc00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1702 = PANDrm
  { 1703,	3,	1,	0,	"PANDrr", 0|(1<<TID::Commutable), 0xdbc00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1703 = PANDrr
  { 1704,	0,	0,	0,	"PAUSE", 0|(1<<TID::UnmodeledSideEffects), 0x90000201ULL, NULL, NULL, NULL, 0 },  // Inst #1704 = PAUSE
  { 1705,	7,	1,	0,	"PAVGBrm", 0|(1<<TID::MayLoad), 0xe0c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1705 = PAVGBrm
  { 1706,	3,	1,	0,	"PAVGBrr", 0|(1<<TID::Commutable), 0xe0c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1706 = PAVGBrr
  { 1707,	7,	1,	0,	"PAVGWrm", 0|(1<<TID::MayLoad), 0xe3c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1707 = PAVGWrm
  { 1708,	3,	1,	0,	"PAVGWrr", 0|(1<<TID::Commutable), 0xe3c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1708 = PAVGWrr
  { 1709,	7,	1,	0,	"PBLENDVBrm0", 0|(1<<TID::MayLoad), 0x10c00d46ULL, ImplicitList8, NULL, NULL, OperandInfo28 },  // Inst #1709 = PBLENDVBrm0
  { 1710,	3,	1,	0,	"PBLENDVBrr0", 0, 0x10c00d45ULL, ImplicitList8, NULL, NULL, OperandInfo29 },  // Inst #1710 = PBLENDVBrr0
  { 1711,	8,	1,	0,	"PBLENDWrmi", 0|(1<<TID::MayLoad), 0xec02e46ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #1711 = PBLENDWrmi
  { 1712,	4,	1,	0,	"PBLENDWrri", 0, 0xec02e45ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #1712 = PBLENDWrri
  { 1713,	7,	1,	0,	"PCMPEQBrm", 0|(1<<TID::MayLoad), 0x74c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1713 = PCMPEQBrm
  { 1714,	3,	1,	0,	"PCMPEQBrr", 0|(1<<TID::Commutable), 0x74c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1714 = PCMPEQBrr
  { 1715,	7,	1,	0,	"PCMPEQDrm", 0|(1<<TID::MayLoad), 0x76c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1715 = PCMPEQDrm
  { 1716,	3,	1,	0,	"PCMPEQDrr", 0|(1<<TID::Commutable), 0x76c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1716 = PCMPEQDrr
  { 1717,	7,	1,	0,	"PCMPEQQrm", 0|(1<<TID::MayLoad), 0x29c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1717 = PCMPEQQrm
  { 1718,	3,	1,	0,	"PCMPEQQrr", 0|(1<<TID::Commutable), 0x29c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1718 = PCMPEQQrr
  { 1719,	7,	1,	0,	"PCMPEQWrm", 0|(1<<TID::MayLoad), 0x75c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1719 = PCMPEQWrm
  { 1720,	3,	1,	0,	"PCMPEQWrr", 0|(1<<TID::Commutable), 0x75c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1720 = PCMPEQWrr
  { 1721,	7,	0,	0,	"PCMPESTRIArm", 0|(1<<TID::MayLoad), 0x61c02e46ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #1721 = PCMPESTRIArm
  { 1722,	3,	0,	0,	"PCMPESTRIArr", 0, 0x61c02e45ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #1722 = PCMPESTRIArr
  { 1723,	7,	0,	0,	"PCMPESTRICrm", 0|(1<<TID::MayLoad), 0x61c02e46ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #1723 = PCMPESTRICrm
  { 1724,	3,	0,	0,	"PCMPESTRICrr", 0, 0x61c02e45ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #1724 = PCMPESTRICrr
  { 1725,	7,	0,	0,	"PCMPESTRIOrm", 0|(1<<TID::MayLoad), 0x61c02e46ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #1725 = PCMPESTRIOrm
  { 1726,	3,	0,	0,	"PCMPESTRIOrr", 0, 0x61c02e45ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #1726 = PCMPESTRIOrr
  { 1727,	7,	0,	0,	"PCMPESTRISrm", 0|(1<<TID::MayLoad), 0x61c02e46ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #1727 = PCMPESTRISrm
  { 1728,	3,	0,	0,	"PCMPESTRISrr", 0, 0x61c02e45ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #1728 = PCMPESTRISrr
  { 1729,	7,	0,	0,	"PCMPESTRIZrm", 0|(1<<TID::MayLoad), 0x61c02e46ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #1729 = PCMPESTRIZrm
  { 1730,	3,	0,	0,	"PCMPESTRIZrr", 0, 0x61c02e45ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #1730 = PCMPESTRIZrr
  { 1731,	7,	0,	0,	"PCMPESTRIrm", 0|(1<<TID::MayLoad), 0x61c02e46ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #1731 = PCMPESTRIrm
  { 1732,	3,	0,	0,	"PCMPESTRIrr", 0, 0x61c02e45ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #1732 = PCMPESTRIrr
  { 1733,	8,	1,	0,	"PCMPESTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0x2000ULL, ImplicitList14, ImplicitList1, Barriers1, OperandInfo136 },  // Inst #1733 = PCMPESTRM128MEM
  { 1734,	4,	1,	0,	"PCMPESTRM128REG", 0|(1<<TID::UsesCustomInserter), 0x2000ULL, ImplicitList14, ImplicitList1, Barriers1, OperandInfo80 },  // Inst #1734 = PCMPESTRM128REG
  { 1735,	7,	0,	0,	"PCMPESTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0x60c02e46ULL, ImplicitList14, ImplicitList43, Barriers1, OperandInfo44 },  // Inst #1735 = PCMPESTRM128rm
  { 1736,	3,	0,	0,	"PCMPESTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0x60c02e45ULL, ImplicitList14, ImplicitList43, Barriers1, OperandInfo45 },  // Inst #1736 = PCMPESTRM128rr
  { 1737,	7,	1,	0,	"PCMPGTBrm", 0|(1<<TID::MayLoad), 0x64c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1737 = PCMPGTBrm
  { 1738,	3,	1,	0,	"PCMPGTBrr", 0, 0x64c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1738 = PCMPGTBrr
  { 1739,	7,	1,	0,	"PCMPGTDrm", 0|(1<<TID::MayLoad), 0x66c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1739 = PCMPGTDrm
  { 1740,	3,	1,	0,	"PCMPGTDrr", 0, 0x66c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1740 = PCMPGTDrr
  { 1741,	7,	1,	0,	"PCMPGTQrm", 0|(1<<TID::MayLoad), 0x37c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1741 = PCMPGTQrm
  { 1742,	3,	1,	0,	"PCMPGTQrr", 0, 0x37c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1742 = PCMPGTQrr
  { 1743,	7,	1,	0,	"PCMPGTWrm", 0|(1<<TID::MayLoad), 0x65c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1743 = PCMPGTWrm
  { 1744,	3,	1,	0,	"PCMPGTWrr", 0, 0x65c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1744 = PCMPGTWrr
  { 1745,	7,	0,	0,	"PCMPISTRIArm", 0|(1<<TID::MayLoad), 0x63c02e46ULL, NULL, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #1745 = PCMPISTRIArm
  { 1746,	3,	0,	0,	"PCMPISTRIArr", 0, 0x63c02e45ULL, NULL, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #1746 = PCMPISTRIArr
  { 1747,	7,	0,	0,	"PCMPISTRICrm", 0|(1<<TID::MayLoad), 0x63c02e46ULL, NULL, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #1747 = PCMPISTRICrm
  { 1748,	3,	0,	0,	"PCMPISTRICrr", 0, 0x63c02e45ULL, NULL, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #1748 = PCMPISTRICrr
  { 1749,	7,	0,	0,	"PCMPISTRIOrm", 0|(1<<TID::MayLoad), 0x63c02e46ULL, NULL, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #1749 = PCMPISTRIOrm
  { 1750,	3,	0,	0,	"PCMPISTRIOrr", 0, 0x63c02e45ULL, NULL, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #1750 = PCMPISTRIOrr
  { 1751,	7,	0,	0,	"PCMPISTRISrm", 0|(1<<TID::MayLoad), 0x63c02e46ULL, NULL, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #1751 = PCMPISTRISrm
  { 1752,	3,	0,	0,	"PCMPISTRISrr", 0, 0x63c02e45ULL, NULL, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #1752 = PCMPISTRISrr
  { 1753,	7,	0,	0,	"PCMPISTRIZrm", 0|(1<<TID::MayLoad), 0x63c02e46ULL, NULL, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #1753 = PCMPISTRIZrm
  { 1754,	3,	0,	0,	"PCMPISTRIZrr", 0, 0x63c02e45ULL, NULL, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #1754 = PCMPISTRIZrr
  { 1755,	7,	0,	0,	"PCMPISTRIrm", 0|(1<<TID::MayLoad), 0x63c02e46ULL, NULL, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #1755 = PCMPISTRIrm
  { 1756,	3,	0,	0,	"PCMPISTRIrr", 0, 0x63c02e45ULL, NULL, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #1756 = PCMPISTRIrr
  { 1757,	8,	1,	0,	"PCMPISTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0x2000ULL, NULL, ImplicitList1, Barriers1, OperandInfo136 },  // Inst #1757 = PCMPISTRM128MEM
  { 1758,	4,	1,	0,	"PCMPISTRM128REG", 0|(1<<TID::UsesCustomInserter), 0x2000ULL, NULL, ImplicitList1, Barriers1, OperandInfo80 },  // Inst #1758 = PCMPISTRM128REG
  { 1759,	7,	0,	0,	"PCMPISTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0x62c02e46ULL, NULL, ImplicitList43, Barriers1, OperandInfo44 },  // Inst #1759 = PCMPISTRM128rm
  { 1760,	3,	0,	0,	"PCMPISTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0x62c02e45ULL, NULL, ImplicitList43, Barriers1, OperandInfo45 },  // Inst #1760 = PCMPISTRM128rr
  { 1761,	7,	0,	0,	"PEXTRBmr", 0|(1<<TID::UnmodeledSideEffects), 0x14c02e44ULL, NULL, NULL, NULL, OperandInfo108 },  // Inst #1761 = PEXTRBmr
  { 1762,	3,	1,	0,	"PEXTRBrr", 0, 0x14c02e43ULL, NULL, NULL, NULL, OperandInfo109 },  // Inst #1762 = PEXTRBrr
  { 1763,	7,	0,	0,	"PEXTRDmr", 0|(1<<TID::MayStore), 0x16c02e44ULL, NULL, NULL, NULL, OperandInfo108 },  // Inst #1763 = PEXTRDmr
  { 1764,	3,	1,	0,	"PEXTRDrr", 0, 0x16c02e43ULL, NULL, NULL, NULL, OperandInfo109 },  // Inst #1764 = PEXTRDrr
  { 1765,	7,	0,	0,	"PEXTRQmr", 0|(1<<TID::MayStore), 0x16c03e44ULL, NULL, NULL, NULL, OperandInfo108 },  // Inst #1765 = PEXTRQmr
  { 1766,	3,	1,	0,	"PEXTRQrr", 0, 0x16c03e43ULL, NULL, NULL, NULL, OperandInfo206 },  // Inst #1766 = PEXTRQrr
  { 1767,	7,	0,	0,	"PEXTRWmr", 0|(1<<TID::UnmodeledSideEffects), 0x15c02e44ULL, NULL, NULL, NULL, OperandInfo108 },  // Inst #1767 = PEXTRWmr
  { 1768,	3,	1,	0,	"PEXTRWri", 0, 0xc5c02145ULL, NULL, NULL, NULL, OperandInfo109 },  // Inst #1768 = PEXTRWri
  { 1769,	7,	1,	0,	"PHADDDrm128", 0|(1<<TID::MayLoad), 0x2c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1769 = PHADDDrm128
  { 1770,	7,	1,	0,	"PHADDDrm64", 0|(1<<TID::MayLoad), 0x2c00d06ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1770 = PHADDDrm64
  { 1771,	3,	1,	0,	"PHADDDrr128", 0, 0x2c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1771 = PHADDDrr128
  { 1772,	3,	1,	0,	"PHADDDrr64", 0, 0x2c00d05ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1772 = PHADDDrr64
  { 1773,	7,	1,	0,	"PHADDSWrm128", 0|(1<<TID::MayLoad), 0x3c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1773 = PHADDSWrm128
  { 1774,	7,	1,	0,	"PHADDSWrm64", 0|(1<<TID::MayLoad), 0x3c00d06ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1774 = PHADDSWrm64
  { 1775,	3,	1,	0,	"PHADDSWrr128", 0, 0x3c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1775 = PHADDSWrr128
  { 1776,	3,	1,	0,	"PHADDSWrr64", 0, 0x3c00d05ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1776 = PHADDSWrr64
  { 1777,	7,	1,	0,	"PHADDWrm128", 0|(1<<TID::MayLoad), 0x1c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1777 = PHADDWrm128
  { 1778,	7,	1,	0,	"PHADDWrm64", 0|(1<<TID::MayLoad), 0x1c00d06ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1778 = PHADDWrm64
  { 1779,	3,	1,	0,	"PHADDWrr128", 0, 0x1c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1779 = PHADDWrr128
  { 1780,	3,	1,	0,	"PHADDWrr64", 0, 0x1c00d05ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1780 = PHADDWrr64
  { 1781,	6,	1,	0,	"PHMINPOSUWrm128", 0|(1<<TID::MayLoad), 0x41c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1781 = PHMINPOSUWrm128
  { 1782,	2,	1,	0,	"PHMINPOSUWrr128", 0, 0x41c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1782 = PHMINPOSUWrr128
  { 1783,	7,	1,	0,	"PHSUBDrm128", 0|(1<<TID::MayLoad), 0x6c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1783 = PHSUBDrm128
  { 1784,	7,	1,	0,	"PHSUBDrm64", 0|(1<<TID::MayLoad), 0x6c00d06ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1784 = PHSUBDrm64
  { 1785,	3,	1,	0,	"PHSUBDrr128", 0, 0x6c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1785 = PHSUBDrr128
  { 1786,	3,	1,	0,	"PHSUBDrr64", 0, 0x6c00d05ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1786 = PHSUBDrr64
  { 1787,	7,	1,	0,	"PHSUBSWrm128", 0|(1<<TID::MayLoad), 0x7c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1787 = PHSUBSWrm128
  { 1788,	7,	1,	0,	"PHSUBSWrm64", 0|(1<<TID::MayLoad), 0x7c00d06ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1788 = PHSUBSWrm64
  { 1789,	3,	1,	0,	"PHSUBSWrr128", 0, 0x7c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1789 = PHSUBSWrr128
  { 1790,	3,	1,	0,	"PHSUBSWrr64", 0, 0x7c00d05ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1790 = PHSUBSWrr64
  { 1791,	7,	1,	0,	"PHSUBWrm128", 0|(1<<TID::MayLoad), 0x5c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1791 = PHSUBWrm128
  { 1792,	7,	1,	0,	"PHSUBWrm64", 0|(1<<TID::MayLoad), 0x5c00d06ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1792 = PHSUBWrm64
  { 1793,	3,	1,	0,	"PHSUBWrr128", 0, 0x5c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1793 = PHSUBWrr128
  { 1794,	3,	1,	0,	"PHSUBWrr64", 0, 0x5c00d05ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1794 = PHSUBWrr64
  { 1795,	8,	1,	0,	"PINSRBrm", 0|(1<<TID::MayLoad), 0x20c02e46ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #1795 = PINSRBrm
  { 1796,	4,	1,	0,	"PINSRBrr", 0, 0x20c02e45ULL, NULL, NULL, NULL, OperandInfo207 },  // Inst #1796 = PINSRBrr
  { 1797,	8,	1,	0,	"PINSRDrm", 0|(1<<TID::MayLoad), 0x22c02e46ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #1797 = PINSRDrm
  { 1798,	4,	1,	0,	"PINSRDrr", 0, 0x22c02e45ULL, NULL, NULL, NULL, OperandInfo207 },  // Inst #1798 = PINSRDrr
  { 1799,	8,	1,	0,	"PINSRQrm", 0|(1<<TID::MayLoad), 0x22c03e46ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #1799 = PINSRQrm
  { 1800,	4,	1,	0,	"PINSRQrr", 0, 0x22c03e45ULL, NULL, NULL, NULL, OperandInfo208 },  // Inst #1800 = PINSRQrr
  { 1801,	8,	1,	0,	"PINSRWrmi", 0|(1<<TID::MayLoad), 0xc4c02146ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #1801 = PINSRWrmi
  { 1802,	4,	1,	0,	"PINSRWrri", 0, 0xc4c02145ULL, NULL, NULL, NULL, OperandInfo207 },  // Inst #1802 = PINSRWrri
  { 1803,	7,	1,	0,	"PMADDUBSWrm128", 0|(1<<TID::MayLoad), 0x4c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1803 = PMADDUBSWrm128
  { 1804,	7,	1,	0,	"PMADDUBSWrm64", 0|(1<<TID::MayLoad), 0x4c00d06ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1804 = PMADDUBSWrm64
  { 1805,	3,	1,	0,	"PMADDUBSWrr128", 0, 0x4c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1805 = PMADDUBSWrr128
  { 1806,	3,	1,	0,	"PMADDUBSWrr64", 0, 0x4c00d05ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1806 = PMADDUBSWrr64
  { 1807,	7,	1,	0,	"PMADDWDrm", 0|(1<<TID::MayLoad), 0xf5c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1807 = PMADDWDrm
  { 1808,	3,	1,	0,	"PMADDWDrr", 0|(1<<TID::Commutable), 0xf5c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1808 = PMADDWDrr
  { 1809,	7,	1,	0,	"PMAXSBrm", 0|(1<<TID::MayLoad), 0x3cc00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1809 = PMAXSBrm
  { 1810,	3,	1,	0,	"PMAXSBrr", 0|(1<<TID::Commutable), 0x3cc00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1810 = PMAXSBrr
  { 1811,	7,	1,	0,	"PMAXSDrm", 0|(1<<TID::MayLoad), 0x3dc00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1811 = PMAXSDrm
  { 1812,	3,	1,	0,	"PMAXSDrr", 0|(1<<TID::Commutable), 0x3dc00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1812 = PMAXSDrr
  { 1813,	7,	1,	0,	"PMAXSWrm", 0|(1<<TID::MayLoad), 0xeec00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1813 = PMAXSWrm
  { 1814,	3,	1,	0,	"PMAXSWrr", 0|(1<<TID::Commutable), 0xeec00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1814 = PMAXSWrr
  { 1815,	7,	1,	0,	"PMAXUBrm", 0|(1<<TID::MayLoad), 0xdec00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1815 = PMAXUBrm
  { 1816,	3,	1,	0,	"PMAXUBrr", 0|(1<<TID::Commutable), 0xdec00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1816 = PMAXUBrr
  { 1817,	7,	1,	0,	"PMAXUDrm", 0|(1<<TID::MayLoad), 0x3fc00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1817 = PMAXUDrm
  { 1818,	3,	1,	0,	"PMAXUDrr", 0|(1<<TID::Commutable), 0x3fc00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1818 = PMAXUDrr
  { 1819,	7,	1,	0,	"PMAXUWrm", 0|(1<<TID::MayLoad), 0x3ec00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1819 = PMAXUWrm
  { 1820,	3,	1,	0,	"PMAXUWrr", 0|(1<<TID::Commutable), 0x3ec00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1820 = PMAXUWrr
  { 1821,	7,	1,	0,	"PMINSBrm", 0|(1<<TID::MayLoad), 0x38c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1821 = PMINSBrm
  { 1822,	3,	1,	0,	"PMINSBrr", 0|(1<<TID::Commutable), 0x38c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1822 = PMINSBrr
  { 1823,	7,	1,	0,	"PMINSDrm", 0|(1<<TID::MayLoad), 0x39c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1823 = PMINSDrm
  { 1824,	3,	1,	0,	"PMINSDrr", 0|(1<<TID::Commutable), 0x39c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1824 = PMINSDrr
  { 1825,	7,	1,	0,	"PMINSWrm", 0|(1<<TID::MayLoad), 0xeac00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1825 = PMINSWrm
  { 1826,	3,	1,	0,	"PMINSWrr", 0|(1<<TID::Commutable), 0xeac00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1826 = PMINSWrr
  { 1827,	7,	1,	0,	"PMINUBrm", 0|(1<<TID::MayLoad), 0xdac00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1827 = PMINUBrm
  { 1828,	3,	1,	0,	"PMINUBrr", 0|(1<<TID::Commutable), 0xdac00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1828 = PMINUBrr
  { 1829,	7,	1,	0,	"PMINUDrm", 0|(1<<TID::MayLoad), 0x3bc00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1829 = PMINUDrm
  { 1830,	3,	1,	0,	"PMINUDrr", 0|(1<<TID::Commutable), 0x3bc00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1830 = PMINUDrr
  { 1831,	7,	1,	0,	"PMINUWrm", 0|(1<<TID::MayLoad), 0x3ac00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1831 = PMINUWrm
  { 1832,	3,	1,	0,	"PMINUWrr", 0|(1<<TID::Commutable), 0x3ac00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1832 = PMINUWrr
  { 1833,	2,	1,	0,	"PMOVMSKBrr", 0, 0xd7c00145ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #1833 = PMOVMSKBrr
  { 1834,	6,	1,	0,	"PMOVSXBDrm", 0|(1<<TID::MayLoad), 0x21c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1834 = PMOVSXBDrm
  { 1835,	2,	1,	0,	"PMOVSXBDrr", 0, 0x21c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1835 = PMOVSXBDrr
  { 1836,	6,	1,	0,	"PMOVSXBQrm", 0|(1<<TID::MayLoad), 0x22c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1836 = PMOVSXBQrm
  { 1837,	2,	1,	0,	"PMOVSXBQrr", 0, 0x22c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1837 = PMOVSXBQrr
  { 1838,	6,	1,	0,	"PMOVSXBWrm", 0|(1<<TID::MayLoad), 0x20c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1838 = PMOVSXBWrm
  { 1839,	2,	1,	0,	"PMOVSXBWrr", 0, 0x20c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1839 = PMOVSXBWrr
  { 1840,	6,	1,	0,	"PMOVSXDQrm", 0|(1<<TID::MayLoad), 0x25c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1840 = PMOVSXDQrm
  { 1841,	2,	1,	0,	"PMOVSXDQrr", 0, 0x25c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1841 = PMOVSXDQrr
  { 1842,	6,	1,	0,	"PMOVSXWDrm", 0|(1<<TID::MayLoad), 0x23c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1842 = PMOVSXWDrm
  { 1843,	2,	1,	0,	"PMOVSXWDrr", 0, 0x23c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1843 = PMOVSXWDrr
  { 1844,	6,	1,	0,	"PMOVSXWQrm", 0|(1<<TID::MayLoad), 0x24c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1844 = PMOVSXWQrm
  { 1845,	2,	1,	0,	"PMOVSXWQrr", 0, 0x24c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1845 = PMOVSXWQrr
  { 1846,	6,	1,	0,	"PMOVZXBDrm", 0|(1<<TID::MayLoad), 0x31c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1846 = PMOVZXBDrm
  { 1847,	2,	1,	0,	"PMOVZXBDrr", 0, 0x31c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1847 = PMOVZXBDrr
  { 1848,	6,	1,	0,	"PMOVZXBQrm", 0|(1<<TID::MayLoad), 0x32c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1848 = PMOVZXBQrm
  { 1849,	2,	1,	0,	"PMOVZXBQrr", 0, 0x32c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1849 = PMOVZXBQrr
  { 1850,	6,	1,	0,	"PMOVZXBWrm", 0|(1<<TID::MayLoad), 0x30c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1850 = PMOVZXBWrm
  { 1851,	2,	1,	0,	"PMOVZXBWrr", 0, 0x30c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1851 = PMOVZXBWrr
  { 1852,	6,	1,	0,	"PMOVZXDQrm", 0|(1<<TID::MayLoad), 0x35c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1852 = PMOVZXDQrm
  { 1853,	2,	1,	0,	"PMOVZXDQrr", 0, 0x35c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1853 = PMOVZXDQrr
  { 1854,	6,	1,	0,	"PMOVZXWDrm", 0|(1<<TID::MayLoad), 0x33c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1854 = PMOVZXWDrm
  { 1855,	2,	1,	0,	"PMOVZXWDrr", 0, 0x33c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1855 = PMOVZXWDrr
  { 1856,	6,	1,	0,	"PMOVZXWQrm", 0|(1<<TID::MayLoad), 0x34c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #1856 = PMOVZXWQrm
  { 1857,	2,	1,	0,	"PMOVZXWQrr", 0, 0x34c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #1857 = PMOVZXWQrr
  { 1858,	7,	1,	0,	"PMULDQrm", 0|(1<<TID::MayLoad), 0x28c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1858 = PMULDQrm
  { 1859,	3,	1,	0,	"PMULDQrr", 0|(1<<TID::Commutable), 0x28c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1859 = PMULDQrr
  { 1860,	7,	1,	0,	"PMULHRSWrm128", 0|(1<<TID::MayLoad), 0xbc00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1860 = PMULHRSWrm128
  { 1861,	7,	1,	0,	"PMULHRSWrm64", 0|(1<<TID::MayLoad), 0xbc00d06ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1861 = PMULHRSWrm64
  { 1862,	3,	1,	0,	"PMULHRSWrr128", 0|(1<<TID::Commutable), 0xbc00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1862 = PMULHRSWrr128
  { 1863,	3,	1,	0,	"PMULHRSWrr64", 0|(1<<TID::Commutable), 0xbc00d05ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1863 = PMULHRSWrr64
  { 1864,	7,	1,	0,	"PMULHUWrm", 0|(1<<TID::MayLoad), 0xe4c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1864 = PMULHUWrm
  { 1865,	3,	1,	0,	"PMULHUWrr", 0|(1<<TID::Commutable), 0xe4c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1865 = PMULHUWrr
  { 1866,	7,	1,	0,	"PMULHWrm", 0|(1<<TID::MayLoad), 0xe5c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1866 = PMULHWrm
  { 1867,	3,	1,	0,	"PMULHWrr", 0|(1<<TID::Commutable), 0xe5c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1867 = PMULHWrr
  { 1868,	7,	1,	0,	"PMULLDrm", 0|(1<<TID::MayLoad), 0x40c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1868 = PMULLDrm
  { 1869,	3,	1,	0,	"PMULLDrr", 0|(1<<TID::Commutable), 0x40c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1869 = PMULLDrr
  { 1870,	7,	1,	0,	"PMULLWrm", 0|(1<<TID::MayLoad), 0xd5c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1870 = PMULLWrm
  { 1871,	3,	1,	0,	"PMULLWrr", 0|(1<<TID::Commutable), 0xd5c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1871 = PMULLWrr
  { 1872,	7,	1,	0,	"PMULUDQrm", 0|(1<<TID::MayLoad), 0xf4c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1872 = PMULUDQrm
  { 1873,	3,	1,	0,	"PMULUDQrr", 0|(1<<TID::Commutable), 0xf4c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1873 = PMULUDQrr
  { 1874,	1,	1,	0,	"POP16r", 0|(1<<TID::MayLoad), 0x58000042ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo106 },  // Inst #1874 = POP16r
  { 1875,	5,	1,	0,	"POP16rmm", 0|(1<<TID::MayLoad), 0x8f000058ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo34 },  // Inst #1875 = POP16rmm
  { 1876,	1,	1,	0,	"POP16rmr", 0|(1<<TID::MayLoad), 0x8f000050ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo106 },  // Inst #1876 = POP16rmr
  { 1877,	1,	1,	0,	"POP32r", 0|(1<<TID::MayLoad), 0x58000002ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo66 },  // Inst #1877 = POP32r
  { 1878,	5,	1,	0,	"POP32rmm", 0|(1<<TID::MayLoad), 0x8f000018ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo34 },  // Inst #1878 = POP32rmm
  { 1879,	1,	1,	0,	"POP32rmr", 0|(1<<TID::MayLoad), 0x8f000010ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo66 },  // Inst #1879 = POP32rmr
  { 1880,	1,	1,	0,	"POP64r", 0|(1<<TID::MayLoad), 0x58000002ULL, ImplicitList4, ImplicitList4, NULL, OperandInfo67 },  // Inst #1880 = POP64r
  { 1881,	5,	1,	0,	"POP64rmm", 0|(1<<TID::MayLoad), 0x8f000018ULL, ImplicitList4, ImplicitList4, NULL, OperandInfo34 },  // Inst #1881 = POP64rmm
  { 1882,	1,	1,	0,	"POP64rmr", 0|(1<<TID::MayLoad), 0x8f000010ULL, ImplicitList4, ImplicitList4, NULL, OperandInfo67 },  // Inst #1882 = POP64rmr
  { 1883,	0,	0,	0,	"POPA32", 0|(1<<TID::MayLoad), 0x61000001ULL, ImplicitList2, ImplicitList44, Barriers7, 0 },  // Inst #1883 = POPA32
  { 1884,	6,	1,	0,	"POPCNT16rm", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xb8000c46ULL, NULL, NULL, NULL, OperandInfo55 },  // Inst #1884 = POPCNT16rm
  { 1885,	2,	1,	0,	"POPCNT16rr", 0|(1<<TID::UnmodeledSideEffects), 0xb8000c45ULL, NULL, NULL, NULL, OperandInfo56 },  // Inst #1885 = POPCNT16rr
  { 1886,	6,	1,	0,	"POPCNT32rm", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xb8000c06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #1886 = POPCNT32rm
  { 1887,	2,	1,	0,	"POPCNT32rr", 0|(1<<TID::UnmodeledSideEffects), 0xb8000c05ULL, NULL, NULL, NULL, OperandInfo58 },  // Inst #1887 = POPCNT32rr
  { 1888,	6,	1,	0,	"POPCNT64rm", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xb8001c06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #1888 = POPCNT64rm
  { 1889,	2,	1,	0,	"POPCNT64rr", 0|(1<<TID::UnmodeledSideEffects), 0xb8001c05ULL, NULL, NULL, NULL, OperandInfo60 },  // Inst #1889 = POPCNT64rr
  { 1890,	0,	0,	0,	"POPF16", 0|(1<<TID::MayLoad), 0x9d000041ULL, ImplicitList2, ImplicitList3, Barriers1, 0 },  // Inst #1890 = POPF16
  { 1891,	0,	0,	0,	"POPF32", 0|(1<<TID::MayLoad), 0x9d000001ULL, ImplicitList2, ImplicitList3, Barriers1, 0 },  // Inst #1891 = POPF32
  { 1892,	0,	0,	0,	"POPF64", 0|(1<<TID::MayLoad), 0x9d000001ULL, ImplicitList4, ImplicitList5, Barriers1, 0 },  // Inst #1892 = POPF64
  { 1893,	0,	0,	0,	"POPFS16", 0|(1<<TID::UnmodeledSideEffects), 0xa1000141ULL, NULL, NULL, NULL, 0 },  // Inst #1893 = POPFS16
  { 1894,	0,	0,	0,	"POPFS32", 0|(1<<TID::UnmodeledSideEffects), 0xa1000101ULL, NULL, NULL, NULL, 0 },  // Inst #1894 = POPFS32
  { 1895,	0,	0,	0,	"POPFS64", 0|(1<<TID::UnmodeledSideEffects), 0xa1000101ULL, NULL, NULL, NULL, 0 },  // Inst #1895 = POPFS64
  { 1896,	0,	0,	0,	"POPGS16", 0|(1<<TID::UnmodeledSideEffects), 0xa9000141ULL, NULL, NULL, NULL, 0 },  // Inst #1896 = POPGS16
  { 1897,	0,	0,	0,	"POPGS32", 0|(1<<TID::UnmodeledSideEffects), 0xa9000101ULL, NULL, NULL, NULL, 0 },  // Inst #1897 = POPGS32
  { 1898,	0,	0,	0,	"POPGS64", 0|(1<<TID::UnmodeledSideEffects), 0xa9000101ULL, NULL, NULL, NULL, 0 },  // Inst #1898 = POPGS64
  { 1899,	7,	1,	0,	"PORrm", 0|(1<<TID::MayLoad), 0xebc00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1899 = PORrm
  { 1900,	3,	1,	0,	"PORrr", 0|(1<<TID::Commutable), 0xebc00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1900 = PORrr
  { 1901,	5,	0,	0,	"PREFETCHNTA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x18400118ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1901 = PREFETCHNTA
  { 1902,	5,	0,	0,	"PREFETCHT0", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x18400119ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1902 = PREFETCHT0
  { 1903,	5,	0,	0,	"PREFETCHT1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x1840011aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1903 = PREFETCHT1
  { 1904,	5,	0,	0,	"PREFETCHT2", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x1840011bULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #1904 = PREFETCHT2
  { 1905,	7,	1,	0,	"PSADBWrm", 0|(1<<TID::MayLoad), 0xf6c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1905 = PSADBWrm
  { 1906,	3,	1,	0,	"PSADBWrr", 0|(1<<TID::Commutable), 0xf6c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1906 = PSADBWrr
  { 1907,	7,	1,	0,	"PSHUFBrm128", 0|(1<<TID::MayLoad), 0xc00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1907 = PSHUFBrm128
  { 1908,	7,	1,	0,	"PSHUFBrm64", 0|(1<<TID::MayLoad), 0xc00d06ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1908 = PSHUFBrm64
  { 1909,	3,	1,	0,	"PSHUFBrr128", 0, 0xc00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1909 = PSHUFBrr128
  { 1910,	3,	1,	0,	"PSHUFBrr64", 0, 0xc00d05ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1910 = PSHUFBrr64
  { 1911,	7,	1,	0,	"PSHUFDmi", 0|(1<<TID::MayLoad), 0x70c02146ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #1911 = PSHUFDmi
  { 1912,	3,	1,	0,	"PSHUFDri", 0, 0x70c02145ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #1912 = PSHUFDri
  { 1913,	7,	1,	0,	"PSHUFHWmi", 0|(1<<TID::MayLoad), 0x70c02c06ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #1913 = PSHUFHWmi
  { 1914,	3,	1,	0,	"PSHUFHWri", 0, 0x70c02c05ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #1914 = PSHUFHWri
  { 1915,	7,	1,	0,	"PSHUFLWmi", 0|(1<<TID::MayLoad), 0x70c02b06ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #1915 = PSHUFLWmi
  { 1916,	3,	1,	0,	"PSHUFLWri", 0, 0x70c02b05ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #1916 = PSHUFLWri
  { 1917,	7,	1,	0,	"PSIGNBrm128", 0|(1<<TID::MayLoad), 0x8c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1917 = PSIGNBrm128
  { 1918,	7,	1,	0,	"PSIGNBrm64", 0|(1<<TID::MayLoad), 0x8c00d06ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1918 = PSIGNBrm64
  { 1919,	3,	1,	0,	"PSIGNBrr128", 0, 0x8c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1919 = PSIGNBrr128
  { 1920,	3,	1,	0,	"PSIGNBrr64", 0, 0x8c00d05ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1920 = PSIGNBrr64
  { 1921,	7,	1,	0,	"PSIGNDrm128", 0|(1<<TID::MayLoad), 0xac00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1921 = PSIGNDrm128
  { 1922,	7,	1,	0,	"PSIGNDrm64", 0|(1<<TID::MayLoad), 0xac00d06ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1922 = PSIGNDrm64
  { 1923,	3,	1,	0,	"PSIGNDrr128", 0, 0xac00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1923 = PSIGNDrr128
  { 1924,	3,	1,	0,	"PSIGNDrr64", 0, 0xac00d05ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1924 = PSIGNDrr64
  { 1925,	7,	1,	0,	"PSIGNWrm128", 0|(1<<TID::MayLoad), 0x9c00d46ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1925 = PSIGNWrm128
  { 1926,	7,	1,	0,	"PSIGNWrm64", 0|(1<<TID::MayLoad), 0x9c00d06ULL, NULL, NULL, NULL, OperandInfo151 },  // Inst #1926 = PSIGNWrm64
  { 1927,	3,	1,	0,	"PSIGNWrr128", 0, 0x9c00d45ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1927 = PSIGNWrr128
  { 1928,	3,	1,	0,	"PSIGNWrr64", 0, 0x9c00d05ULL, NULL, NULL, NULL, OperandInfo152 },  // Inst #1928 = PSIGNWrr64
  { 1929,	3,	1,	0,	"PSLLDQri", 0, 0x73c02157ULL, NULL, NULL, NULL, OperandInfo209 },  // Inst #1929 = PSLLDQri
  { 1930,	3,	1,	0,	"PSLLDri", 0, 0x72c02156ULL, NULL, NULL, NULL, OperandInfo209 },  // Inst #1930 = PSLLDri
  { 1931,	7,	1,	0,	"PSLLDrm", 0|(1<<TID::MayLoad), 0xf2c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1931 = PSLLDrm
  { 1932,	3,	1,	0,	"PSLLDrr", 0, 0xf2c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1932 = PSLLDrr
  { 1933,	3,	1,	0,	"PSLLQri", 0, 0x73c02156ULL, NULL, NULL, NULL, OperandInfo209 },  // Inst #1933 = PSLLQri
  { 1934,	7,	1,	0,	"PSLLQrm", 0|(1<<TID::MayLoad), 0xf3c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1934 = PSLLQrm
  { 1935,	3,	1,	0,	"PSLLQrr", 0, 0xf3c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1935 = PSLLQrr
  { 1936,	3,	1,	0,	"PSLLWri", 0, 0x71c02156ULL, NULL, NULL, NULL, OperandInfo209 },  // Inst #1936 = PSLLWri
  { 1937,	7,	1,	0,	"PSLLWrm", 0|(1<<TID::MayLoad), 0xf1c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1937 = PSLLWrm
  { 1938,	3,	1,	0,	"PSLLWrr", 0, 0xf1c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1938 = PSLLWrr
  { 1939,	3,	1,	0,	"PSRADri", 0, 0x72c02154ULL, NULL, NULL, NULL, OperandInfo209 },  // Inst #1939 = PSRADri
  { 1940,	7,	1,	0,	"PSRADrm", 0|(1<<TID::MayLoad), 0xe2c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1940 = PSRADrm
  { 1941,	3,	1,	0,	"PSRADrr", 0, 0xe2c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1941 = PSRADrr
  { 1942,	3,	1,	0,	"PSRAWri", 0, 0x71c02154ULL, NULL, NULL, NULL, OperandInfo209 },  // Inst #1942 = PSRAWri
  { 1943,	7,	1,	0,	"PSRAWrm", 0|(1<<TID::MayLoad), 0xe1c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1943 = PSRAWrm
  { 1944,	3,	1,	0,	"PSRAWrr", 0, 0xe1c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1944 = PSRAWrr
  { 1945,	3,	1,	0,	"PSRLDQri", 0, 0x73c02153ULL, NULL, NULL, NULL, OperandInfo209 },  // Inst #1945 = PSRLDQri
  { 1946,	3,	1,	0,	"PSRLDri", 0, 0x72c02152ULL, NULL, NULL, NULL, OperandInfo209 },  // Inst #1946 = PSRLDri
  { 1947,	7,	1,	0,	"PSRLDrm", 0|(1<<TID::MayLoad), 0xd2c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1947 = PSRLDrm
  { 1948,	3,	1,	0,	"PSRLDrr", 0, 0xd2c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1948 = PSRLDrr
  { 1949,	3,	1,	0,	"PSRLQri", 0, 0x73c02152ULL, NULL, NULL, NULL, OperandInfo209 },  // Inst #1949 = PSRLQri
  { 1950,	7,	1,	0,	"PSRLQrm", 0|(1<<TID::MayLoad), 0xd3c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1950 = PSRLQrm
  { 1951,	3,	1,	0,	"PSRLQrr", 0, 0xd3c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1951 = PSRLQrr
  { 1952,	3,	1,	0,	"PSRLWri", 0, 0x71c02152ULL, NULL, NULL, NULL, OperandInfo209 },  // Inst #1952 = PSRLWri
  { 1953,	7,	1,	0,	"PSRLWrm", 0|(1<<TID::MayLoad), 0xd1c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1953 = PSRLWrm
  { 1954,	3,	1,	0,	"PSRLWrr", 0, 0xd1c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1954 = PSRLWrr
  { 1955,	7,	1,	0,	"PSUBBrm", 0|(1<<TID::MayLoad), 0xf8c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1955 = PSUBBrm
  { 1956,	3,	1,	0,	"PSUBBrr", 0, 0xf8c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1956 = PSUBBrr
  { 1957,	7,	1,	0,	"PSUBDrm", 0|(1<<TID::MayLoad), 0xfac00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1957 = PSUBDrm
  { 1958,	3,	1,	0,	"PSUBDrr", 0, 0xfac00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1958 = PSUBDrr
  { 1959,	7,	1,	0,	"PSUBQrm", 0|(1<<TID::MayLoad), 0xfbc00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1959 = PSUBQrm
  { 1960,	3,	1,	0,	"PSUBQrr", 0, 0xfbc00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1960 = PSUBQrr
  { 1961,	7,	1,	0,	"PSUBSBrm", 0|(1<<TID::MayLoad), 0xe8c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1961 = PSUBSBrm
  { 1962,	3,	1,	0,	"PSUBSBrr", 0, 0xe8c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1962 = PSUBSBrr
  { 1963,	7,	1,	0,	"PSUBSWrm", 0|(1<<TID::MayLoad), 0xe9c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1963 = PSUBSWrm
  { 1964,	3,	1,	0,	"PSUBSWrr", 0, 0xe9c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1964 = PSUBSWrr
  { 1965,	7,	1,	0,	"PSUBUSBrm", 0|(1<<TID::MayLoad), 0xd8c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1965 = PSUBUSBrm
  { 1966,	3,	1,	0,	"PSUBUSBrr", 0, 0xd8c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1966 = PSUBUSBrr
  { 1967,	7,	1,	0,	"PSUBUSWrm", 0|(1<<TID::MayLoad), 0xd9c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1967 = PSUBUSWrm
  { 1968,	3,	1,	0,	"PSUBUSWrr", 0, 0xd9c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1968 = PSUBUSWrr
  { 1969,	7,	1,	0,	"PSUBWrm", 0|(1<<TID::MayLoad), 0xf9c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1969 = PSUBWrm
  { 1970,	3,	1,	0,	"PSUBWrr", 0, 0xf9c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1970 = PSUBWrr
  { 1971,	6,	0,	0,	"PTESTrm", 0|(1<<TID::MayLoad), 0x17c00d46ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #1971 = PTESTrm
  { 1972,	2,	0,	0,	"PTESTrr", 0, 0x17c00d45ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #1972 = PTESTrr
  { 1973,	7,	1,	0,	"PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0x68c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1973 = PUNPCKHBWrm
  { 1974,	3,	1,	0,	"PUNPCKHBWrr", 0, 0x68c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1974 = PUNPCKHBWrr
  { 1975,	7,	1,	0,	"PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0x6ac00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1975 = PUNPCKHDQrm
  { 1976,	3,	1,	0,	"PUNPCKHDQrr", 0, 0x6ac00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1976 = PUNPCKHDQrr
  { 1977,	7,	1,	0,	"PUNPCKHQDQrm", 0|(1<<TID::MayLoad), 0x6dc00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1977 = PUNPCKHQDQrm
  { 1978,	3,	1,	0,	"PUNPCKHQDQrr", 0, 0x6dc00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1978 = PUNPCKHQDQrr
  { 1979,	7,	1,	0,	"PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0x69c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1979 = PUNPCKHWDrm
  { 1980,	3,	1,	0,	"PUNPCKHWDrr", 0, 0x69c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1980 = PUNPCKHWDrr
  { 1981,	7,	1,	0,	"PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0x60c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1981 = PUNPCKLBWrm
  { 1982,	3,	1,	0,	"PUNPCKLBWrr", 0, 0x60c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1982 = PUNPCKLBWrr
  { 1983,	7,	1,	0,	"PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0x62c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1983 = PUNPCKLDQrm
  { 1984,	3,	1,	0,	"PUNPCKLDQrr", 0, 0x62c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1984 = PUNPCKLDQrr
  { 1985,	7,	1,	0,	"PUNPCKLQDQrm", 0|(1<<TID::MayLoad), 0x6cc00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1985 = PUNPCKLQDQrm
  { 1986,	3,	1,	0,	"PUNPCKLQDQrr", 0, 0x6cc00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1986 = PUNPCKLQDQrr
  { 1987,	7,	1,	0,	"PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0x61c00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #1987 = PUNPCKLWDrm
  { 1988,	3,	1,	0,	"PUNPCKLWDrr", 0, 0x61c00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #1988 = PUNPCKLWDrr
  { 1989,	1,	0,	0,	"PUSH16r", 0|(1<<TID::MayStore), 0x50000042ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo106 },  // Inst #1989 = PUSH16r
  { 1990,	5,	0,	0,	"PUSH16rmm", 0|(1<<TID::MayStore), 0xff00005eULL, ImplicitList2, ImplicitList2, NULL, OperandInfo34 },  // Inst #1990 = PUSH16rmm
  { 1991,	1,	0,	0,	"PUSH16rmr", 0|(1<<TID::MayStore), 0xff000056ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo106 },  // Inst #1991 = PUSH16rmr
  { 1992,	1,	0,	0,	"PUSH32r", 0|(1<<TID::MayStore), 0x50000002ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo66 },  // Inst #1992 = PUSH32r
  { 1993,	5,	0,	0,	"PUSH32rmm", 0|(1<<TID::MayStore), 0xff00001eULL, ImplicitList2, ImplicitList2, NULL, OperandInfo34 },  // Inst #1993 = PUSH32rmm
  { 1994,	1,	0,	0,	"PUSH32rmr", 0|(1<<TID::MayStore), 0xff000016ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo66 },  // Inst #1994 = PUSH32rmr
  { 1995,	1,	0,	0,	"PUSH64i16", 0|(1<<TID::MayStore), 0x68006001ULL, ImplicitList4, ImplicitList4, NULL, OperandInfo2 },  // Inst #1995 = PUSH64i16
  { 1996,	1,	0,	0,	"PUSH64i32", 0|(1<<TID::MayStore), 0x6800a001ULL, ImplicitList4, ImplicitList4, NULL, OperandInfo2 },  // Inst #1996 = PUSH64i32
  { 1997,	1,	0,	0,	"PUSH64i8", 0|(1<<TID::MayStore), 0x6a002001ULL, ImplicitList4, ImplicitList4, NULL, OperandInfo2 },  // Inst #1997 = PUSH64i8
  { 1998,	1,	0,	0,	"PUSH64r", 0|(1<<TID::MayStore), 0x50000002ULL, ImplicitList4, ImplicitList4, NULL, OperandInfo67 },  // Inst #1998 = PUSH64r
  { 1999,	5,	0,	0,	"PUSH64rmm", 0|(1<<TID::MayStore), 0xff00001eULL, ImplicitList4, ImplicitList4, NULL, OperandInfo34 },  // Inst #1999 = PUSH64rmm
  { 2000,	1,	0,	0,	"PUSH64rmr", 0|(1<<TID::MayStore), 0xff000016ULL, ImplicitList4, ImplicitList4, NULL, OperandInfo67 },  // Inst #2000 = PUSH64rmr
  { 2001,	0,	0,	0,	"PUSHA32", 0|(1<<TID::MayStore), 0x60000001ULL, ImplicitList44, ImplicitList2, NULL, 0 },  // Inst #2001 = PUSHA32
  { 2002,	0,	0,	0,	"PUSHF16", 0|(1<<TID::MayStore), 0x9c000041ULL, ImplicitList3, ImplicitList2, NULL, 0 },  // Inst #2002 = PUSHF16
  { 2003,	0,	0,	0,	"PUSHF32", 0|(1<<TID::MayStore), 0x9c000001ULL, ImplicitList3, ImplicitList2, NULL, 0 },  // Inst #2003 = PUSHF32
  { 2004,	0,	0,	0,	"PUSHF64", 0|(1<<TID::MayStore), 0x9c000001ULL, ImplicitList5, ImplicitList4, NULL, 0 },  // Inst #2004 = PUSHF64
  { 2005,	0,	0,	0,	"PUSHFS16", 0|(1<<TID::UnmodeledSideEffects), 0xa0000141ULL, NULL, NULL, NULL, 0 },  // Inst #2005 = PUSHFS16
  { 2006,	0,	0,	0,	"PUSHFS32", 0|(1<<TID::UnmodeledSideEffects), 0xa0000101ULL, NULL, NULL, NULL, 0 },  // Inst #2006 = PUSHFS32
  { 2007,	0,	0,	0,	"PUSHFS64", 0|(1<<TID::UnmodeledSideEffects), 0xa0000101ULL, NULL, NULL, NULL, 0 },  // Inst #2007 = PUSHFS64
  { 2008,	0,	0,	0,	"PUSHGS16", 0|(1<<TID::UnmodeledSideEffects), 0xa8000141ULL, NULL, NULL, NULL, 0 },  // Inst #2008 = PUSHGS16
  { 2009,	0,	0,	0,	"PUSHGS32", 0|(1<<TID::UnmodeledSideEffects), 0xa8000101ULL, NULL, NULL, NULL, 0 },  // Inst #2009 = PUSHGS32
  { 2010,	0,	0,	0,	"PUSHGS64", 0|(1<<TID::UnmodeledSideEffects), 0xa8000101ULL, NULL, NULL, NULL, 0 },  // Inst #2010 = PUSHGS64
  { 2011,	1,	0,	0,	"PUSHi16", 0|(1<<TID::MayStore), 0x68006041ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo2 },  // Inst #2011 = PUSHi16
  { 2012,	1,	0,	0,	"PUSHi32", 0|(1<<TID::MayStore), 0x6800a001ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo2 },  // Inst #2012 = PUSHi32
  { 2013,	1,	0,	0,	"PUSHi8", 0|(1<<TID::MayStore), 0x6a002001ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo2 },  // Inst #2013 = PUSHi8
  { 2014,	7,	1,	0,	"PXORrm", 0|(1<<TID::MayLoad), 0xefc00146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #2014 = PXORrm
  { 2015,	3,	1,	0,	"PXORrr", 0|(1<<TID::Commutable), 0xefc00145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #2015 = PXORrr
  { 2016,	5,	0,	0,	"RCL16m1", 0|(1<<TID::UnmodeledSideEffects), 0xd100005aULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2016 = RCL16m1
  { 2017,	5,	0,	0,	"RCL16mCL", 0|(1<<TID::UnmodeledSideEffects), 0xd300005aULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2017 = RCL16mCL
  { 2018,	6,	0,	0,	"RCL16mi", 0|(1<<TID::UnmodeledSideEffects), 0xc100205aULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2018 = RCL16mi
  { 2019,	2,	1,	0,	"RCL16r1", 0|(1<<TID::UnmodeledSideEffects), 0xd1000052ULL, NULL, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #2019 = RCL16r1
  { 2020,	2,	1,	0,	"RCL16rCL", 0|(1<<TID::UnmodeledSideEffects), 0xd3000052ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #2020 = RCL16rCL
  { 2021,	3,	1,	0,	"RCL16ri", 0|(1<<TID::UnmodeledSideEffects), 0xc1002052ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #2021 = RCL16ri
  { 2022,	5,	0,	0,	"RCL32m1", 0|(1<<TID::UnmodeledSideEffects), 0xd100001aULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2022 = RCL32m1
  { 2023,	5,	0,	0,	"RCL32mCL", 0|(1<<TID::UnmodeledSideEffects), 0xd300001aULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2023 = RCL32mCL
  { 2024,	6,	0,	0,	"RCL32mi", 0|(1<<TID::UnmodeledSideEffects), 0xc100201aULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2024 = RCL32mi
  { 2025,	2,	1,	0,	"RCL32r1", 0|(1<<TID::UnmodeledSideEffects), 0xd1000012ULL, NULL, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #2025 = RCL32r1
  { 2026,	2,	1,	0,	"RCL32rCL", 0|(1<<TID::UnmodeledSideEffects), 0xd3000012ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #2026 = RCL32rCL
  { 2027,	3,	1,	0,	"RCL32ri", 0|(1<<TID::UnmodeledSideEffects), 0xc1002012ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #2027 = RCL32ri
  { 2028,	5,	0,	0,	"RCL64m1", 0|(1<<TID::UnmodeledSideEffects), 0xd100101aULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2028 = RCL64m1
  { 2029,	5,	0,	0,	"RCL64mCL", 0|(1<<TID::UnmodeledSideEffects), 0xd300101aULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2029 = RCL64mCL
  { 2030,	6,	0,	0,	"RCL64mi", 0|(1<<TID::UnmodeledSideEffects), 0xc100301aULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2030 = RCL64mi
  { 2031,	2,	1,	0,	"RCL64r1", 0|(1<<TID::UnmodeledSideEffects), 0xd1001012ULL, NULL, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #2031 = RCL64r1
  { 2032,	2,	1,	0,	"RCL64rCL", 0|(1<<TID::UnmodeledSideEffects), 0xd3001012ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #2032 = RCL64rCL
  { 2033,	3,	1,	0,	"RCL64ri", 0|(1<<TID::UnmodeledSideEffects), 0xc1003012ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #2033 = RCL64ri
  { 2034,	5,	0,	0,	"RCL8m1", 0|(1<<TID::UnmodeledSideEffects), 0xd000001aULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2034 = RCL8m1
  { 2035,	5,	0,	0,	"RCL8mCL", 0|(1<<TID::UnmodeledSideEffects), 0xd200001aULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2035 = RCL8mCL
  { 2036,	6,	0,	0,	"RCL8mi", 0|(1<<TID::UnmodeledSideEffects), 0xc000201aULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2036 = RCL8mi
  { 2037,	2,	1,	0,	"RCL8r1", 0|(1<<TID::UnmodeledSideEffects), 0xd0000012ULL, NULL, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #2037 = RCL8r1
  { 2038,	2,	1,	0,	"RCL8rCL", 0|(1<<TID::UnmodeledSideEffects), 0xd2000012ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #2038 = RCL8rCL
  { 2039,	3,	1,	0,	"RCL8ri", 0|(1<<TID::UnmodeledSideEffects), 0xc0002012ULL, NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #2039 = RCL8ri
  { 2040,	6,	1,	0,	"RCPPSm", 0|(1<<TID::MayLoad), 0x53400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2040 = RCPPSm
  { 2041,	6,	1,	0,	"RCPPSm_Int", 0|(1<<TID::MayLoad), 0x53400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2041 = RCPPSm_Int
  { 2042,	2,	1,	0,	"RCPPSr", 0, 0x53400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2042 = RCPPSr
  { 2043,	2,	1,	0,	"RCPPSr_Int", 0, 0x53400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2043 = RCPPSr_Int
  { 2044,	6,	1,	0,	"RCPSSm", 0|(1<<TID::MayLoad), 0x53000c06ULL, NULL, NULL, NULL, OperandInfo92 },  // Inst #2044 = RCPSSm
  { 2045,	6,	1,	0,	"RCPSSm_Int", 0|(1<<TID::MayLoad), 0x53000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2045 = RCPSSm_Int
  { 2046,	2,	1,	0,	"RCPSSr", 0, 0x53000c05ULL, NULL, NULL, NULL, OperandInfo119 },  // Inst #2046 = RCPSSr
  { 2047,	2,	1,	0,	"RCPSSr_Int", 0, 0x53000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2047 = RCPSSr_Int
  { 2048,	5,	0,	0,	"RCR16m1", 0|(1<<TID::UnmodeledSideEffects), 0xd100005bULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2048 = RCR16m1
  { 2049,	5,	0,	0,	"RCR16mCL", 0|(1<<TID::UnmodeledSideEffects), 0xd300005bULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2049 = RCR16mCL
  { 2050,	6,	0,	0,	"RCR16mi", 0|(1<<TID::UnmodeledSideEffects), 0xc100205bULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2050 = RCR16mi
  { 2051,	2,	1,	0,	"RCR16r1", 0|(1<<TID::UnmodeledSideEffects), 0xd1000053ULL, NULL, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #2051 = RCR16r1
  { 2052,	2,	1,	0,	"RCR16rCL", 0|(1<<TID::UnmodeledSideEffects), 0xd3000053ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #2052 = RCR16rCL
  { 2053,	3,	1,	0,	"RCR16ri", 0|(1<<TID::UnmodeledSideEffects), 0xc1002053ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #2053 = RCR16ri
  { 2054,	5,	0,	0,	"RCR32m1", 0|(1<<TID::UnmodeledSideEffects), 0xd100001bULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2054 = RCR32m1
  { 2055,	5,	0,	0,	"RCR32mCL", 0|(1<<TID::UnmodeledSideEffects), 0xd300001bULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2055 = RCR32mCL
  { 2056,	6,	0,	0,	"RCR32mi", 0|(1<<TID::UnmodeledSideEffects), 0xc100201bULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2056 = RCR32mi
  { 2057,	2,	1,	0,	"RCR32r1", 0|(1<<TID::UnmodeledSideEffects), 0xd1000013ULL, NULL, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #2057 = RCR32r1
  { 2058,	2,	1,	0,	"RCR32rCL", 0|(1<<TID::UnmodeledSideEffects), 0xd3000013ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #2058 = RCR32rCL
  { 2059,	3,	1,	0,	"RCR32ri", 0|(1<<TID::UnmodeledSideEffects), 0xc1002013ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #2059 = RCR32ri
  { 2060,	5,	0,	0,	"RCR64m1", 0|(1<<TID::UnmodeledSideEffects), 0xd100101bULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2060 = RCR64m1
  { 2061,	5,	0,	0,	"RCR64mCL", 0|(1<<TID::UnmodeledSideEffects), 0xd300101bULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2061 = RCR64mCL
  { 2062,	6,	0,	0,	"RCR64mi", 0|(1<<TID::UnmodeledSideEffects), 0xc100301bULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2062 = RCR64mi
  { 2063,	2,	1,	0,	"RCR64r1", 0|(1<<TID::UnmodeledSideEffects), 0xd1001013ULL, NULL, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #2063 = RCR64r1
  { 2064,	2,	1,	0,	"RCR64rCL", 0|(1<<TID::UnmodeledSideEffects), 0xd3001013ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #2064 = RCR64rCL
  { 2065,	3,	1,	0,	"RCR64ri", 0|(1<<TID::UnmodeledSideEffects), 0xc1003013ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #2065 = RCR64ri
  { 2066,	5,	0,	0,	"RCR8m1", 0|(1<<TID::UnmodeledSideEffects), 0xd000001bULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2066 = RCR8m1
  { 2067,	5,	0,	0,	"RCR8mCL", 0|(1<<TID::UnmodeledSideEffects), 0xd200001bULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2067 = RCR8mCL
  { 2068,	6,	0,	0,	"RCR8mi", 0|(1<<TID::UnmodeledSideEffects), 0xc000201bULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2068 = RCR8mi
  { 2069,	2,	1,	0,	"RCR8r1", 0|(1<<TID::UnmodeledSideEffects), 0xd0000013ULL, NULL, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #2069 = RCR8r1
  { 2070,	2,	1,	0,	"RCR8rCL", 0|(1<<TID::UnmodeledSideEffects), 0xd2000013ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #2070 = RCR8rCL
  { 2071,	3,	1,	0,	"RCR8ri", 0|(1<<TID::UnmodeledSideEffects), 0xc0002013ULL, NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #2071 = RCR8ri
  { 2072,	0,	0,	0,	"RDMSR", 0|(1<<TID::UnmodeledSideEffects), 0x32000101ULL, NULL, NULL, NULL, 0 },  // Inst #2072 = RDMSR
  { 2073,	0,	0,	0,	"RDPMC", 0|(1<<TID::UnmodeledSideEffects), 0x33000101ULL, NULL, NULL, NULL, 0 },  // Inst #2073 = RDPMC
  { 2074,	0,	0,	0,	"RDTSC", 0|(1<<TID::UnmodeledSideEffects), 0x31000101ULL, NULL, ImplicitList19, NULL, 0 },  // Inst #2074 = RDTSC
  { 2075,	0,	0,	0,	"RDTSCP", 0|(1<<TID::UnmodeledSideEffects), 0x100012aULL, NULL, ImplicitList46, NULL, 0 },  // Inst #2075 = RDTSCP
  { 2076,	0,	0,	0,	"REPNE_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0xf2000001ULL, ImplicitList42, ImplicitList26, NULL, 0 },  // Inst #2076 = REPNE_PREFIX
  { 2077,	0,	0,	0,	"REP_MOVSB", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xa4000201ULL, ImplicitList47, ImplicitList47, NULL, 0 },  // Inst #2077 = REP_MOVSB
  { 2078,	0,	0,	0,	"REP_MOVSD", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xa5000201ULL, ImplicitList47, ImplicitList47, NULL, 0 },  // Inst #2078 = REP_MOVSD
  { 2079,	0,	0,	0,	"REP_MOVSQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xa5001201ULL, ImplicitList48, ImplicitList48, NULL, 0 },  // Inst #2079 = REP_MOVSQ
  { 2080,	0,	0,	0,	"REP_MOVSW", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xa5000241ULL, ImplicitList47, ImplicitList47, NULL, 0 },  // Inst #2080 = REP_MOVSW
  { 2081,	0,	0,	0,	"REP_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0xf3000001ULL, ImplicitList42, ImplicitList26, NULL, 0 },  // Inst #2081 = REP_PREFIX
  { 2082,	0,	0,	0,	"REP_STOSB", 0|(1<<TID::MayStore), 0xaa000201ULL, ImplicitList49, ImplicitList50, NULL, 0 },  // Inst #2082 = REP_STOSB
  { 2083,	0,	0,	0,	"REP_STOSD", 0|(1<<TID::MayStore), 0xab000201ULL, ImplicitList51, ImplicitList50, NULL, 0 },  // Inst #2083 = REP_STOSD
  { 2084,	0,	0,	0,	"REP_STOSQ", 0|(1<<TID::MayStore), 0xab001201ULL, ImplicitList52, ImplicitList53, NULL, 0 },  // Inst #2084 = REP_STOSQ
  { 2085,	0,	0,	0,	"REP_STOSW", 0|(1<<TID::MayStore), 0xab000241ULL, ImplicitList54, ImplicitList50, NULL, 0 },  // Inst #2085 = REP_STOSW
  { 2086,	0,	0,	0,	"RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0xc3070001ULL, NULL, NULL, NULL, 0 },  // Inst #2086 = RET
  { 2087,	1,	0,	0,	"RETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0xc2076001ULL, NULL, NULL, NULL, OperandInfo2 },  // Inst #2087 = RETI
  { 2088,	5,	0,	0,	"ROL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd1000058ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2088 = ROL16m1
  { 2089,	5,	0,	0,	"ROL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd3000058ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2089 = ROL16mCL
  { 2090,	6,	0,	0,	"ROL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc1002058ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2090 = ROL16mi
  { 2091,	2,	1,	0,	"ROL16r1", 0, 0xd1000050ULL, NULL, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #2091 = ROL16r1
  { 2092,	2,	1,	0,	"ROL16rCL", 0, 0xd3000050ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #2092 = ROL16rCL
  { 2093,	3,	1,	0,	"ROL16ri", 0, 0xc1002050ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #2093 = ROL16ri
  { 2094,	5,	0,	0,	"ROL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd1000018ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2094 = ROL32m1
  { 2095,	5,	0,	0,	"ROL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd3000018ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2095 = ROL32mCL
  { 2096,	6,	0,	0,	"ROL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc1002018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2096 = ROL32mi
  { 2097,	2,	1,	0,	"ROL32r1", 0, 0xd1000010ULL, NULL, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #2097 = ROL32r1
  { 2098,	2,	1,	0,	"ROL32rCL", 0, 0xd3000010ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #2098 = ROL32rCL
  { 2099,	3,	1,	0,	"ROL32ri", 0, 0xc1002010ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #2099 = ROL32ri
  { 2100,	5,	0,	0,	"ROL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd1001018ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2100 = ROL64m1
  { 2101,	5,	0,	0,	"ROL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd3001018ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2101 = ROL64mCL
  { 2102,	6,	0,	0,	"ROL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc1003018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2102 = ROL64mi
  { 2103,	2,	1,	0,	"ROL64r1", 0, 0xd1001010ULL, NULL, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #2103 = ROL64r1
  { 2104,	2,	1,	0,	"ROL64rCL", 0, 0xd3001010ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #2104 = ROL64rCL
  { 2105,	3,	1,	0,	"ROL64ri", 0, 0xc1003010ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #2105 = ROL64ri
  { 2106,	5,	0,	0,	"ROL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd0000018ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2106 = ROL8m1
  { 2107,	5,	0,	0,	"ROL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd2000018ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2107 = ROL8mCL
  { 2108,	6,	0,	0,	"ROL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc0002018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2108 = ROL8mi
  { 2109,	2,	1,	0,	"ROL8r1", 0, 0xd0000010ULL, NULL, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #2109 = ROL8r1
  { 2110,	2,	1,	0,	"ROL8rCL", 0, 0xd2000010ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #2110 = ROL8rCL
  { 2111,	3,	1,	0,	"ROL8ri", 0, 0xc0002010ULL, NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #2111 = ROL8ri
  { 2112,	5,	0,	0,	"ROR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd1000059ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2112 = ROR16m1
  { 2113,	5,	0,	0,	"ROR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd3000059ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2113 = ROR16mCL
  { 2114,	6,	0,	0,	"ROR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc1002059ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2114 = ROR16mi
  { 2115,	2,	1,	0,	"ROR16r1", 0, 0xd1000051ULL, NULL, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #2115 = ROR16r1
  { 2116,	2,	1,	0,	"ROR16rCL", 0, 0xd3000051ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #2116 = ROR16rCL
  { 2117,	3,	1,	0,	"ROR16ri", 0, 0xc1002051ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #2117 = ROR16ri
  { 2118,	5,	0,	0,	"ROR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd1000019ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2118 = ROR32m1
  { 2119,	5,	0,	0,	"ROR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd3000019ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2119 = ROR32mCL
  { 2120,	6,	0,	0,	"ROR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc1002019ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2120 = ROR32mi
  { 2121,	2,	1,	0,	"ROR32r1", 0, 0xd1000011ULL, NULL, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #2121 = ROR32r1
  { 2122,	2,	1,	0,	"ROR32rCL", 0, 0xd3000011ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #2122 = ROR32rCL
  { 2123,	3,	1,	0,	"ROR32ri", 0, 0xc1002011ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #2123 = ROR32ri
  { 2124,	5,	0,	0,	"ROR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd1001019ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2124 = ROR64m1
  { 2125,	5,	0,	0,	"ROR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd3001019ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2125 = ROR64mCL
  { 2126,	6,	0,	0,	"ROR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc1003019ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2126 = ROR64mi
  { 2127,	2,	1,	0,	"ROR64r1", 0, 0xd1001011ULL, NULL, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #2127 = ROR64r1
  { 2128,	2,	1,	0,	"ROR64rCL", 0, 0xd3001011ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #2128 = ROR64rCL
  { 2129,	3,	1,	0,	"ROR64ri", 0, 0xc1003011ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #2129 = ROR64ri
  { 2130,	5,	0,	0,	"ROR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd0000019ULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2130 = ROR8m1
  { 2131,	5,	0,	0,	"ROR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd2000019ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2131 = ROR8mCL
  { 2132,	6,	0,	0,	"ROR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc0002019ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2132 = ROR8mi
  { 2133,	2,	1,	0,	"ROR8r1", 0, 0xd0000011ULL, NULL, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #2133 = ROR8r1
  { 2134,	2,	1,	0,	"ROR8rCL", 0, 0xd2000011ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #2134 = ROR8rCL
  { 2135,	3,	1,	0,	"ROR8ri", 0, 0xc0002011ULL, NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #2135 = ROR8ri
  { 2136,	7,	1,	0,	"ROUNDPDm_Int", 0|(1<<TID::MayLoad), 0x9c02e46ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #2136 = ROUNDPDm_Int
  { 2137,	3,	1,	0,	"ROUNDPDr_Int", 0, 0x9c02e45ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #2137 = ROUNDPDr_Int
  { 2138,	7,	1,	0,	"ROUNDPSm_Int", 0|(1<<TID::MayLoad), 0x8002e46ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #2138 = ROUNDPSm_Int
  { 2139,	3,	1,	0,	"ROUNDPSr_Int", 0, 0x8c02e45ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #2139 = ROUNDPSr_Int
  { 2140,	8,	1,	0,	"ROUNDSDm_Int", 0|(1<<TID::MayLoad), 0xbc02e46ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #2140 = ROUNDSDm_Int
  { 2141,	4,	1,	0,	"ROUNDSDr_Int", 0, 0xbc02e45ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #2141 = ROUNDSDr_Int
  { 2142,	8,	1,	0,	"ROUNDSSm_Int", 0|(1<<TID::MayLoad), 0xac02e46ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #2142 = ROUNDSSm_Int
  { 2143,	4,	1,	0,	"ROUNDSSr_Int", 0, 0xac02e45ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #2143 = ROUNDSSr_Int
  { 2144,	0,	0,	0,	"RSM", 0|(1<<TID::UnmodeledSideEffects), 0xaa000101ULL, NULL, NULL, NULL, 0 },  // Inst #2144 = RSM
  { 2145,	6,	1,	0,	"RSQRTPSm", 0|(1<<TID::MayLoad), 0x52400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2145 = RSQRTPSm
  { 2146,	6,	1,	0,	"RSQRTPSm_Int", 0|(1<<TID::MayLoad), 0x52400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2146 = RSQRTPSm_Int
  { 2147,	2,	1,	0,	"RSQRTPSr", 0, 0x52400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2147 = RSQRTPSr
  { 2148,	2,	1,	0,	"RSQRTPSr_Int", 0, 0x52400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2148 = RSQRTPSr_Int
  { 2149,	6,	1,	0,	"RSQRTSSm", 0|(1<<TID::MayLoad), 0x52000c06ULL, NULL, NULL, NULL, OperandInfo92 },  // Inst #2149 = RSQRTSSm
  { 2150,	6,	1,	0,	"RSQRTSSm_Int", 0|(1<<TID::MayLoad), 0x52000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2150 = RSQRTSSm_Int
  { 2151,	2,	1,	0,	"RSQRTSSr", 0, 0x52000c05ULL, NULL, NULL, NULL, OperandInfo119 },  // Inst #2151 = RSQRTSSr
  { 2152,	2,	1,	0,	"RSQRTSSr_Int", 0, 0x52000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2152 = RSQRTSSr_Int
  { 2153,	0,	0,	0,	"SAHF", 0, 0x9e000001ULL, ImplicitList27, ImplicitList1, Barriers1, 0 },  // Inst #2153 = SAHF
  { 2154,	5,	0,	0,	"SAR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd100005fULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2154 = SAR16m1
  { 2155,	5,	0,	0,	"SAR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd300005fULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2155 = SAR16mCL
  { 2156,	6,	0,	0,	"SAR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc100205fULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2156 = SAR16mi
  { 2157,	2,	1,	0,	"SAR16r1", 0, 0xd1000057ULL, NULL, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #2157 = SAR16r1
  { 2158,	2,	1,	0,	"SAR16rCL", 0, 0xd3000057ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #2158 = SAR16rCL
  { 2159,	3,	1,	0,	"SAR16ri", 0, 0xc1002057ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #2159 = SAR16ri
  { 2160,	5,	0,	0,	"SAR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd100001fULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2160 = SAR32m1
  { 2161,	5,	0,	0,	"SAR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd300001fULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2161 = SAR32mCL
  { 2162,	6,	0,	0,	"SAR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc100201fULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2162 = SAR32mi
  { 2163,	2,	1,	0,	"SAR32r1", 0, 0xd1000017ULL, NULL, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #2163 = SAR32r1
  { 2164,	2,	1,	0,	"SAR32rCL", 0, 0xd3000017ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #2164 = SAR32rCL
  { 2165,	3,	1,	0,	"SAR32ri", 0, 0xc1002017ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #2165 = SAR32ri
  { 2166,	5,	0,	0,	"SAR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd100101fULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2166 = SAR64m1
  { 2167,	5,	0,	0,	"SAR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd300101fULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2167 = SAR64mCL
  { 2168,	6,	0,	0,	"SAR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc100301fULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2168 = SAR64mi
  { 2169,	2,	1,	0,	"SAR64r1", 0, 0xd1001017ULL, NULL, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #2169 = SAR64r1
  { 2170,	2,	1,	0,	"SAR64rCL", 0, 0xd3001017ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #2170 = SAR64rCL
  { 2171,	3,	1,	0,	"SAR64ri", 0, 0xc1003017ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #2171 = SAR64ri
  { 2172,	5,	0,	0,	"SAR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd000001fULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2172 = SAR8m1
  { 2173,	5,	0,	0,	"SAR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd200001fULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2173 = SAR8mCL
  { 2174,	6,	0,	0,	"SAR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc000201fULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2174 = SAR8mi
  { 2175,	2,	1,	0,	"SAR8r1", 0, 0xd0000017ULL, NULL, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #2175 = SAR8r1
  { 2176,	2,	1,	0,	"SAR8rCL", 0, 0xd2000017ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #2176 = SAR8rCL
  { 2177,	3,	1,	0,	"SAR8ri", 0, 0xc0002017ULL, NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #2177 = SAR8ri
  { 2178,	1,	0,	0,	"SBB16i16", 0|(1<<TID::UnmodeledSideEffects), 0x1d006041ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #2178 = SBB16i16
  { 2179,	6,	0,	0,	"SBB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100605bULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2179 = SBB16mi
  { 2180,	6,	0,	0,	"SBB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300205bULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2180 = SBB16mi8
  { 2181,	6,	0,	0,	"SBB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x19000044ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #2181 = SBB16mr
  { 2182,	3,	1,	0,	"SBB16ri", 0, 0x81006053ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #2182 = SBB16ri
  { 2183,	3,	1,	0,	"SBB16ri8", 0, 0x83002053ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #2183 = SBB16ri8
  { 2184,	7,	1,	0,	"SBB16rm", 0|(1<<TID::MayLoad), 0x1b000046ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 },  // Inst #2184 = SBB16rm
  { 2185,	3,	1,	0,	"SBB16rr", 0, 0x19000043ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #2185 = SBB16rr
  { 2186,	3,	1,	0,	"SBB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x1b000045ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #2186 = SBB16rr_REV
  { 2187,	1,	0,	0,	"SBB32i32", 0|(1<<TID::UnmodeledSideEffects), 0x1d00a001ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #2187 = SBB32i32
  { 2188,	6,	0,	0,	"SBB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100a01bULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2188 = SBB32mi
  { 2189,	6,	0,	0,	"SBB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300201bULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2189 = SBB32mi8
  { 2190,	6,	0,	0,	"SBB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x19000004ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #2190 = SBB32mr
  { 2191,	3,	1,	0,	"SBB32ri", 0, 0x8100a013ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #2191 = SBB32ri
  { 2192,	3,	1,	0,	"SBB32ri8", 0, 0x83002013ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #2192 = SBB32ri8
  { 2193,	7,	1,	0,	"SBB32rm", 0|(1<<TID::MayLoad), 0x1b000006ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 },  // Inst #2193 = SBB32rm
  { 2194,	3,	1,	0,	"SBB32rr", 0, 0x19000003ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #2194 = SBB32rr
  { 2195,	3,	1,	0,	"SBB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x1b000005ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #2195 = SBB32rr_REV
  { 2196,	1,	0,	0,	"SBB64i32", 0|(1<<TID::UnmodeledSideEffects), 0x1d00b001ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #2196 = SBB64i32
  { 2197,	6,	0,	0,	"SBB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100b01bULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2197 = SBB64mi32
  { 2198,	6,	0,	0,	"SBB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300301bULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2198 = SBB64mi8
  { 2199,	6,	0,	0,	"SBB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x19001004ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #2199 = SBB64mr
  { 2200,	3,	1,	0,	"SBB64ri32", 0, 0x8100b013ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #2200 = SBB64ri32
  { 2201,	3,	1,	0,	"SBB64ri8", 0, 0x83003013ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #2201 = SBB64ri8
  { 2202,	7,	1,	0,	"SBB64rm", 0|(1<<TID::MayLoad), 0x1b001006ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 },  // Inst #2202 = SBB64rm
  { 2203,	3,	1,	0,	"SBB64rr", 0, 0x19001003ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #2203 = SBB64rr
  { 2204,	3,	1,	0,	"SBB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x1b001005ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #2204 = SBB64rr_REV
  { 2205,	1,	0,	0,	"SBB8i8", 0|(1<<TID::UnmodeledSideEffects), 0x1c002001ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #2205 = SBB8i8
  { 2206,	6,	0,	0,	"SBB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8000201bULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2206 = SBB8mi
  { 2207,	6,	0,	0,	"SBB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x18000004ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo24 },  // Inst #2207 = SBB8mr
  { 2208,	3,	1,	0,	"SBB8ri", 0, 0x80002013ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #2208 = SBB8ri
  { 2209,	7,	1,	0,	"SBB8rm", 0|(1<<TID::MayLoad), 0x1a000006ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #2209 = SBB8rm
  { 2210,	3,	1,	0,	"SBB8rr", 0, 0x18000003ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #2210 = SBB8rr
  { 2211,	3,	1,	0,	"SBB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x1a000005ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #2211 = SBB8rr_REV
  { 2212,	0,	0,	0,	"SCAS16", 0|(1<<TID::UnmodeledSideEffects), 0xaf000041ULL, NULL, NULL, NULL, 0 },  // Inst #2212 = SCAS16
  { 2213,	0,	0,	0,	"SCAS32", 0|(1<<TID::UnmodeledSideEffects), 0xaf000001ULL, NULL, NULL, NULL, 0 },  // Inst #2213 = SCAS32
  { 2214,	0,	0,	0,	"SCAS64", 0|(1<<TID::UnmodeledSideEffects), 0xaf001001ULL, NULL, NULL, NULL, 0 },  // Inst #2214 = SCAS64
  { 2215,	0,	0,	0,	"SCAS8", 0|(1<<TID::UnmodeledSideEffects), 0xae000001ULL, NULL, NULL, NULL, 0 },  // Inst #2215 = SCAS8
  { 2216,	5,	0,	0,	"SETAEm", 0|(1<<TID::MayStore), 0x93000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2216 = SETAEm
  { 2217,	1,	1,	0,	"SETAEr", 0, 0x93000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2217 = SETAEr
  { 2218,	5,	0,	0,	"SETAm", 0|(1<<TID::MayStore), 0x97000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2218 = SETAm
  { 2219,	1,	1,	0,	"SETAr", 0, 0x97000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2219 = SETAr
  { 2220,	5,	0,	0,	"SETBEm", 0|(1<<TID::MayStore), 0x96000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2220 = SETBEm
  { 2221,	1,	1,	0,	"SETBEr", 0, 0x96000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2221 = SETBEr
  { 2222,	1,	1,	0,	"SETB_C16r", 0, 0x19000060ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo106 },  // Inst #2222 = SETB_C16r
  { 2223,	1,	1,	0,	"SETB_C32r", 0, 0x19000020ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo66 },  // Inst #2223 = SETB_C32r
  { 2224,	1,	1,	0,	"SETB_C64r", 0, 0x19001020ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo67 },  // Inst #2224 = SETB_C64r
  { 2225,	1,	1,	0,	"SETB_C8r", 0, 0x18000020ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo107 },  // Inst #2225 = SETB_C8r
  { 2226,	5,	0,	0,	"SETBm", 0|(1<<TID::MayStore), 0x92000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2226 = SETBm
  { 2227,	1,	1,	0,	"SETBr", 0, 0x92000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2227 = SETBr
  { 2228,	5,	0,	0,	"SETEm", 0|(1<<TID::MayStore), 0x94000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2228 = SETEm
  { 2229,	1,	1,	0,	"SETEr", 0, 0x94000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2229 = SETEr
  { 2230,	5,	0,	0,	"SETGEm", 0|(1<<TID::MayStore), 0x9d000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2230 = SETGEm
  { 2231,	1,	1,	0,	"SETGEr", 0, 0x9d000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2231 = SETGEr
  { 2232,	5,	0,	0,	"SETGm", 0|(1<<TID::MayStore), 0x9f000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2232 = SETGm
  { 2233,	1,	1,	0,	"SETGr", 0, 0x9f000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2233 = SETGr
  { 2234,	5,	0,	0,	"SETLEm", 0|(1<<TID::MayStore), 0x9e000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2234 = SETLEm
  { 2235,	1,	1,	0,	"SETLEr", 0, 0x9e000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2235 = SETLEr
  { 2236,	5,	0,	0,	"SETLm", 0|(1<<TID::MayStore), 0x9c000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2236 = SETLm
  { 2237,	1,	1,	0,	"SETLr", 0, 0x9c000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2237 = SETLr
  { 2238,	5,	0,	0,	"SETNEm", 0|(1<<TID::MayStore), 0x95000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2238 = SETNEm
  { 2239,	1,	1,	0,	"SETNEr", 0, 0x95000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2239 = SETNEr
  { 2240,	5,	0,	0,	"SETNOm", 0|(1<<TID::MayStore), 0x91000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2240 = SETNOm
  { 2241,	1,	1,	0,	"SETNOr", 0, 0x91000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2241 = SETNOr
  { 2242,	5,	0,	0,	"SETNPm", 0|(1<<TID::MayStore), 0x9b000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2242 = SETNPm
  { 2243,	1,	1,	0,	"SETNPr", 0, 0x9b000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2243 = SETNPr
  { 2244,	5,	0,	0,	"SETNSm", 0|(1<<TID::MayStore), 0x99000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2244 = SETNSm
  { 2245,	1,	1,	0,	"SETNSr", 0, 0x99000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2245 = SETNSr
  { 2246,	5,	0,	0,	"SETOm", 0|(1<<TID::MayStore), 0x90000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2246 = SETOm
  { 2247,	1,	1,	0,	"SETOr", 0, 0x90000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2247 = SETOr
  { 2248,	5,	0,	0,	"SETPm", 0|(1<<TID::MayStore), 0x9a000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2248 = SETPm
  { 2249,	1,	1,	0,	"SETPr", 0, 0x9a000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2249 = SETPr
  { 2250,	5,	0,	0,	"SETSm", 0|(1<<TID::MayStore), 0x98000118ULL, ImplicitList1, NULL, NULL, OperandInfo34 },  // Inst #2250 = SETSm
  { 2251,	1,	1,	0,	"SETSr", 0, 0x98000110ULL, ImplicitList1, NULL, NULL, OperandInfo107 },  // Inst #2251 = SETSr
  { 2252,	0,	0,	0,	"SFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xae000129ULL, NULL, NULL, NULL, 0 },  // Inst #2252 = SFENCE
  { 2253,	5,	1,	0,	"SGDTm", 0|(1<<TID::UnmodeledSideEffects), 0x1000118ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2253 = SGDTm
  { 2254,	5,	0,	0,	"SHL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd100005cULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2254 = SHL16m1
  { 2255,	5,	0,	0,	"SHL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd300005cULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2255 = SHL16mCL
  { 2256,	6,	0,	0,	"SHL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc100205cULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2256 = SHL16mi
  { 2257,	2,	1,	0,	"SHL16r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0xd1000054ULL, NULL, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #2257 = SHL16r1
  { 2258,	2,	1,	0,	"SHL16rCL", 0, 0xd3000054ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #2258 = SHL16rCL
  { 2259,	3,	1,	0,	"SHL16ri", 0|(1<<TID::ConvertibleTo3Addr), 0xc1002054ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #2259 = SHL16ri
  { 2260,	5,	0,	0,	"SHL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd100001cULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2260 = SHL32m1
  { 2261,	5,	0,	0,	"SHL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd300001cULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2261 = SHL32mCL
  { 2262,	6,	0,	0,	"SHL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc100201cULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2262 = SHL32mi
  { 2263,	2,	1,	0,	"SHL32r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0xd1000014ULL, NULL, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #2263 = SHL32r1
  { 2264,	2,	1,	0,	"SHL32rCL", 0, 0xd3000014ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #2264 = SHL32rCL
  { 2265,	3,	1,	0,	"SHL32ri", 0|(1<<TID::ConvertibleTo3Addr), 0xc1002014ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #2265 = SHL32ri
  { 2266,	5,	0,	0,	"SHL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd100101cULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2266 = SHL64m1
  { 2267,	5,	0,	0,	"SHL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd300101cULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2267 = SHL64mCL
  { 2268,	6,	0,	0,	"SHL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc100301cULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2268 = SHL64mi
  { 2269,	2,	1,	0,	"SHL64r1", 0|(1<<TID::UnmodeledSideEffects), 0xd1001014ULL, NULL, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #2269 = SHL64r1
  { 2270,	2,	1,	0,	"SHL64rCL", 0, 0xd3001014ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #2270 = SHL64rCL
  { 2271,	3,	1,	0,	"SHL64ri", 0|(1<<TID::ConvertibleTo3Addr), 0xc1003014ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #2271 = SHL64ri
  { 2272,	5,	0,	0,	"SHL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd000001cULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2272 = SHL8m1
  { 2273,	5,	0,	0,	"SHL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd200001cULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2273 = SHL8mCL
  { 2274,	6,	0,	0,	"SHL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc000201cULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2274 = SHL8mi
  { 2275,	2,	1,	0,	"SHL8r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0xd0000014ULL, NULL, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #2275 = SHL8r1
  { 2276,	2,	1,	0,	"SHL8rCL", 0, 0xd2000014ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #2276 = SHL8rCL
  { 2277,	3,	1,	0,	"SHL8ri", 0, 0xc0002014ULL, NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #2277 = SHL8ri
  { 2278,	6,	0,	0,	"SHLD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xa5000144ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #2278 = SHLD16mrCL
  { 2279,	7,	0,	0,	"SHLD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xa4002144ULL, NULL, ImplicitList1, Barriers1, OperandInfo210 },  // Inst #2279 = SHLD16mri8
  { 2280,	3,	1,	0,	"SHLD16rrCL", 0, 0xa5000143ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #2280 = SHLD16rrCL
  { 2281,	4,	1,	0,	"SHLD16rri8", 0|(1<<TID::Commutable), 0xa4002143ULL, NULL, ImplicitList1, Barriers1, OperandInfo211 },  // Inst #2281 = SHLD16rri8
  { 2282,	6,	0,	0,	"SHLD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xa5000104ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #2282 = SHLD32mrCL
  { 2283,	7,	0,	0,	"SHLD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xa4002104ULL, NULL, ImplicitList1, Barriers1, OperandInfo212 },  // Inst #2283 = SHLD32mri8
  { 2284,	3,	1,	0,	"SHLD32rrCL", 0, 0xa5000103ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #2284 = SHLD32rrCL
  { 2285,	4,	1,	0,	"SHLD32rri8", 0|(1<<TID::Commutable), 0xa4002103ULL, NULL, ImplicitList1, Barriers1, OperandInfo213 },  // Inst #2285 = SHLD32rri8
  { 2286,	6,	0,	0,	"SHLD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xa5001104ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #2286 = SHLD64mrCL
  { 2287,	7,	0,	0,	"SHLD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xa4003104ULL, NULL, ImplicitList1, Barriers1, OperandInfo214 },  // Inst #2287 = SHLD64mri8
  { 2288,	3,	1,	0,	"SHLD64rrCL", 0, 0xa5001103ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #2288 = SHLD64rrCL
  { 2289,	4,	1,	0,	"SHLD64rri8", 0|(1<<TID::Commutable), 0xa4003103ULL, NULL, ImplicitList1, Barriers1, OperandInfo215 },  // Inst #2289 = SHLD64rri8
  { 2290,	5,	0,	0,	"SHR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd100005dULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2290 = SHR16m1
  { 2291,	5,	0,	0,	"SHR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd300005dULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2291 = SHR16mCL
  { 2292,	6,	0,	0,	"SHR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc100205dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2292 = SHR16mi
  { 2293,	2,	1,	0,	"SHR16r1", 0, 0xd1000055ULL, NULL, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #2293 = SHR16r1
  { 2294,	2,	1,	0,	"SHR16rCL", 0, 0xd3000055ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo104 },  // Inst #2294 = SHR16rCL
  { 2295,	3,	1,	0,	"SHR16ri", 0, 0xc1002055ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #2295 = SHR16ri
  { 2296,	5,	0,	0,	"SHR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd100001dULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2296 = SHR32m1
  { 2297,	5,	0,	0,	"SHR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd300001dULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2297 = SHR32mCL
  { 2298,	6,	0,	0,	"SHR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc100201dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2298 = SHR32mi
  { 2299,	2,	1,	0,	"SHR32r1", 0, 0xd1000015ULL, NULL, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #2299 = SHR32r1
  { 2300,	2,	1,	0,	"SHR32rCL", 0, 0xd3000015ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo61 },  // Inst #2300 = SHR32rCL
  { 2301,	3,	1,	0,	"SHR32ri", 0, 0xc1002015ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #2301 = SHR32ri
  { 2302,	5,	0,	0,	"SHR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd100101dULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2302 = SHR64m1
  { 2303,	5,	0,	0,	"SHR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd300101dULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2303 = SHR64mCL
  { 2304,	6,	0,	0,	"SHR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc100301dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2304 = SHR64mi
  { 2305,	2,	1,	0,	"SHR64r1", 0, 0xd1001015ULL, NULL, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #2305 = SHR64r1
  { 2306,	2,	1,	0,	"SHR64rCL", 0, 0xd3001015ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo62 },  // Inst #2306 = SHR64rCL
  { 2307,	3,	1,	0,	"SHR64ri", 0, 0xc1003015ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #2307 = SHR64ri
  { 2308,	5,	0,	0,	"SHR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd000001dULL, NULL, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2308 = SHR8m1
  { 2309,	5,	0,	0,	"SHR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xd200001dULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo34 },  // Inst #2309 = SHR8mCL
  { 2310,	6,	0,	0,	"SHR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xc000201dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2310 = SHR8mi
  { 2311,	2,	1,	0,	"SHR8r1", 0, 0xd0000015ULL, NULL, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #2311 = SHR8r1
  { 2312,	2,	1,	0,	"SHR8rCL", 0, 0xd2000015ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo105 },  // Inst #2312 = SHR8rCL
  { 2313,	3,	1,	0,	"SHR8ri", 0, 0xc0002015ULL, NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #2313 = SHR8ri
  { 2314,	6,	0,	0,	"SHRD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xad000144ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #2314 = SHRD16mrCL
  { 2315,	7,	0,	0,	"SHRD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xac002144ULL, NULL, ImplicitList1, Barriers1, OperandInfo210 },  // Inst #2315 = SHRD16mri8
  { 2316,	3,	1,	0,	"SHRD16rrCL", 0, 0xad000143ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #2316 = SHRD16rrCL
  { 2317,	4,	1,	0,	"SHRD16rri8", 0|(1<<TID::Commutable), 0xac002143ULL, NULL, ImplicitList1, Barriers1, OperandInfo211 },  // Inst #2317 = SHRD16rri8
  { 2318,	6,	0,	0,	"SHRD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xad000104ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #2318 = SHRD32mrCL
  { 2319,	7,	0,	0,	"SHRD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xac002104ULL, NULL, ImplicitList1, Barriers1, OperandInfo212 },  // Inst #2319 = SHRD32mri8
  { 2320,	3,	1,	0,	"SHRD32rrCL", 0, 0xad000103ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #2320 = SHRD32rrCL
  { 2321,	4,	1,	0,	"SHRD32rri8", 0|(1<<TID::Commutable), 0xac002103ULL, NULL, ImplicitList1, Barriers1, OperandInfo213 },  // Inst #2321 = SHRD32rri8
  { 2322,	6,	0,	0,	"SHRD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xad001104ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #2322 = SHRD64mrCL
  { 2323,	7,	0,	0,	"SHRD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0xac003104ULL, NULL, ImplicitList1, Barriers1, OperandInfo214 },  // Inst #2323 = SHRD64mri8
  { 2324,	3,	1,	0,	"SHRD64rrCL", 0, 0xad001103ULL, ImplicitList45, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #2324 = SHRD64rrCL
  { 2325,	4,	1,	0,	"SHRD64rri8", 0|(1<<TID::Commutable), 0xac003103ULL, NULL, ImplicitList1, Barriers1, OperandInfo215 },  // Inst #2325 = SHRD64rri8
  { 2326,	8,	1,	0,	"SHUFPDrmi", 0|(1<<TID::MayLoad), 0xc6802146ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #2326 = SHUFPDrmi
  { 2327,	4,	1,	0,	"SHUFPDrri", 0, 0xc6802145ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #2327 = SHUFPDrri
  { 2328,	8,	1,	0,	"SHUFPSrmi", 0|(1<<TID::MayLoad), 0xc6402106ULL, NULL, NULL, NULL, OperandInfo53 },  // Inst #2328 = SHUFPSrmi
  { 2329,	4,	1,	0,	"SHUFPSrri", 0|(1<<TID::ConvertibleTo3Addr), 0xc6402105ULL, NULL, NULL, NULL, OperandInfo54 },  // Inst #2329 = SHUFPSrri
  { 2330,	5,	1,	0,	"SIDTm", 0|(1<<TID::UnmodeledSideEffects), 0x1000119ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2330 = SIDTm
  { 2331,	0,	0,	0,	"SIN_F", 0|(1<<TID::UnmodeledSideEffects), 0xfe000401ULL, NULL, NULL, NULL, 0 },  // Inst #2331 = SIN_F
  { 2332,	2,	1,	0,	"SIN_Fp32", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo7 },  // Inst #2332 = SIN_Fp32
  { 2333,	2,	1,	0,	"SIN_Fp64", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo8 },  // Inst #2333 = SIN_Fp64
  { 2334,	2,	1,	0,	"SIN_Fp80", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo9 },  // Inst #2334 = SIN_Fp80
  { 2335,	5,	1,	0,	"SLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0x118ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2335 = SLDT16m
  { 2336,	1,	1,	0,	"SLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0x110ULL, NULL, NULL, NULL, OperandInfo106 },  // Inst #2336 = SLDT16r
  { 2337,	5,	1,	0,	"SLDT64m", 0|(1<<TID::UnmodeledSideEffects), 0x1118ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2337 = SLDT64m
  { 2338,	1,	1,	0,	"SLDT64r", 0|(1<<TID::UnmodeledSideEffects), 0x1110ULL, NULL, NULL, NULL, OperandInfo67 },  // Inst #2338 = SLDT64r
  { 2339,	5,	1,	0,	"SMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0x100011cULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2339 = SMSW16m
  { 2340,	1,	1,	0,	"SMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0x1000154ULL, NULL, NULL, NULL, OperandInfo106 },  // Inst #2340 = SMSW16r
  { 2341,	1,	1,	0,	"SMSW32r", 0|(1<<TID::UnmodeledSideEffects), 0x1000114ULL, NULL, NULL, NULL, OperandInfo66 },  // Inst #2341 = SMSW32r
  { 2342,	1,	1,	0,	"SMSW64r", 0|(1<<TID::UnmodeledSideEffects), 0x1001114ULL, NULL, NULL, NULL, OperandInfo67 },  // Inst #2342 = SMSW64r
  { 2343,	6,	1,	0,	"SQRTPDm", 0|(1<<TID::MayLoad), 0x51800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2343 = SQRTPDm
  { 2344,	6,	1,	0,	"SQRTPDm_Int", 0|(1<<TID::MayLoad), 0x51800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2344 = SQRTPDm_Int
  { 2345,	2,	1,	0,	"SQRTPDr", 0, 0x51800145ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2345 = SQRTPDr
  { 2346,	2,	1,	0,	"SQRTPDr_Int", 0, 0x51800145ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2346 = SQRTPDr_Int
  { 2347,	6,	1,	0,	"SQRTPSm", 0|(1<<TID::MayLoad), 0x51400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2347 = SQRTPSm
  { 2348,	6,	1,	0,	"SQRTPSm_Int", 0|(1<<TID::MayLoad), 0x51400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2348 = SQRTPSm_Int
  { 2349,	2,	1,	0,	"SQRTPSr", 0, 0x51400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2349 = SQRTPSr
  { 2350,	2,	1,	0,	"SQRTPSr_Int", 0, 0x51400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2350 = SQRTPSr_Int
  { 2351,	6,	1,	0,	"SQRTSDm", 0|(1<<TID::MayLoad), 0x51000b06ULL, NULL, NULL, NULL, OperandInfo94 },  // Inst #2351 = SQRTSDm
  { 2352,	6,	1,	0,	"SQRTSDm_Int", 0|(1<<TID::MayLoad), 0x51000b06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2352 = SQRTSDm_Int
  { 2353,	2,	1,	0,	"SQRTSDr", 0, 0x51000b05ULL, NULL, NULL, NULL, OperandInfo118 },  // Inst #2353 = SQRTSDr
  { 2354,	2,	1,	0,	"SQRTSDr_Int", 0, 0x51000b05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2354 = SQRTSDr_Int
  { 2355,	6,	1,	0,	"SQRTSSm", 0|(1<<TID::MayLoad), 0x51000c06ULL, NULL, NULL, NULL, OperandInfo92 },  // Inst #2355 = SQRTSSm
  { 2356,	6,	1,	0,	"SQRTSSm_Int", 0|(1<<TID::MayLoad), 0x51000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2356 = SQRTSSm_Int
  { 2357,	2,	1,	0,	"SQRTSSr", 0, 0x51000c05ULL, NULL, NULL, NULL, OperandInfo119 },  // Inst #2357 = SQRTSSr
  { 2358,	2,	1,	0,	"SQRTSSr_Int", 0, 0x51000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2358 = SQRTSSr_Int
  { 2359,	0,	0,	0,	"SQRT_F", 0|(1<<TID::UnmodeledSideEffects), 0xfa000401ULL, NULL, NULL, NULL, 0 },  // Inst #2359 = SQRT_F
  { 2360,	2,	1,	0,	"SQRT_Fp32", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo7 },  // Inst #2360 = SQRT_Fp32
  { 2361,	2,	1,	0,	"SQRT_Fp64", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo8 },  // Inst #2361 = SQRT_Fp64
  { 2362,	2,	1,	0,	"SQRT_Fp80", 0, 0x30000ULL, NULL, NULL, NULL, OperandInfo9 },  // Inst #2362 = SQRT_Fp80
  { 2363,	0,	0,	0,	"SS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0x36000001ULL, NULL, NULL, NULL, 0 },  // Inst #2363 = SS_PREFIX
  { 2364,	0,	0,	0,	"STC", 0|(1<<TID::UnmodeledSideEffects), 0xf9000001ULL, NULL, NULL, NULL, 0 },  // Inst #2364 = STC
  { 2365,	0,	0,	0,	"STD", 0|(1<<TID::UnmodeledSideEffects), 0xfd000001ULL, NULL, NULL, NULL, 0 },  // Inst #2365 = STD
  { 2366,	0,	0,	0,	"STI", 0|(1<<TID::UnmodeledSideEffects), 0xfb000001ULL, NULL, NULL, NULL, 0 },  // Inst #2366 = STI
  { 2367,	5,	0,	0,	"STMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xae40011bULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2367 = STMXCSR
  { 2368,	0,	0,	0,	"STOSB", 0|(1<<TID::UnmodeledSideEffects), 0xaa000001ULL, ImplicitList55, ImplicitList34, NULL, 0 },  // Inst #2368 = STOSB
  { 2369,	0,	0,	0,	"STOSD", 0|(1<<TID::UnmodeledSideEffects), 0xab000001ULL, ImplicitList56, ImplicitList34, NULL, 0 },  // Inst #2369 = STOSD
  { 2370,	0,	0,	0,	"STOSQ", 0|(1<<TID::UnmodeledSideEffects), 0xab001001ULL, ImplicitList57, ImplicitList53, NULL, 0 },  // Inst #2370 = STOSQ
  { 2371,	0,	0,	0,	"STOSW", 0|(1<<TID::UnmodeledSideEffects), 0xab000041ULL, ImplicitList58, ImplicitList34, NULL, 0 },  // Inst #2371 = STOSW
  { 2372,	5,	1,	0,	"STRm", 0|(1<<TID::UnmodeledSideEffects), 0x119ULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2372 = STRm
  { 2373,	1,	1,	0,	"STRr", 0|(1<<TID::UnmodeledSideEffects), 0x111ULL, NULL, NULL, NULL, OperandInfo106 },  // Inst #2373 = STRr
  { 2374,	5,	0,	0,	"ST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xd900001aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2374 = ST_F32m
  { 2375,	5,	0,	0,	"ST_F64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xdd00001aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2375 = ST_F64m
  { 2376,	5,	0,	0,	"ST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xd900001bULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2376 = ST_FP32m
  { 2377,	5,	0,	0,	"ST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xdd00001bULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2377 = ST_FP64m
  { 2378,	5,	0,	0,	"ST_FP80m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xdb00001fULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2378 = ST_FP80m
  { 2379,	1,	0,	0,	"ST_FPrr", 0|(1<<TID::UnmodeledSideEffects), 0xd8000802ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #2379 = ST_FPrr
  { 2380,	6,	0,	0,	"ST_Fp32m", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo110 },  // Inst #2380 = ST_Fp32m
  { 2381,	6,	0,	0,	"ST_Fp64m", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo111 },  // Inst #2381 = ST_Fp64m
  { 2382,	6,	0,	0,	"ST_Fp64m32", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo111 },  // Inst #2382 = ST_Fp64m32
  { 2383,	6,	0,	0,	"ST_Fp80m32", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo112 },  // Inst #2383 = ST_Fp80m32
  { 2384,	6,	0,	0,	"ST_Fp80m64", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo112 },  // Inst #2384 = ST_Fp80m64
  { 2385,	6,	0,	0,	"ST_FpP32m", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo110 },  // Inst #2385 = ST_FpP32m
  { 2386,	6,	0,	0,	"ST_FpP64m", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo111 },  // Inst #2386 = ST_FpP64m
  { 2387,	6,	0,	0,	"ST_FpP64m32", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo111 },  // Inst #2387 = ST_FpP64m32
  { 2388,	6,	0,	0,	"ST_FpP80m", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo112 },  // Inst #2388 = ST_FpP80m
  { 2389,	6,	0,	0,	"ST_FpP80m32", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo112 },  // Inst #2389 = ST_FpP80m32
  { 2390,	6,	0,	0,	"ST_FpP80m64", 0|(1<<TID::MayStore), 0x20000ULL, NULL, NULL, NULL, OperandInfo112 },  // Inst #2390 = ST_FpP80m64
  { 2391,	1,	0,	0,	"ST_Frr", 0|(1<<TID::UnmodeledSideEffects), 0xd0000802ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #2391 = ST_Frr
  { 2392,	1,	0,	0,	"SUB16i16", 0|(1<<TID::UnmodeledSideEffects), 0x2d006041ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #2392 = SUB16i16
  { 2393,	6,	0,	0,	"SUB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100605dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2393 = SUB16mi
  { 2394,	6,	0,	0,	"SUB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300205dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2394 = SUB16mi8
  { 2395,	6,	0,	0,	"SUB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x29000044ULL, NULL, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #2395 = SUB16mr
  { 2396,	3,	1,	0,	"SUB16ri", 0, 0x81006055ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #2396 = SUB16ri
  { 2397,	3,	1,	0,	"SUB16ri8", 0, 0x83002055ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #2397 = SUB16ri8
  { 2398,	7,	1,	0,	"SUB16rm", 0|(1<<TID::MayLoad), 0x2b000046ULL, NULL, ImplicitList1, Barriers1, OperandInfo13 },  // Inst #2398 = SUB16rm
  { 2399,	3,	1,	0,	"SUB16rr", 0, 0x29000043ULL, NULL, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #2399 = SUB16rr
  { 2400,	3,	1,	0,	"SUB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x2b000045ULL, NULL, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #2400 = SUB16rr_REV
  { 2401,	1,	0,	0,	"SUB32i32", 0|(1<<TID::UnmodeledSideEffects), 0x2d00a001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #2401 = SUB32i32
  { 2402,	6,	0,	0,	"SUB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100a01dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2402 = SUB32mi
  { 2403,	6,	0,	0,	"SUB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300201dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2403 = SUB32mi8
  { 2404,	6,	0,	0,	"SUB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x29000004ULL, NULL, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #2404 = SUB32mr
  { 2405,	3,	1,	0,	"SUB32ri", 0, 0x8100a015ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #2405 = SUB32ri
  { 2406,	3,	1,	0,	"SUB32ri8", 0, 0x83002015ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #2406 = SUB32ri8
  { 2407,	7,	1,	0,	"SUB32rm", 0|(1<<TID::MayLoad), 0x2b000006ULL, NULL, ImplicitList1, Barriers1, OperandInfo17 },  // Inst #2407 = SUB32rm
  { 2408,	3,	1,	0,	"SUB32rr", 0, 0x29000003ULL, NULL, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #2408 = SUB32rr
  { 2409,	3,	1,	0,	"SUB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x2b000005ULL, NULL, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #2409 = SUB32rr_REV
  { 2410,	1,	0,	0,	"SUB64i32", 0|(1<<TID::UnmodeledSideEffects), 0x2d00b001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #2410 = SUB64i32
  { 2411,	6,	0,	0,	"SUB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100b01dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2411 = SUB64mi32
  { 2412,	6,	0,	0,	"SUB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300301dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2412 = SUB64mi8
  { 2413,	6,	0,	0,	"SUB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x29001004ULL, NULL, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #2413 = SUB64mr
  { 2414,	3,	1,	0,	"SUB64ri32", 0, 0x8100b015ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #2414 = SUB64ri32
  { 2415,	3,	1,	0,	"SUB64ri8", 0, 0x83003015ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #2415 = SUB64ri8
  { 2416,	7,	1,	0,	"SUB64rm", 0|(1<<TID::MayLoad), 0x2b001006ULL, NULL, ImplicitList1, Barriers1, OperandInfo21 },  // Inst #2416 = SUB64rm
  { 2417,	3,	1,	0,	"SUB64rr", 0, 0x29001003ULL, NULL, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #2417 = SUB64rr
  { 2418,	3,	1,	0,	"SUB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x2b001005ULL, NULL, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #2418 = SUB64rr_REV
  { 2419,	1,	0,	0,	"SUB8i8", 0|(1<<TID::UnmodeledSideEffects), 0x2c002001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #2419 = SUB8i8
  { 2420,	6,	0,	0,	"SUB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8000201dULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2420 = SUB8mi
  { 2421,	6,	0,	0,	"SUB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x28000004ULL, NULL, ImplicitList1, Barriers1, OperandInfo24 },  // Inst #2421 = SUB8mr
  { 2422,	3,	1,	0,	"SUB8ri", 0, 0x80002015ULL, NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #2422 = SUB8ri
  { 2423,	7,	1,	0,	"SUB8rm", 0|(1<<TID::MayLoad), 0x2a000006ULL, NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #2423 = SUB8rm
  { 2424,	3,	1,	0,	"SUB8rr", 0, 0x28000003ULL, NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #2424 = SUB8rr
  { 2425,	3,	1,	0,	"SUB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x2a000005ULL, NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #2425 = SUB8rr_REV
  { 2426,	7,	1,	0,	"SUBPDrm", 0|(1<<TID::MayLoad), 0x5c800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #2426 = SUBPDrm
  { 2427,	3,	1,	0,	"SUBPDrr", 0, 0x5c800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #2427 = SUBPDrr
  { 2428,	7,	1,	0,	"SUBPSrm", 0|(1<<TID::MayLoad), 0x5c400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #2428 = SUBPSrm
  { 2429,	3,	1,	0,	"SUBPSrr", 0, 0x5c400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #2429 = SUBPSrr
  { 2430,	5,	0,	0,	"SUBR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xd800001dULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2430 = SUBR_F32m
  { 2431,	5,	0,	0,	"SUBR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xdc00001dULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2431 = SUBR_F64m
  { 2432,	5,	0,	0,	"SUBR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xde00001dULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2432 = SUBR_FI16m
  { 2433,	5,	0,	0,	"SUBR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xda00001dULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2433 = SUBR_FI32m
  { 2434,	1,	0,	0,	"SUBR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0xe0000902ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #2434 = SUBR_FPrST0
  { 2435,	1,	0,	0,	"SUBR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0xe8000302ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #2435 = SUBR_FST0r
  { 2436,	7,	1,	0,	"SUBR_Fp32m", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #2436 = SUBR_Fp32m
  { 2437,	7,	1,	0,	"SUBR_Fp64m", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #2437 = SUBR_Fp64m
  { 2438,	7,	1,	0,	"SUBR_Fp64m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #2438 = SUBR_Fp64m32
  { 2439,	7,	1,	0,	"SUBR_Fp80m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #2439 = SUBR_Fp80m32
  { 2440,	7,	1,	0,	"SUBR_Fp80m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #2440 = SUBR_Fp80m64
  { 2441,	7,	1,	0,	"SUBR_FpI16m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #2441 = SUBR_FpI16m32
  { 2442,	7,	1,	0,	"SUBR_FpI16m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #2442 = SUBR_FpI16m64
  { 2443,	7,	1,	0,	"SUBR_FpI16m80", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #2443 = SUBR_FpI16m80
  { 2444,	7,	1,	0,	"SUBR_FpI32m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #2444 = SUBR_FpI32m32
  { 2445,	7,	1,	0,	"SUBR_FpI32m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #2445 = SUBR_FpI32m64
  { 2446,	7,	1,	0,	"SUBR_FpI32m80", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #2446 = SUBR_FpI32m80
  { 2447,	1,	0,	0,	"SUBR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0xe0000702ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #2447 = SUBR_FrST0
  { 2448,	7,	1,	0,	"SUBSDrm", 0|(1<<TID::MayLoad), 0x5c000b06ULL, NULL, NULL, NULL, OperandInfo30 },  // Inst #2448 = SUBSDrm
  { 2449,	7,	1,	0,	"SUBSDrm_Int", 0|(1<<TID::MayLoad), 0x5c000b06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #2449 = SUBSDrm_Int
  { 2450,	3,	1,	0,	"SUBSDrr", 0, 0x5c000b05ULL, NULL, NULL, NULL, OperandInfo31 },  // Inst #2450 = SUBSDrr
  { 2451,	3,	1,	0,	"SUBSDrr_Int", 0, 0x5c000b05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #2451 = SUBSDrr_Int
  { 2452,	7,	1,	0,	"SUBSSrm", 0|(1<<TID::MayLoad), 0x5c000c06ULL, NULL, NULL, NULL, OperandInfo32 },  // Inst #2452 = SUBSSrm
  { 2453,	7,	1,	0,	"SUBSSrm_Int", 0|(1<<TID::MayLoad), 0x5c000c06ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #2453 = SUBSSrm_Int
  { 2454,	3,	1,	0,	"SUBSSrr", 0, 0x5c000c05ULL, NULL, NULL, NULL, OperandInfo33 },  // Inst #2454 = SUBSSrr
  { 2455,	3,	1,	0,	"SUBSSrr_Int", 0, 0x5c000c05ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #2455 = SUBSSrr_Int
  { 2456,	5,	0,	0,	"SUB_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xd800001cULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2456 = SUB_F32m
  { 2457,	5,	0,	0,	"SUB_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xdc00001cULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2457 = SUB_F64m
  { 2458,	5,	0,	0,	"SUB_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xde00001cULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2458 = SUB_FI16m
  { 2459,	5,	0,	0,	"SUB_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0xda00001cULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2459 = SUB_FI32m
  { 2460,	1,	0,	0,	"SUB_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0xe8000902ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #2460 = SUB_FPrST0
  { 2461,	1,	0,	0,	"SUB_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0xe0000302ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #2461 = SUB_FST0r
  { 2462,	3,	1,	0,	"SUB_Fp32", 0, 0x40000ULL, NULL, NULL, NULL, OperandInfo36 },  // Inst #2462 = SUB_Fp32
  { 2463,	7,	1,	0,	"SUB_Fp32m", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #2463 = SUB_Fp32m
  { 2464,	3,	1,	0,	"SUB_Fp64", 0, 0x40000ULL, NULL, NULL, NULL, OperandInfo38 },  // Inst #2464 = SUB_Fp64
  { 2465,	7,	1,	0,	"SUB_Fp64m", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #2465 = SUB_Fp64m
  { 2466,	7,	1,	0,	"SUB_Fp64m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #2466 = SUB_Fp64m32
  { 2467,	3,	1,	0,	"SUB_Fp80", 0, 0x40000ULL, NULL, NULL, NULL, OperandInfo40 },  // Inst #2467 = SUB_Fp80
  { 2468,	7,	1,	0,	"SUB_Fp80m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #2468 = SUB_Fp80m32
  { 2469,	7,	1,	0,	"SUB_Fp80m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #2469 = SUB_Fp80m64
  { 2470,	7,	1,	0,	"SUB_FpI16m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #2470 = SUB_FpI16m32
  { 2471,	7,	1,	0,	"SUB_FpI16m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #2471 = SUB_FpI16m64
  { 2472,	7,	1,	0,	"SUB_FpI16m80", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #2472 = SUB_FpI16m80
  { 2473,	7,	1,	0,	"SUB_FpI32m32", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo37 },  // Inst #2473 = SUB_FpI32m32
  { 2474,	7,	1,	0,	"SUB_FpI32m64", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo39 },  // Inst #2474 = SUB_FpI32m64
  { 2475,	7,	1,	0,	"SUB_FpI32m80", 0|(1<<TID::MayLoad), 0x30000ULL, NULL, NULL, NULL, OperandInfo41 },  // Inst #2475 = SUB_FpI32m80
  { 2476,	1,	0,	0,	"SUB_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0xe8000702ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #2476 = SUB_FrST0
  { 2477,	0,	0,	0,	"SWAPGS", 0|(1<<TID::UnmodeledSideEffects), 0x1000129ULL, NULL, NULL, NULL, 0 },  // Inst #2477 = SWAPGS
  { 2478,	0,	0,	0,	"SYSCALL", 0|(1<<TID::UnmodeledSideEffects), 0x5000101ULL, NULL, NULL, NULL, 0 },  // Inst #2478 = SYSCALL
  { 2479,	0,	0,	0,	"SYSENTER", 0|(1<<TID::UnmodeledSideEffects), 0x34000101ULL, NULL, NULL, NULL, 0 },  // Inst #2479 = SYSENTER
  { 2480,	0,	0,	0,	"SYSEXIT", 0|(1<<TID::UnmodeledSideEffects), 0x35000101ULL, NULL, NULL, NULL, 0 },  // Inst #2480 = SYSEXIT
  { 2481,	0,	0,	0,	"SYSEXIT64", 0|(1<<TID::UnmodeledSideEffects), 0x35001101ULL, NULL, NULL, NULL, 0 },  // Inst #2481 = SYSEXIT64
  { 2482,	0,	0,	0,	"SYSRET", 0|(1<<TID::UnmodeledSideEffects), 0x7000101ULL, NULL, NULL, NULL, 0 },  // Inst #2482 = SYSRET
  { 2483,	1,	0,	0,	"TAILJMPd", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0xe900c001ULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo2 },  // Inst #2483 = TAILJMPd
  { 2484,	1,	0,	0,	"TAILJMPd64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0xe900c001ULL, ImplicitList4, ImplicitList10, Barriers4, OperandInfo2 },  // Inst #2484 = TAILJMPd64
  { 2485,	5,	0,	0,	"TAILJMPm", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0xff00001cULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo216 },  // Inst #2485 = TAILJMPm
  { 2486,	5,	0,	0,	"TAILJMPm64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0xff00001cULL, ImplicitList4, ImplicitList10, Barriers4, OperandInfo217 },  // Inst #2486 = TAILJMPm64
  { 2487,	1,	0,	0,	"TAILJMPr", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0xff000014ULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo218 },  // Inst #2487 = TAILJMPr
  { 2488,	1,	0,	0,	"TAILJMPr64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0xff000014ULL, ImplicitList4, ImplicitList10, Barriers4, OperandInfo219 },  // Inst #2488 = TAILJMPr64
  { 2489,	2,	0,	0,	"TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo6 },  // Inst #2489 = TCRETURNdi
  { 2490,	2,	0,	0,	"TCRETURNdi64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList4, ImplicitList10, Barriers4, OperandInfo6 },  // Inst #2490 = TCRETURNdi64
  { 2491,	6,	0,	0,	"TCRETURNmi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo220 },  // Inst #2491 = TCRETURNmi
  { 2492,	6,	0,	0,	"TCRETURNmi64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList4, ImplicitList10, Barriers4, OperandInfo221 },  // Inst #2492 = TCRETURNmi64
  { 2493,	2,	0,	0,	"TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo222 },  // Inst #2493 = TCRETURNri
  { 2494,	2,	0,	0,	"TCRETURNri64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList4, ImplicitList10, Barriers4, OperandInfo223 },  // Inst #2494 = TCRETURNri64
  { 2495,	1,	0,	0,	"TEST16i16", 0|(1<<TID::UnmodeledSideEffects), 0xa9006041ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #2495 = TEST16i16
  { 2496,	6,	0,	0,	"TEST16mi", 0|(1<<TID::MayLoad), 0xf7006058ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2496 = TEST16mi
  { 2497,	2,	0,	0,	"TEST16ri", 0, 0xf7006050ULL, NULL, ImplicitList1, Barriers1, OperandInfo63 },  // Inst #2497 = TEST16ri
  { 2498,	6,	0,	0,	"TEST16rm", 0|(1<<TID::MayLoad), 0x85000046ULL, NULL, ImplicitList1, Barriers1, OperandInfo55 },  // Inst #2498 = TEST16rm
  { 2499,	2,	0,	0,	"TEST16rr", 0|(1<<TID::Commutable), 0x85000045ULL, NULL, ImplicitList1, Barriers1, OperandInfo56 },  // Inst #2499 = TEST16rr
  { 2500,	1,	0,	0,	"TEST32i32", 0|(1<<TID::UnmodeledSideEffects), 0xa900a001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #2500 = TEST32i32
  { 2501,	6,	0,	0,	"TEST32mi", 0|(1<<TID::MayLoad), 0xf700a018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2501 = TEST32mi
  { 2502,	2,	0,	0,	"TEST32ri", 0, 0xf700a010ULL, NULL, ImplicitList1, Barriers1, OperandInfo64 },  // Inst #2502 = TEST32ri
  { 2503,	6,	0,	0,	"TEST32rm", 0|(1<<TID::MayLoad), 0x85000006ULL, NULL, ImplicitList1, Barriers1, OperandInfo57 },  // Inst #2503 = TEST32rm
  { 2504,	2,	0,	0,	"TEST32rr", 0|(1<<TID::Commutable), 0x85000005ULL, NULL, ImplicitList1, Barriers1, OperandInfo58 },  // Inst #2504 = TEST32rr
  { 2505,	1,	0,	0,	"TEST64i32", 0|(1<<TID::UnmodeledSideEffects), 0xa900b001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #2505 = TEST64i32
  { 2506,	6,	0,	0,	"TEST64mi32", 0|(1<<TID::MayLoad), 0xf700b018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2506 = TEST64mi32
  { 2507,	2,	0,	0,	"TEST64ri32", 0, 0xf700b010ULL, NULL, ImplicitList1, Barriers1, OperandInfo65 },  // Inst #2507 = TEST64ri32
  { 2508,	6,	0,	0,	"TEST64rm", 0|(1<<TID::MayLoad), 0x85001006ULL, NULL, ImplicitList1, Barriers1, OperandInfo59 },  // Inst #2508 = TEST64rm
  { 2509,	2,	0,	0,	"TEST64rr", 0|(1<<TID::Commutable), 0x85001005ULL, NULL, ImplicitList1, Barriers1, OperandInfo60 },  // Inst #2509 = TEST64rr
  { 2510,	1,	0,	0,	"TEST8i8", 0|(1<<TID::UnmodeledSideEffects), 0xa8002001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #2510 = TEST8i8
  { 2511,	6,	0,	0,	"TEST8mi", 0|(1<<TID::MayLoad), 0xf6002018ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #2511 = TEST8mi
  { 2512,	2,	0,	0,	"TEST8ri", 0, 0xf6002010ULL, NULL, ImplicitList1, Barriers1, OperandInfo81 },  // Inst #2512 = TEST8ri
  { 2513,	6,	0,	0,	"TEST8rm", 0|(1<<TID::MayLoad), 0x84000006ULL, NULL, ImplicitList1, Barriers1, OperandInfo82 },  // Inst #2513 = TEST8rm
  { 2514,	2,	0,	0,	"TEST8rr", 0|(1<<TID::Commutable), 0x84000005ULL, NULL, ImplicitList1, Barriers1, OperandInfo83 },  // Inst #2514 = TEST8rr
  { 2515,	5,	0,	0,	"TLSCall_32", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList2, ImplicitList59, NULL, OperandInfo34 },  // Inst #2515 = TLSCall_32
  { 2516,	5,	0,	0,	"TLSCall_64", 0|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList35, ImplicitList15, NULL, OperandInfo34 },  // Inst #2516 = TLSCall_64
  { 2517,	5,	0,	0,	"TLS_addr32", 0, 0x0ULL, ImplicitList2, ImplicitList9, Barriers3, OperandInfo34 },  // Inst #2517 = TLS_addr32
  { 2518,	5,	0,	0,	"TLS_addr64", 0, 0x0ULL, ImplicitList4, ImplicitList10, Barriers4, OperandInfo34 },  // Inst #2518 = TLS_addr64
  { 2519,	0,	0,	0,	"TRAP", 0|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0xb000101ULL, NULL, NULL, NULL, 0 },  // Inst #2519 = TRAP
  { 2520,	0,	0,	0,	"TST_F", 0|(1<<TID::UnmodeledSideEffects), 0xe4000401ULL, NULL, NULL, NULL, 0 },  // Inst #2520 = TST_F
  { 2521,	1,	0,	0,	"TST_Fp32", 0, 0x20000ULL, NULL, NULL, NULL, OperandInfo113 },  // Inst #2521 = TST_Fp32
  { 2522,	1,	0,	0,	"TST_Fp64", 0, 0x20000ULL, NULL, NULL, NULL, OperandInfo114 },  // Inst #2522 = TST_Fp64
  { 2523,	1,	0,	0,	"TST_Fp80", 0, 0x20000ULL, NULL, NULL, NULL, OperandInfo115 },  // Inst #2523 = TST_Fp80
  { 2524,	6,	0,	0,	"UCOMISDrm", 0|(1<<TID::MayLoad), 0x2e800146ULL, NULL, ImplicitList1, Barriers1, OperandInfo94 },  // Inst #2524 = UCOMISDrm
  { 2525,	2,	0,	0,	"UCOMISDrr", 0, 0x2e800145ULL, NULL, ImplicitList1, Barriers1, OperandInfo118 },  // Inst #2525 = UCOMISDrr
  { 2526,	6,	0,	0,	"UCOMISSrm", 0|(1<<TID::MayLoad), 0x2e400106ULL, NULL, ImplicitList1, Barriers1, OperandInfo92 },  // Inst #2526 = UCOMISSrm
  { 2527,	2,	0,	0,	"UCOMISSrr", 0, 0x2e400105ULL, NULL, ImplicitList1, Barriers1, OperandInfo119 },  // Inst #2527 = UCOMISSrr
  { 2528,	1,	0,	0,	"UCOM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0xe8000a02ULL, ImplicitList23, ImplicitList1, Barriers1, OperandInfo35 },  // Inst #2528 = UCOM_FIPr
  { 2529,	1,	0,	0,	"UCOM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0xe8000602ULL, ImplicitList23, ImplicitList1, Barriers1, OperandInfo35 },  // Inst #2529 = UCOM_FIr
  { 2530,	0,	0,	0,	"UCOM_FPPr", 0|(1<<TID::UnmodeledSideEffects), 0xe9000501ULL, ImplicitList23, ImplicitList1, Barriers1, 0 },  // Inst #2530 = UCOM_FPPr
  { 2531,	1,	0,	0,	"UCOM_FPr", 0|(1<<TID::UnmodeledSideEffects), 0xe8000802ULL, ImplicitList23, ImplicitList1, Barriers1, OperandInfo35 },  // Inst #2531 = UCOM_FPr
  { 2532,	2,	0,	0,	"UCOM_FpIr32", 0, 0x50000ULL, NULL, ImplicitList1, Barriers1, OperandInfo7 },  // Inst #2532 = UCOM_FpIr32
  { 2533,	2,	0,	0,	"UCOM_FpIr64", 0, 0x50000ULL, NULL, ImplicitList1, Barriers1, OperandInfo8 },  // Inst #2533 = UCOM_FpIr64
  { 2534,	2,	0,	0,	"UCOM_FpIr80", 0, 0x50000ULL, NULL, ImplicitList1, Barriers1, OperandInfo9 },  // Inst #2534 = UCOM_FpIr80
  { 2535,	2,	0,	0,	"UCOM_Fpr32", 0|(1<<TID::UnmodeledSideEffects), 0x50000ULL, NULL, ImplicitList1, Barriers1, OperandInfo7 },  // Inst #2535 = UCOM_Fpr32
  { 2536,	2,	0,	0,	"UCOM_Fpr64", 0|(1<<TID::UnmodeledSideEffects), 0x50000ULL, NULL, ImplicitList1, Barriers1, OperandInfo8 },  // Inst #2536 = UCOM_Fpr64
  { 2537,	2,	0,	0,	"UCOM_Fpr80", 0|(1<<TID::UnmodeledSideEffects), 0x50000ULL, NULL, ImplicitList1, Barriers1, OperandInfo9 },  // Inst #2537 = UCOM_Fpr80
  { 2538,	1,	0,	0,	"UCOM_Fr", 0|(1<<TID::UnmodeledSideEffects), 0xe0000802ULL, ImplicitList23, ImplicitList1, Barriers1, OperandInfo35 },  // Inst #2538 = UCOM_Fr
  { 2539,	7,	1,	0,	"UNPCKHPDrm", 0|(1<<TID::MayLoad), 0x15800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #2539 = UNPCKHPDrm
  { 2540,	3,	1,	0,	"UNPCKHPDrr", 0, 0x15800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #2540 = UNPCKHPDrr
  { 2541,	7,	1,	0,	"UNPCKHPSrm", 0|(1<<TID::MayLoad), 0x15400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #2541 = UNPCKHPSrm
  { 2542,	3,	1,	0,	"UNPCKHPSrr", 0, 0x15400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #2542 = UNPCKHPSrr
  { 2543,	7,	1,	0,	"UNPCKLPDrm", 0|(1<<TID::MayLoad), 0x14800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #2543 = UNPCKLPDrm
  { 2544,	3,	1,	0,	"UNPCKLPDrr", 0, 0x14800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #2544 = UNPCKLPDrr
  { 2545,	7,	1,	0,	"UNPCKLPSrm", 0|(1<<TID::MayLoad), 0x14400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #2545 = UNPCKLPSrm
  { 2546,	3,	1,	0,	"UNPCKLPSrr", 0, 0x14400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #2546 = UNPCKLPSrr
  { 2547,	7,	1,	0,	"VADDPDYrm", 0|(1<<TID::MayLoad), 0x558800146ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2547 = VADDPDYrm
  { 2548,	3,	1,	0,	"VADDPDYrr", 0|(1<<TID::Commutable), 0x558800145ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2548 = VADDPDYrr
  { 2549,	7,	1,	0,	"VADDPDrm", 0|(1<<TID::MayLoad), 0x558800146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2549 = VADDPDrm
  { 2550,	3,	1,	0,	"VADDPDrr", 0|(1<<TID::Commutable), 0x558800145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2550 = VADDPDrr
  { 2551,	7,	1,	0,	"VADDPSYrm", 0|(1<<TID::MayLoad), 0x558400106ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2551 = VADDPSYrm
  { 2552,	3,	1,	0,	"VADDPSYrr", 0|(1<<TID::Commutable), 0x558400105ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2552 = VADDPSYrr
  { 2553,	7,	1,	0,	"VADDPSrm", 0|(1<<TID::MayLoad), 0x558400106ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2553 = VADDPSrm
  { 2554,	3,	1,	0,	"VADDPSrr", 0|(1<<TID::Commutable), 0x558400105ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2554 = VADDPSrr
  { 2555,	7,	1,	0,	"VADDSDrm", 0|(1<<TID::MayLoad), 0x558000b06ULL, NULL, NULL, NULL, OperandInfo226 },  // Inst #2555 = VADDSDrm
  { 2556,	7,	1,	0,	"VADDSDrm_Int", 0|(1<<TID::MayLoad), 0x558000b06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2556 = VADDSDrm_Int
  { 2557,	3,	1,	0,	"VADDSDrr", 0|(1<<TID::Commutable), 0x558000b05ULL, NULL, NULL, NULL, OperandInfo227 },  // Inst #2557 = VADDSDrr
  { 2558,	3,	1,	0,	"VADDSDrr_Int", 0, 0x558000b05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2558 = VADDSDrr_Int
  { 2559,	7,	1,	0,	"VADDSSrm", 0|(1<<TID::MayLoad), 0x558000c06ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #2559 = VADDSSrm
  { 2560,	7,	1,	0,	"VADDSSrm_Int", 0|(1<<TID::MayLoad), 0x558000c06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2560 = VADDSSrm_Int
  { 2561,	3,	1,	0,	"VADDSSrr", 0|(1<<TID::Commutable), 0x558000c05ULL, NULL, NULL, NULL, OperandInfo229 },  // Inst #2561 = VADDSSrr
  { 2562,	3,	1,	0,	"VADDSSrr_Int", 0, 0x558000c05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2562 = VADDSSrr_Int
  { 2563,	7,	1,	0,	"VADDSUBPDYrm", 0|(1<<TID::MayLoad), 0x5d0800046ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2563 = VADDSUBPDYrm
  { 2564,	3,	1,	0,	"VADDSUBPDYrr", 0, 0x5d0800045ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2564 = VADDSUBPDYrr
  { 2565,	7,	1,	0,	"VADDSUBPDrm", 0|(1<<TID::MayLoad), 0x5d0800046ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2565 = VADDSUBPDrm
  { 2566,	3,	1,	0,	"VADDSUBPDrr", 0, 0x5d0800045ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2566 = VADDSUBPDrr
  { 2567,	7,	1,	0,	"VADDSUBPSYrm", 0|(1<<TID::MayLoad), 0x5d0800b06ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2567 = VADDSUBPSYrm
  { 2568,	3,	1,	0,	"VADDSUBPSYrr", 0, 0x5d0800b05ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2568 = VADDSUBPSYrr
  { 2569,	7,	1,	0,	"VADDSUBPSrm", 0|(1<<TID::MayLoad), 0x5d0800b06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2569 = VADDSUBPSrm
  { 2570,	3,	1,	0,	"VADDSUBPSrr", 0, 0x5d0800b05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2570 = VADDSUBPSrr
  { 2571,	7,	1,	0,	"VAESDECLASTrm", 0|(1<<TID::MayLoad), 0x5dfc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2571 = VAESDECLASTrm
  { 2572,	3,	1,	0,	"VAESDECLASTrr", 0, 0x5dfc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2572 = VAESDECLASTrr
  { 2573,	7,	1,	0,	"VAESDECrm", 0|(1<<TID::MayLoad), 0x5dec00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2573 = VAESDECrm
  { 2574,	3,	1,	0,	"VAESDECrr", 0, 0x5dec00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2574 = VAESDECrr
  { 2575,	7,	1,	0,	"VAESENCLASTrm", 0|(1<<TID::MayLoad), 0x5ddc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2575 = VAESENCLASTrm
  { 2576,	3,	1,	0,	"VAESENCLASTrr", 0, 0x5ddc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2576 = VAESENCLASTrr
  { 2577,	7,	1,	0,	"VAESENCrm", 0|(1<<TID::MayLoad), 0x5dcc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2577 = VAESENCrm
  { 2578,	3,	1,	0,	"VAESENCrr", 0, 0x5dcc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2578 = VAESENCrr
  { 2579,	6,	1,	0,	"VAESIMCrm", 0|(1<<TID::MayLoad), 0x1dbc00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2579 = VAESIMCrm
  { 2580,	2,	1,	0,	"VAESIMCrr", 0, 0x1dbc00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2580 = VAESIMCrr
  { 2581,	7,	1,	0,	"VAESKEYGENASSIST128rm", 0|(1<<TID::MayLoad), 0x1dfc02e46ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #2581 = VAESKEYGENASSIST128rm
  { 2582,	3,	1,	0,	"VAESKEYGENASSIST128rr", 0, 0x1dfc02e45ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #2582 = VAESKEYGENASSIST128rr
  { 2583,	7,	1,	0,	"VANDNPDYrm", 0|(1<<TID::UnmodeledSideEffects), 0x555800046ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2583 = VANDNPDYrm
  { 2584,	3,	1,	0,	"VANDNPDYrr", 0|(1<<TID::UnmodeledSideEffects), 0x555800045ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2584 = VANDNPDYrr
  { 2585,	7,	1,	0,	"VANDNPDrm", 0|(1<<TID::UnmodeledSideEffects), 0x555800046ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2585 = VANDNPDrm
  { 2586,	3,	1,	0,	"VANDNPDrr", 0|(1<<TID::UnmodeledSideEffects), 0x555800045ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2586 = VANDNPDrr
  { 2587,	7,	1,	0,	"VANDNPSYrm", 0|(1<<TID::UnmodeledSideEffects), 0x555400006ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2587 = VANDNPSYrm
  { 2588,	3,	1,	0,	"VANDNPSYrr", 0|(1<<TID::UnmodeledSideEffects), 0x555400005ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2588 = VANDNPSYrr
  { 2589,	7,	1,	0,	"VANDNPSrm", 0|(1<<TID::UnmodeledSideEffects), 0x555400006ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2589 = VANDNPSrm
  { 2590,	3,	1,	0,	"VANDNPSrr", 0|(1<<TID::UnmodeledSideEffects), 0x555400005ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2590 = VANDNPSrr
  { 2591,	7,	1,	0,	"VANDPDYrm", 0|(1<<TID::UnmodeledSideEffects), 0x554800046ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2591 = VANDPDYrm
  { 2592,	3,	1,	0,	"VANDPDYrr", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0x554800045ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2592 = VANDPDYrr
  { 2593,	7,	1,	0,	"VANDPDrm", 0|(1<<TID::UnmodeledSideEffects), 0x554800046ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2593 = VANDPDrm
  { 2594,	3,	1,	0,	"VANDPDrr", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0x554800045ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2594 = VANDPDrr
  { 2595,	7,	1,	0,	"VANDPSYrm", 0|(1<<TID::UnmodeledSideEffects), 0x554400006ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2595 = VANDPSYrm
  { 2596,	3,	1,	0,	"VANDPSYrr", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0x554400005ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2596 = VANDPSYrr
  { 2597,	7,	1,	0,	"VANDPSrm", 0|(1<<TID::UnmodeledSideEffects), 0x554400006ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2597 = VANDPSrm
  { 2598,	3,	1,	0,	"VANDPSrr", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0x554400005ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2598 = VANDPSrr
  { 2599,	3,	0,	0,	"VASTART_SAVE_XMM_REGS", 0|(1<<TID::UsesCustomInserter)|(1<<TID::Variadic), 0x0ULL, NULL, NULL, NULL, OperandInfo230 },  // Inst #2599 = VASTART_SAVE_XMM_REGS
  { 2600,	8,	1,	0,	"VBLENDPDYrmi", 0|(1<<TID::MayLoad), 0x50dc02e46ULL, NULL, NULL, NULL, OperandInfo231 },  // Inst #2600 = VBLENDPDYrmi
  { 2601,	4,	1,	0,	"VBLENDPDYrri", 0, 0x50dc02e45ULL, NULL, NULL, NULL, OperandInfo232 },  // Inst #2601 = VBLENDPDYrri
  { 2602,	8,	1,	0,	"VBLENDPDrmi", 0|(1<<TID::MayLoad), 0x50dc02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #2602 = VBLENDPDrmi
  { 2603,	4,	1,	0,	"VBLENDPDrri", 0, 0x50dc02e45ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #2603 = VBLENDPDrri
  { 2604,	8,	1,	0,	"VBLENDPSYrmi", 0|(1<<TID::MayLoad), 0x50cc02e46ULL, NULL, NULL, NULL, OperandInfo231 },  // Inst #2604 = VBLENDPSYrmi
  { 2605,	4,	1,	0,	"VBLENDPSYrri", 0, 0x50cc02e45ULL, NULL, NULL, NULL, OperandInfo232 },  // Inst #2605 = VBLENDPSYrri
  { 2606,	8,	1,	0,	"VBLENDPSrmi", 0|(1<<TID::MayLoad), 0x50cc02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #2606 = VBLENDPSrmi
  { 2607,	4,	1,	0,	"VBLENDPSrri", 0, 0x50cc02e45ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #2607 = VBLENDPSrri
  { 2608,	8,	1,	0,	"VBLENDVPDYrm", 0|(1<<TID::MayLoad), 0xd4bc00e46ULL, NULL, NULL, NULL, OperandInfo233 },  // Inst #2608 = VBLENDVPDYrm
  { 2609,	4,	1,	0,	"VBLENDVPDYrr", 0, 0xd4bc00e45ULL, NULL, NULL, NULL, OperandInfo234 },  // Inst #2609 = VBLENDVPDYrr
  { 2610,	8,	1,	0,	"VBLENDVPDrm", 0|(1<<TID::MayLoad), 0xd4bc00e46ULL, NULL, NULL, NULL, OperandInfo235 },  // Inst #2610 = VBLENDVPDrm
  { 2611,	4,	1,	0,	"VBLENDVPDrr", 0, 0xd4bc00e45ULL, NULL, NULL, NULL, OperandInfo236 },  // Inst #2611 = VBLENDVPDrr
  { 2612,	8,	1,	0,	"VBLENDVPSYrm", 0|(1<<TID::MayLoad), 0xd4ac00e46ULL, NULL, NULL, NULL, OperandInfo233 },  // Inst #2612 = VBLENDVPSYrm
  { 2613,	4,	1,	0,	"VBLENDVPSYrr", 0, 0xd4ac00e45ULL, NULL, NULL, NULL, OperandInfo234 },  // Inst #2613 = VBLENDVPSYrr
  { 2614,	8,	1,	0,	"VBLENDVPSrm", 0|(1<<TID::MayLoad), 0xd4ac00e46ULL, NULL, NULL, NULL, OperandInfo235 },  // Inst #2614 = VBLENDVPSrm
  { 2615,	4,	1,	0,	"VBLENDVPSrr", 0, 0xd4ac00e45ULL, NULL, NULL, NULL, OperandInfo236 },  // Inst #2615 = VBLENDVPSrr
  { 2616,	6,	1,	0,	"VBROADCASTF128", 0|(1<<TID::MayLoad), 0x11ac00d46ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #2616 = VBROADCASTF128
  { 2617,	6,	1,	0,	"VBROADCASTSD", 0|(1<<TID::MayLoad), 0x119c00d46ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #2617 = VBROADCASTSD
  { 2618,	6,	1,	0,	"VBROADCASTSS", 0|(1<<TID::MayLoad), 0x118c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2618 = VBROADCASTSS
  { 2619,	6,	1,	0,	"VBROADCASTSSY", 0|(1<<TID::MayLoad), 0x118c00d46ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #2619 = VBROADCASTSSY
  { 2620,	8,	1,	0,	"VCMPPDYrmi", 0|(1<<TID::MayLoad), 0x5c2802046ULL, NULL, NULL, NULL, OperandInfo231 },  // Inst #2620 = VCMPPDYrmi
  { 2621,	8,	1,	0,	"VCMPPDYrmi_alt", 0|(1<<TID::UnmodeledSideEffects), 0x5c2802046ULL, NULL, NULL, NULL, OperandInfo231 },  // Inst #2621 = VCMPPDYrmi_alt
  { 2622,	4,	1,	0,	"VCMPPDYrri", 0, 0x5c2802045ULL, NULL, NULL, NULL, OperandInfo232 },  // Inst #2622 = VCMPPDYrri
  { 2623,	4,	1,	0,	"VCMPPDYrri_alt", 0|(1<<TID::UnmodeledSideEffects), 0x5c2802045ULL, NULL, NULL, NULL, OperandInfo232 },  // Inst #2623 = VCMPPDYrri_alt
  { 2624,	8,	1,	0,	"VCMPPDrmi", 0|(1<<TID::MayLoad), 0x5c2802046ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #2624 = VCMPPDrmi
  { 2625,	8,	1,	0,	"VCMPPDrmi_alt", 0|(1<<TID::UnmodeledSideEffects), 0x5c2802046ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #2625 = VCMPPDrmi_alt
  { 2626,	4,	1,	0,	"VCMPPDrri", 0, 0x5c2802045ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #2626 = VCMPPDrri
  { 2627,	4,	1,	0,	"VCMPPDrri_alt", 0|(1<<TID::UnmodeledSideEffects), 0x5c2802045ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #2627 = VCMPPDrri_alt
  { 2628,	8,	1,	0,	"VCMPPSYrmi", 0|(1<<TID::MayLoad), 0x5c2402006ULL, NULL, NULL, NULL, OperandInfo231 },  // Inst #2628 = VCMPPSYrmi
  { 2629,	8,	1,	0,	"VCMPPSYrmi_alt", 0|(1<<TID::UnmodeledSideEffects), 0x5c2402006ULL, NULL, NULL, NULL, OperandInfo231 },  // Inst #2629 = VCMPPSYrmi_alt
  { 2630,	4,	1,	0,	"VCMPPSYrri", 0, 0x5c2402005ULL, NULL, NULL, NULL, OperandInfo232 },  // Inst #2630 = VCMPPSYrri
  { 2631,	4,	1,	0,	"VCMPPSYrri_alt", 0|(1<<TID::UnmodeledSideEffects), 0x5c2402005ULL, NULL, NULL, NULL, OperandInfo232 },  // Inst #2631 = VCMPPSYrri_alt
  { 2632,	8,	1,	0,	"VCMPPSrmi", 0|(1<<TID::MayLoad), 0x5c2402006ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #2632 = VCMPPSrmi
  { 2633,	8,	1,	0,	"VCMPPSrmi_alt", 0|(1<<TID::UnmodeledSideEffects), 0x5c2402006ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #2633 = VCMPPSrmi_alt
  { 2634,	4,	1,	0,	"VCMPPSrri", 0, 0x5c2402005ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #2634 = VCMPPSrri
  { 2635,	4,	1,	0,	"VCMPPSrri_alt", 0|(1<<TID::UnmodeledSideEffects), 0x5c2402005ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #2635 = VCMPPSrri_alt
  { 2636,	8,	1,	0,	"VCMPSDrm", 0|(1<<TID::MayLoad), 0x5c2002b06ULL, NULL, NULL, NULL, OperandInfo238 },  // Inst #2636 = VCMPSDrm
  { 2637,	8,	1,	0,	"VCMPSDrm_alt", 0|(1<<TID::MayLoad), 0x5c2002b06ULL, NULL, NULL, NULL, OperandInfo238 },  // Inst #2637 = VCMPSDrm_alt
  { 2638,	4,	1,	0,	"VCMPSDrr", 0, 0x5c2002b05ULL, NULL, NULL, NULL, OperandInfo72 },  // Inst #2638 = VCMPSDrr
  { 2639,	4,	1,	0,	"VCMPSDrr_alt", 0, 0x5c2002b05ULL, NULL, NULL, NULL, OperandInfo72 },  // Inst #2639 = VCMPSDrr_alt
  { 2640,	8,	1,	0,	"VCMPSSrm", 0|(1<<TID::MayLoad), 0x5c2002c06ULL, NULL, NULL, NULL, OperandInfo239 },  // Inst #2640 = VCMPSSrm
  { 2641,	8,	1,	0,	"VCMPSSrm_alt", 0|(1<<TID::MayLoad), 0x5c2002c06ULL, NULL, NULL, NULL, OperandInfo239 },  // Inst #2641 = VCMPSSrm_alt
  { 2642,	4,	1,	0,	"VCMPSSrr", 0, 0x5c2002c05ULL, NULL, NULL, NULL, OperandInfo71 },  // Inst #2642 = VCMPSSrr
  { 2643,	4,	1,	0,	"VCMPSSrr_alt", 0, 0x5c2002c05ULL, NULL, NULL, NULL, OperandInfo71 },  // Inst #2643 = VCMPSSrr_alt
  { 2644,	6,	0,	0,	"VCOMISDrm", 0|(1<<TID::UnmodeledSideEffects), 0x12f800046ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #2644 = VCOMISDrm
  { 2645,	2,	0,	0,	"VCOMISDrr", 0|(1<<TID::UnmodeledSideEffects), 0x12f800045ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #2645 = VCOMISDrr
  { 2646,	6,	0,	0,	"VCOMISSrm", 0|(1<<TID::UnmodeledSideEffects), 0x12f400006ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #2646 = VCOMISSrm
  { 2647,	2,	0,	0,	"VCOMISSrr", 0|(1<<TID::UnmodeledSideEffects), 0x12f400005ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #2647 = VCOMISSrr
  { 2648,	6,	1,	0,	"VCVTDQ2PDYrm", 0|(1<<TID::UnmodeledSideEffects), 0x1e6400c06ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #2648 = VCVTDQ2PDYrm
  { 2649,	2,	1,	0,	"VCVTDQ2PDYrr", 0|(1<<TID::UnmodeledSideEffects), 0x1e6400c05ULL, NULL, NULL, NULL, OperandInfo240 },  // Inst #2649 = VCVTDQ2PDYrr
  { 2650,	6,	1,	0,	"VCVTDQ2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0x1e6400c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2650 = VCVTDQ2PDrm
  { 2651,	2,	1,	0,	"VCVTDQ2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0x1e6400c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2651 = VCVTDQ2PDrr
  { 2652,	6,	1,	0,	"VCVTDQ2PSYrm", 0|(1<<TID::UnmodeledSideEffects), 0x15b400106ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #2652 = VCVTDQ2PSYrm
  { 2653,	2,	1,	0,	"VCVTDQ2PSYrr", 0|(1<<TID::UnmodeledSideEffects), 0x15b400105ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #2653 = VCVTDQ2PSYrr
  { 2654,	6,	1,	0,	"VCVTDQ2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0x15b400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2654 = VCVTDQ2PSrm
  { 2655,	2,	1,	0,	"VCVTDQ2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0x15b400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2655 = VCVTDQ2PSrr
  { 2656,	2,	1,	0,	"VCVTPD2DQXrYr", 0|(1<<TID::UnmodeledSideEffects), 0x1e6800b05ULL, NULL, NULL, NULL, OperandInfo242 },  // Inst #2656 = VCVTPD2DQXrYr
  { 2657,	6,	1,	0,	"VCVTPD2DQXrm", 0|(1<<TID::UnmodeledSideEffects), 0x1e6800b06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2657 = VCVTPD2DQXrm
  { 2658,	2,	1,	0,	"VCVTPD2DQXrr", 0|(1<<TID::UnmodeledSideEffects), 0x1e6800b05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2658 = VCVTPD2DQXrr
  { 2659,	6,	1,	0,	"VCVTPD2DQYrm", 0|(1<<TID::UnmodeledSideEffects), 0x11e6800b06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2659 = VCVTPD2DQYrm
  { 2660,	2,	1,	0,	"VCVTPD2DQYrr", 0|(1<<TID::UnmodeledSideEffects), 0x1e6800b05ULL, NULL, NULL, NULL, OperandInfo242 },  // Inst #2660 = VCVTPD2DQYrr
  { 2661,	2,	1,	0,	"VCVTPD2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0x1e6800b05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2661 = VCVTPD2DQrr
  { 2662,	2,	1,	0,	"VCVTPD2PSXrYr", 0|(1<<TID::UnmodeledSideEffects), 0x15a800045ULL, NULL, NULL, NULL, OperandInfo242 },  // Inst #2662 = VCVTPD2PSXrYr
  { 2663,	6,	1,	0,	"VCVTPD2PSXrm", 0|(1<<TID::UnmodeledSideEffects), 0x15a800046ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2663 = VCVTPD2PSXrm
  { 2664,	2,	1,	0,	"VCVTPD2PSXrr", 0|(1<<TID::UnmodeledSideEffects), 0x15a800045ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2664 = VCVTPD2PSXrr
  { 2665,	6,	1,	0,	"VCVTPD2PSYrm", 0|(1<<TID::UnmodeledSideEffects), 0x115a800046ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2665 = VCVTPD2PSYrm
  { 2666,	2,	1,	0,	"VCVTPD2PSYrr", 0|(1<<TID::UnmodeledSideEffects), 0x15a800045ULL, NULL, NULL, NULL, OperandInfo242 },  // Inst #2666 = VCVTPD2PSYrr
  { 2667,	2,	1,	0,	"VCVTPD2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0x15a800045ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2667 = VCVTPD2PSrr
  { 2668,	6,	1,	0,	"VCVTPS2DQYrm", 0|(1<<TID::UnmodeledSideEffects), 0x15b800046ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #2668 = VCVTPS2DQYrm
  { 2669,	2,	1,	0,	"VCVTPS2DQYrr", 0|(1<<TID::UnmodeledSideEffects), 0x15b800045ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #2669 = VCVTPS2DQYrr
  { 2670,	6,	1,	0,	"VCVTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0x15b800046ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2670 = VCVTPS2DQrm
  { 2671,	2,	1,	0,	"VCVTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0x15b800045ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2671 = VCVTPS2DQrr
  { 2672,	6,	1,	0,	"VCVTPS2PDYrm", 0|(1<<TID::UnmodeledSideEffects), 0x15a000006ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #2672 = VCVTPS2PDYrm
  { 2673,	2,	1,	0,	"VCVTPS2PDYrr", 0|(1<<TID::UnmodeledSideEffects), 0x15a000005ULL, NULL, NULL, NULL, OperandInfo240 },  // Inst #2673 = VCVTPS2PDYrr
  { 2674,	6,	1,	0,	"VCVTPS2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0x15a000006ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2674 = VCVTPS2PDrm
  { 2675,	2,	1,	0,	"VCVTPS2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0x15a000005ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2675 = VCVTPS2PDrr
  { 2676,	6,	1,	0,	"VCVTSD2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0x32d000b06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #2676 = VCVTSD2SI64rm
  { 2677,	2,	1,	0,	"VCVTSD2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0x32d000b05ULL, NULL, NULL, NULL, OperandInfo102 },  // Inst #2677 = VCVTSD2SI64rr
  { 2678,	6,	1,	0,	"VCVTSD2SI_altrm", 0|(1<<TID::UnmodeledSideEffects), 0x12d000b06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #2678 = VCVTSD2SI_altrm
  { 2679,	2,	1,	0,	"VCVTSD2SI_altrr", 0|(1<<TID::UnmodeledSideEffects), 0x12d000b05ULL, NULL, NULL, NULL, OperandInfo103 },  // Inst #2679 = VCVTSD2SI_altrr
  { 2680,	7,	1,	0,	"VCVTSD2SSrm", 0|(1<<TID::UnmodeledSideEffects), 0x55a000b06ULL, NULL, NULL, NULL, OperandInfo243 },  // Inst #2680 = VCVTSD2SSrm
  { 2681,	3,	1,	0,	"VCVTSD2SSrr", 0|(1<<TID::UnmodeledSideEffects), 0x55a000b05ULL, NULL, NULL, NULL, OperandInfo244 },  // Inst #2681 = VCVTSD2SSrr
  { 2682,	7,	1,	0,	"VCVTSI2SD64rm", 0|(1<<TID::UnmodeledSideEffects), 0x72a000b06ULL, NULL, NULL, NULL, OperandInfo226 },  // Inst #2682 = VCVTSI2SD64rm
  { 2683,	3,	1,	0,	"VCVTSI2SD64rr", 0|(1<<TID::UnmodeledSideEffects), 0x72a000b05ULL, NULL, NULL, NULL, OperandInfo245 },  // Inst #2683 = VCVTSI2SD64rr
  { 2684,	7,	1,	0,	"VCVTSI2SDLrm", 0|(1<<TID::UnmodeledSideEffects), 0x52a000b06ULL, NULL, NULL, NULL, OperandInfo226 },  // Inst #2684 = VCVTSI2SDLrm
  { 2685,	3,	1,	0,	"VCVTSI2SDLrr", 0|(1<<TID::UnmodeledSideEffects), 0x52a000b05ULL, NULL, NULL, NULL, OperandInfo246 },  // Inst #2685 = VCVTSI2SDLrr
  { 2686,	7,	1,	0,	"VCVTSI2SDrm", 0|(1<<TID::UnmodeledSideEffects), 0x52a000b06ULL, NULL, NULL, NULL, OperandInfo226 },  // Inst #2686 = VCVTSI2SDrm
  { 2687,	3,	1,	0,	"VCVTSI2SDrr", 0|(1<<TID::UnmodeledSideEffects), 0x52a000b05ULL, NULL, NULL, NULL, OperandInfo246 },  // Inst #2687 = VCVTSI2SDrr
  { 2688,	7,	1,	0,	"VCVTSI2SS64rm", 0|(1<<TID::UnmodeledSideEffects), 0x72a000c06ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #2688 = VCVTSI2SS64rm
  { 2689,	3,	1,	0,	"VCVTSI2SS64rr", 0|(1<<TID::UnmodeledSideEffects), 0x72a000c05ULL, NULL, NULL, NULL, OperandInfo247 },  // Inst #2689 = VCVTSI2SS64rr
  { 2690,	7,	1,	0,	"VCVTSI2SSrm", 0|(1<<TID::UnmodeledSideEffects), 0x52a000c06ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #2690 = VCVTSI2SSrm
  { 2691,	3,	1,	0,	"VCVTSI2SSrr", 0|(1<<TID::UnmodeledSideEffects), 0x52a000c05ULL, NULL, NULL, NULL, OperandInfo248 },  // Inst #2691 = VCVTSI2SSrr
  { 2692,	7,	1,	0,	"VCVTSS2SDrm", 0|(1<<TID::UnmodeledSideEffects), 0x55a000c06ULL, NULL, NULL, NULL, OperandInfo249 },  // Inst #2692 = VCVTSS2SDrm
  { 2693,	3,	1,	0,	"VCVTSS2SDrr", 0|(1<<TID::UnmodeledSideEffects), 0x55a000c05ULL, NULL, NULL, NULL, OperandInfo250 },  // Inst #2693 = VCVTSS2SDrr
  { 2694,	6,	1,	0,	"VCVTSS2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0x32d000c06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #2694 = VCVTSS2SI64rm
  { 2695,	2,	1,	0,	"VCVTSS2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0x32d000c05ULL, NULL, NULL, NULL, OperandInfo100 },  // Inst #2695 = VCVTSS2SI64rr
  { 2696,	6,	1,	0,	"VCVTSS2SIrm", 0|(1<<TID::UnmodeledSideEffects), 0x12d000c06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #2696 = VCVTSS2SIrm
  { 2697,	2,	1,	0,	"VCVTSS2SIrr", 0|(1<<TID::UnmodeledSideEffects), 0x12d000c05ULL, NULL, NULL, NULL, OperandInfo101 },  // Inst #2697 = VCVTSS2SIrr
  { 2698,	2,	1,	0,	"VCVTTPD2DQXrYr", 0|(1<<TID::UnmodeledSideEffects), 0x1e6800045ULL, NULL, NULL, NULL, OperandInfo242 },  // Inst #2698 = VCVTTPD2DQXrYr
  { 2699,	6,	1,	0,	"VCVTTPD2DQXrm", 0|(1<<TID::UnmodeledSideEffects), 0x1e6800046ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2699 = VCVTTPD2DQXrm
  { 2700,	2,	1,	0,	"VCVTTPD2DQXrr", 0|(1<<TID::UnmodeledSideEffects), 0x1e6800045ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2700 = VCVTTPD2DQXrr
  { 2701,	6,	1,	0,	"VCVTTPD2DQYrm", 0|(1<<TID::UnmodeledSideEffects), 0x11e6800046ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2701 = VCVTTPD2DQYrm
  { 2702,	2,	1,	0,	"VCVTTPD2DQYrr", 0|(1<<TID::UnmodeledSideEffects), 0x1e6800045ULL, NULL, NULL, NULL, OperandInfo242 },  // Inst #2702 = VCVTTPD2DQYrr
  { 2703,	2,	1,	0,	"VCVTTPD2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0x1e6800045ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2703 = VCVTTPD2DQrr
  { 2704,	6,	1,	0,	"VCVTTPS2DQYrm", 0|(1<<TID::UnmodeledSideEffects), 0x15b000c06ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #2704 = VCVTTPS2DQYrm
  { 2705,	2,	1,	0,	"VCVTTPS2DQYrr", 0|(1<<TID::UnmodeledSideEffects), 0x15b000c05ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #2705 = VCVTTPS2DQYrr
  { 2706,	6,	1,	0,	"VCVTTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0x15b000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2706 = VCVTTPS2DQrm
  { 2707,	2,	1,	0,	"VCVTTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0x15b000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2707 = VCVTTPS2DQrr
  { 2708,	6,	1,	0,	"VCVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0x32c000b06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #2708 = VCVTTSD2SI64rm
  { 2709,	2,	1,	0,	"VCVTTSD2SI64rr", 0, 0x32c000b05ULL, NULL, NULL, NULL, OperandInfo102 },  // Inst #2709 = VCVTTSD2SI64rr
  { 2710,	6,	1,	0,	"VCVTTSD2SIrm", 0|(1<<TID::MayLoad), 0x12c000b06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #2710 = VCVTTSD2SIrm
  { 2711,	2,	1,	0,	"VCVTTSD2SIrr", 0, 0x12c000b05ULL, NULL, NULL, NULL, OperandInfo103 },  // Inst #2711 = VCVTTSD2SIrr
  { 2712,	6,	1,	0,	"VCVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0x32c000c06ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #2712 = VCVTTSS2SI64rm
  { 2713,	2,	1,	0,	"VCVTTSS2SI64rr", 0, 0x32c000c05ULL, NULL, NULL, NULL, OperandInfo100 },  // Inst #2713 = VCVTTSS2SI64rr
  { 2714,	6,	1,	0,	"VCVTTSS2SIrm", 0|(1<<TID::MayLoad), 0x12c000c06ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #2714 = VCVTTSS2SIrm
  { 2715,	2,	1,	0,	"VCVTTSS2SIrr", 0, 0x12c000c05ULL, NULL, NULL, NULL, OperandInfo101 },  // Inst #2715 = VCVTTSS2SIrr
  { 2716,	7,	1,	0,	"VDIVPDYrm", 0|(1<<TID::MayLoad), 0x55e800146ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2716 = VDIVPDYrm
  { 2717,	3,	1,	0,	"VDIVPDYrr", 0, 0x55e800145ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2717 = VDIVPDYrr
  { 2718,	7,	1,	0,	"VDIVPDrm", 0|(1<<TID::MayLoad), 0x55e800146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2718 = VDIVPDrm
  { 2719,	3,	1,	0,	"VDIVPDrr", 0, 0x55e800145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2719 = VDIVPDrr
  { 2720,	7,	1,	0,	"VDIVPSYrm", 0|(1<<TID::MayLoad), 0x55e400106ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2720 = VDIVPSYrm
  { 2721,	3,	1,	0,	"VDIVPSYrr", 0, 0x55e400105ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2721 = VDIVPSYrr
  { 2722,	7,	1,	0,	"VDIVPSrm", 0|(1<<TID::MayLoad), 0x55e400106ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2722 = VDIVPSrm
  { 2723,	3,	1,	0,	"VDIVPSrr", 0, 0x55e400105ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2723 = VDIVPSrr
  { 2724,	7,	1,	0,	"VDIVSDrm", 0|(1<<TID::MayLoad), 0x55e000b06ULL, NULL, NULL, NULL, OperandInfo226 },  // Inst #2724 = VDIVSDrm
  { 2725,	7,	1,	0,	"VDIVSDrm_Int", 0|(1<<TID::MayLoad), 0x55e000b06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2725 = VDIVSDrm_Int
  { 2726,	3,	1,	0,	"VDIVSDrr", 0, 0x55e000b05ULL, NULL, NULL, NULL, OperandInfo227 },  // Inst #2726 = VDIVSDrr
  { 2727,	3,	1,	0,	"VDIVSDrr_Int", 0, 0x55e000b05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2727 = VDIVSDrr_Int
  { 2728,	7,	1,	0,	"VDIVSSrm", 0|(1<<TID::MayLoad), 0x55e000c06ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #2728 = VDIVSSrm
  { 2729,	7,	1,	0,	"VDIVSSrm_Int", 0|(1<<TID::MayLoad), 0x55e000c06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2729 = VDIVSSrm_Int
  { 2730,	3,	1,	0,	"VDIVSSrr", 0, 0x55e000c05ULL, NULL, NULL, NULL, OperandInfo229 },  // Inst #2730 = VDIVSSrr
  { 2731,	3,	1,	0,	"VDIVSSrr_Int", 0, 0x55e000c05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2731 = VDIVSSrr_Int
  { 2732,	8,	1,	0,	"VDPPDrmi", 0|(1<<TID::MayLoad), 0x541c02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #2732 = VDPPDrmi
  { 2733,	4,	1,	0,	"VDPPDrri", 0|(1<<TID::Commutable), 0x541c02e45ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #2733 = VDPPDrri
  { 2734,	8,	1,	0,	"VDPPSYrmi", 0|(1<<TID::MayLoad), 0x540c02e46ULL, NULL, NULL, NULL, OperandInfo231 },  // Inst #2734 = VDPPSYrmi
  { 2735,	4,	1,	0,	"VDPPSYrri", 0|(1<<TID::Commutable), 0x540c02e45ULL, NULL, NULL, NULL, OperandInfo232 },  // Inst #2735 = VDPPSYrri
  { 2736,	8,	1,	0,	"VDPPSrmi", 0|(1<<TID::MayLoad), 0x540c02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #2736 = VDPPSrmi
  { 2737,	4,	1,	0,	"VDPPSrri", 0|(1<<TID::Commutable), 0x540c02e45ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #2737 = VDPPSrri
  { 2738,	5,	0,	0,	"VERRm", 0|(1<<TID::UnmodeledSideEffects), 0x11cULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2738 = VERRm
  { 2739,	1,	0,	0,	"VERRr", 0|(1<<TID::UnmodeledSideEffects), 0x114ULL, NULL, NULL, NULL, OperandInfo106 },  // Inst #2739 = VERRr
  { 2740,	5,	0,	0,	"VERWm", 0|(1<<TID::UnmodeledSideEffects), 0x11dULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2740 = VERWm
  { 2741,	1,	0,	0,	"VERWr", 0|(1<<TID::UnmodeledSideEffects), 0x115ULL, NULL, NULL, NULL, OperandInfo106 },  // Inst #2741 = VERWr
  { 2742,	7,	0,	0,	"VEXTRACTF128mr", 0|(1<<TID::UnmodeledSideEffects), 0x119c02e44ULL, NULL, NULL, NULL, OperandInfo251 },  // Inst #2742 = VEXTRACTF128mr
  { 2743,	3,	1,	0,	"VEXTRACTF128rr", 0|(1<<TID::UnmodeledSideEffects), 0x119c02e43ULL, NULL, NULL, NULL, OperandInfo252 },  // Inst #2743 = VEXTRACTF128rr
  { 2744,	7,	0,	0,	"VEXTRACTPSmr", 0|(1<<TID::MayStore), 0x117c02e44ULL, NULL, NULL, NULL, OperandInfo108 },  // Inst #2744 = VEXTRACTPSmr
  { 2745,	3,	1,	0,	"VEXTRACTPSrr", 0, 0x117c02e43ULL, NULL, NULL, NULL, OperandInfo109 },  // Inst #2745 = VEXTRACTPSrr
  { 2746,	3,	1,	0,	"VEXTRACTPSrr64", 0|(1<<TID::UnmodeledSideEffects), 0x117c02e43ULL, NULL, NULL, NULL, OperandInfo206 },  // Inst #2746 = VEXTRACTPSrr64
  { 2747,	7,	1,	0,	"VFMADDPDr132m", 0|(1<<TID::UnmodeledSideEffects), 0x798c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2747 = VFMADDPDr132m
  { 2748,	7,	1,	0,	"VFMADDPDr132mY", 0|(1<<TID::UnmodeledSideEffects), 0x798c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2748 = VFMADDPDr132mY
  { 2749,	3,	1,	0,	"VFMADDPDr132r", 0|(1<<TID::UnmodeledSideEffects), 0x798c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2749 = VFMADDPDr132r
  { 2750,	3,	1,	0,	"VFMADDPDr132rY", 0|(1<<TID::UnmodeledSideEffects), 0x798c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2750 = VFMADDPDr132rY
  { 2751,	7,	1,	0,	"VFMADDPDr213m", 0|(1<<TID::UnmodeledSideEffects), 0x7a8c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2751 = VFMADDPDr213m
  { 2752,	7,	1,	0,	"VFMADDPDr213mY", 0|(1<<TID::UnmodeledSideEffects), 0x7a8c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2752 = VFMADDPDr213mY
  { 2753,	3,	1,	0,	"VFMADDPDr213r", 0|(1<<TID::UnmodeledSideEffects), 0x7a8c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2753 = VFMADDPDr213r
  { 2754,	3,	1,	0,	"VFMADDPDr213rY", 0|(1<<TID::UnmodeledSideEffects), 0x7a8c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2754 = VFMADDPDr213rY
  { 2755,	7,	1,	0,	"VFMADDPDr231m", 0|(1<<TID::UnmodeledSideEffects), 0x7b8c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2755 = VFMADDPDr231m
  { 2756,	7,	1,	0,	"VFMADDPDr231mY", 0|(1<<TID::UnmodeledSideEffects), 0x7b8c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2756 = VFMADDPDr231mY
  { 2757,	3,	1,	0,	"VFMADDPDr231r", 0|(1<<TID::UnmodeledSideEffects), 0x7b8c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2757 = VFMADDPDr231r
  { 2758,	3,	1,	0,	"VFMADDPDr231rY", 0|(1<<TID::UnmodeledSideEffects), 0x7b8c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2758 = VFMADDPDr231rY
  { 2759,	7,	1,	0,	"VFMADDPSr132m", 0|(1<<TID::UnmodeledSideEffects), 0x598c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2759 = VFMADDPSr132m
  { 2760,	7,	1,	0,	"VFMADDPSr132mY", 0|(1<<TID::UnmodeledSideEffects), 0x598c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2760 = VFMADDPSr132mY
  { 2761,	3,	1,	0,	"VFMADDPSr132r", 0|(1<<TID::UnmodeledSideEffects), 0x598c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2761 = VFMADDPSr132r
  { 2762,	3,	1,	0,	"VFMADDPSr132rY", 0|(1<<TID::UnmodeledSideEffects), 0x598c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2762 = VFMADDPSr132rY
  { 2763,	7,	1,	0,	"VFMADDPSr213m", 0|(1<<TID::UnmodeledSideEffects), 0x5a8c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2763 = VFMADDPSr213m
  { 2764,	7,	1,	0,	"VFMADDPSr213mY", 0|(1<<TID::UnmodeledSideEffects), 0x5a8c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2764 = VFMADDPSr213mY
  { 2765,	3,	1,	0,	"VFMADDPSr213r", 0|(1<<TID::UnmodeledSideEffects), 0x5a8c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2765 = VFMADDPSr213r
  { 2766,	3,	1,	0,	"VFMADDPSr213rY", 0|(1<<TID::UnmodeledSideEffects), 0x5a8c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2766 = VFMADDPSr213rY
  { 2767,	7,	1,	0,	"VFMADDPSr231m", 0|(1<<TID::UnmodeledSideEffects), 0x5b8c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2767 = VFMADDPSr231m
  { 2768,	7,	1,	0,	"VFMADDPSr231mY", 0|(1<<TID::UnmodeledSideEffects), 0x5b8c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2768 = VFMADDPSr231mY
  { 2769,	3,	1,	0,	"VFMADDPSr231r", 0|(1<<TID::UnmodeledSideEffects), 0x5b8c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2769 = VFMADDPSr231r
  { 2770,	3,	1,	0,	"VFMADDPSr231rY", 0|(1<<TID::UnmodeledSideEffects), 0x5b8c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2770 = VFMADDPSr231rY
  { 2771,	7,	1,	0,	"VFMADDSUBPDr132m", 0|(1<<TID::UnmodeledSideEffects), 0x796c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2771 = VFMADDSUBPDr132m
  { 2772,	7,	1,	0,	"VFMADDSUBPDr132mY", 0|(1<<TID::UnmodeledSideEffects), 0x796c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2772 = VFMADDSUBPDr132mY
  { 2773,	3,	1,	0,	"VFMADDSUBPDr132r", 0|(1<<TID::UnmodeledSideEffects), 0x796c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2773 = VFMADDSUBPDr132r
  { 2774,	3,	1,	0,	"VFMADDSUBPDr132rY", 0|(1<<TID::UnmodeledSideEffects), 0x796c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2774 = VFMADDSUBPDr132rY
  { 2775,	7,	1,	0,	"VFMADDSUBPDr213m", 0|(1<<TID::UnmodeledSideEffects), 0x7a6c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2775 = VFMADDSUBPDr213m
  { 2776,	7,	1,	0,	"VFMADDSUBPDr213mY", 0|(1<<TID::UnmodeledSideEffects), 0x7a6c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2776 = VFMADDSUBPDr213mY
  { 2777,	3,	1,	0,	"VFMADDSUBPDr213r", 0|(1<<TID::UnmodeledSideEffects), 0x7a6c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2777 = VFMADDSUBPDr213r
  { 2778,	3,	1,	0,	"VFMADDSUBPDr213rY", 0|(1<<TID::UnmodeledSideEffects), 0x7a6c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2778 = VFMADDSUBPDr213rY
  { 2779,	7,	1,	0,	"VFMADDSUBPDr231m", 0|(1<<TID::UnmodeledSideEffects), 0x7b6c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2779 = VFMADDSUBPDr231m
  { 2780,	7,	1,	0,	"VFMADDSUBPDr231mY", 0|(1<<TID::UnmodeledSideEffects), 0x7b6c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2780 = VFMADDSUBPDr231mY
  { 2781,	3,	1,	0,	"VFMADDSUBPDr231r", 0|(1<<TID::UnmodeledSideEffects), 0x7b6c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2781 = VFMADDSUBPDr231r
  { 2782,	3,	1,	0,	"VFMADDSUBPDr231rY", 0|(1<<TID::UnmodeledSideEffects), 0x7b6c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2782 = VFMADDSUBPDr231rY
  { 2783,	7,	1,	0,	"VFMADDSUBPSr132m", 0|(1<<TID::UnmodeledSideEffects), 0x596c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2783 = VFMADDSUBPSr132m
  { 2784,	7,	1,	0,	"VFMADDSUBPSr132mY", 0|(1<<TID::UnmodeledSideEffects), 0x596c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2784 = VFMADDSUBPSr132mY
  { 2785,	3,	1,	0,	"VFMADDSUBPSr132r", 0|(1<<TID::UnmodeledSideEffects), 0x596c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2785 = VFMADDSUBPSr132r
  { 2786,	3,	1,	0,	"VFMADDSUBPSr132rY", 0|(1<<TID::UnmodeledSideEffects), 0x596c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2786 = VFMADDSUBPSr132rY
  { 2787,	7,	1,	0,	"VFMADDSUBPSr213m", 0|(1<<TID::UnmodeledSideEffects), 0x5a6c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2787 = VFMADDSUBPSr213m
  { 2788,	7,	1,	0,	"VFMADDSUBPSr213mY", 0|(1<<TID::UnmodeledSideEffects), 0x5a6c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2788 = VFMADDSUBPSr213mY
  { 2789,	3,	1,	0,	"VFMADDSUBPSr213r", 0|(1<<TID::UnmodeledSideEffects), 0x5a6c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2789 = VFMADDSUBPSr213r
  { 2790,	3,	1,	0,	"VFMADDSUBPSr213rY", 0|(1<<TID::UnmodeledSideEffects), 0x5a6c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2790 = VFMADDSUBPSr213rY
  { 2791,	7,	1,	0,	"VFMADDSUBPSr231m", 0|(1<<TID::UnmodeledSideEffects), 0x5b6c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2791 = VFMADDSUBPSr231m
  { 2792,	7,	1,	0,	"VFMADDSUBPSr231mY", 0|(1<<TID::UnmodeledSideEffects), 0x5b6c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2792 = VFMADDSUBPSr231mY
  { 2793,	3,	1,	0,	"VFMADDSUBPSr231r", 0|(1<<TID::UnmodeledSideEffects), 0x5b6c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2793 = VFMADDSUBPSr231r
  { 2794,	3,	1,	0,	"VFMADDSUBPSr231rY", 0|(1<<TID::UnmodeledSideEffects), 0x5b6c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2794 = VFMADDSUBPSr231rY
  { 2795,	7,	1,	0,	"VFMSUBADDPDr132m", 0|(1<<TID::UnmodeledSideEffects), 0x797c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2795 = VFMSUBADDPDr132m
  { 2796,	7,	1,	0,	"VFMSUBADDPDr132mY", 0|(1<<TID::UnmodeledSideEffects), 0x797c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2796 = VFMSUBADDPDr132mY
  { 2797,	3,	1,	0,	"VFMSUBADDPDr132r", 0|(1<<TID::UnmodeledSideEffects), 0x797c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2797 = VFMSUBADDPDr132r
  { 2798,	3,	1,	0,	"VFMSUBADDPDr132rY", 0|(1<<TID::UnmodeledSideEffects), 0x797c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2798 = VFMSUBADDPDr132rY
  { 2799,	7,	1,	0,	"VFMSUBADDPDr213m", 0|(1<<TID::UnmodeledSideEffects), 0x7a7c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2799 = VFMSUBADDPDr213m
  { 2800,	7,	1,	0,	"VFMSUBADDPDr213mY", 0|(1<<TID::UnmodeledSideEffects), 0x7a7c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2800 = VFMSUBADDPDr213mY
  { 2801,	3,	1,	0,	"VFMSUBADDPDr213r", 0|(1<<TID::UnmodeledSideEffects), 0x7a7c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2801 = VFMSUBADDPDr213r
  { 2802,	3,	1,	0,	"VFMSUBADDPDr213rY", 0|(1<<TID::UnmodeledSideEffects), 0x7a7c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2802 = VFMSUBADDPDr213rY
  { 2803,	7,	1,	0,	"VFMSUBADDPDr231m", 0|(1<<TID::UnmodeledSideEffects), 0x7b7c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2803 = VFMSUBADDPDr231m
  { 2804,	7,	1,	0,	"VFMSUBADDPDr231mY", 0|(1<<TID::UnmodeledSideEffects), 0x7b7c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2804 = VFMSUBADDPDr231mY
  { 2805,	3,	1,	0,	"VFMSUBADDPDr231r", 0|(1<<TID::UnmodeledSideEffects), 0x7b7c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2805 = VFMSUBADDPDr231r
  { 2806,	3,	1,	0,	"VFMSUBADDPDr231rY", 0|(1<<TID::UnmodeledSideEffects), 0x7b7c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2806 = VFMSUBADDPDr231rY
  { 2807,	7,	1,	0,	"VFMSUBADDPSr132m", 0|(1<<TID::UnmodeledSideEffects), 0x597c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2807 = VFMSUBADDPSr132m
  { 2808,	7,	1,	0,	"VFMSUBADDPSr132mY", 0|(1<<TID::UnmodeledSideEffects), 0x597c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2808 = VFMSUBADDPSr132mY
  { 2809,	3,	1,	0,	"VFMSUBADDPSr132r", 0|(1<<TID::UnmodeledSideEffects), 0x597c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2809 = VFMSUBADDPSr132r
  { 2810,	3,	1,	0,	"VFMSUBADDPSr132rY", 0|(1<<TID::UnmodeledSideEffects), 0x597c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2810 = VFMSUBADDPSr132rY
  { 2811,	7,	1,	0,	"VFMSUBADDPSr213m", 0|(1<<TID::UnmodeledSideEffects), 0x5a7c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2811 = VFMSUBADDPSr213m
  { 2812,	7,	1,	0,	"VFMSUBADDPSr213mY", 0|(1<<TID::UnmodeledSideEffects), 0x5a7c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2812 = VFMSUBADDPSr213mY
  { 2813,	3,	1,	0,	"VFMSUBADDPSr213r", 0|(1<<TID::UnmodeledSideEffects), 0x5a7c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2813 = VFMSUBADDPSr213r
  { 2814,	3,	1,	0,	"VFMSUBADDPSr213rY", 0|(1<<TID::UnmodeledSideEffects), 0x5a7c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2814 = VFMSUBADDPSr213rY
  { 2815,	7,	1,	0,	"VFMSUBADDPSr231m", 0|(1<<TID::UnmodeledSideEffects), 0x5b7c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2815 = VFMSUBADDPSr231m
  { 2816,	7,	1,	0,	"VFMSUBADDPSr231mY", 0|(1<<TID::UnmodeledSideEffects), 0x5b7c00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2816 = VFMSUBADDPSr231mY
  { 2817,	3,	1,	0,	"VFMSUBADDPSr231r", 0|(1<<TID::UnmodeledSideEffects), 0x5b7c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2817 = VFMSUBADDPSr231r
  { 2818,	3,	1,	0,	"VFMSUBADDPSr231rY", 0|(1<<TID::UnmodeledSideEffects), 0x5b7c00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2818 = VFMSUBADDPSr231rY
  { 2819,	7,	1,	0,	"VFMSUBPDr132m", 0|(1<<TID::UnmodeledSideEffects), 0x79ac00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2819 = VFMSUBPDr132m
  { 2820,	7,	1,	0,	"VFMSUBPDr132mY", 0|(1<<TID::UnmodeledSideEffects), 0x79ac00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2820 = VFMSUBPDr132mY
  { 2821,	3,	1,	0,	"VFMSUBPDr132r", 0|(1<<TID::UnmodeledSideEffects), 0x79ac00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2821 = VFMSUBPDr132r
  { 2822,	3,	1,	0,	"VFMSUBPDr132rY", 0|(1<<TID::UnmodeledSideEffects), 0x79ac00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2822 = VFMSUBPDr132rY
  { 2823,	7,	1,	0,	"VFMSUBPDr213m", 0|(1<<TID::UnmodeledSideEffects), 0x7aac00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2823 = VFMSUBPDr213m
  { 2824,	7,	1,	0,	"VFMSUBPDr213mY", 0|(1<<TID::UnmodeledSideEffects), 0x7aac00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2824 = VFMSUBPDr213mY
  { 2825,	3,	1,	0,	"VFMSUBPDr213r", 0|(1<<TID::UnmodeledSideEffects), 0x7aac00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2825 = VFMSUBPDr213r
  { 2826,	3,	1,	0,	"VFMSUBPDr213rY", 0|(1<<TID::UnmodeledSideEffects), 0x7aac00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2826 = VFMSUBPDr213rY
  { 2827,	7,	1,	0,	"VFMSUBPDr231m", 0|(1<<TID::UnmodeledSideEffects), 0x7bac00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2827 = VFMSUBPDr231m
  { 2828,	7,	1,	0,	"VFMSUBPDr231mY", 0|(1<<TID::UnmodeledSideEffects), 0x7bac00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2828 = VFMSUBPDr231mY
  { 2829,	3,	1,	0,	"VFMSUBPDr231r", 0|(1<<TID::UnmodeledSideEffects), 0x7bac00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2829 = VFMSUBPDr231r
  { 2830,	3,	1,	0,	"VFMSUBPDr231rY", 0|(1<<TID::UnmodeledSideEffects), 0x7bac00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2830 = VFMSUBPDr231rY
  { 2831,	7,	1,	0,	"VFMSUBPSr132m", 0|(1<<TID::UnmodeledSideEffects), 0x59ac00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2831 = VFMSUBPSr132m
  { 2832,	7,	1,	0,	"VFMSUBPSr132mY", 0|(1<<TID::UnmodeledSideEffects), 0x59ac00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2832 = VFMSUBPSr132mY
  { 2833,	3,	1,	0,	"VFMSUBPSr132r", 0|(1<<TID::UnmodeledSideEffects), 0x59ac00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2833 = VFMSUBPSr132r
  { 2834,	3,	1,	0,	"VFMSUBPSr132rY", 0|(1<<TID::UnmodeledSideEffects), 0x59ac00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2834 = VFMSUBPSr132rY
  { 2835,	7,	1,	0,	"VFMSUBPSr213m", 0|(1<<TID::UnmodeledSideEffects), 0x5aac00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2835 = VFMSUBPSr213m
  { 2836,	7,	1,	0,	"VFMSUBPSr213mY", 0|(1<<TID::UnmodeledSideEffects), 0x5aac00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2836 = VFMSUBPSr213mY
  { 2837,	3,	1,	0,	"VFMSUBPSr213r", 0|(1<<TID::UnmodeledSideEffects), 0x5aac00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2837 = VFMSUBPSr213r
  { 2838,	3,	1,	0,	"VFMSUBPSr213rY", 0|(1<<TID::UnmodeledSideEffects), 0x5aac00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2838 = VFMSUBPSr213rY
  { 2839,	7,	1,	0,	"VFMSUBPSr231m", 0|(1<<TID::UnmodeledSideEffects), 0x5bac00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2839 = VFMSUBPSr231m
  { 2840,	7,	1,	0,	"VFMSUBPSr231mY", 0|(1<<TID::UnmodeledSideEffects), 0x5bac00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2840 = VFMSUBPSr231mY
  { 2841,	3,	1,	0,	"VFMSUBPSr231r", 0|(1<<TID::UnmodeledSideEffects), 0x5bac00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2841 = VFMSUBPSr231r
  { 2842,	3,	1,	0,	"VFMSUBPSr231rY", 0|(1<<TID::UnmodeledSideEffects), 0x5bac00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2842 = VFMSUBPSr231rY
  { 2843,	7,	1,	0,	"VFNMADDPDr132m", 0|(1<<TID::UnmodeledSideEffects), 0x79cc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2843 = VFNMADDPDr132m
  { 2844,	7,	1,	0,	"VFNMADDPDr132mY", 0|(1<<TID::UnmodeledSideEffects), 0x79cc00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2844 = VFNMADDPDr132mY
  { 2845,	3,	1,	0,	"VFNMADDPDr132r", 0|(1<<TID::UnmodeledSideEffects), 0x79cc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2845 = VFNMADDPDr132r
  { 2846,	3,	1,	0,	"VFNMADDPDr132rY", 0|(1<<TID::UnmodeledSideEffects), 0x79cc00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2846 = VFNMADDPDr132rY
  { 2847,	7,	1,	0,	"VFNMADDPDr213m", 0|(1<<TID::UnmodeledSideEffects), 0x7acc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2847 = VFNMADDPDr213m
  { 2848,	7,	1,	0,	"VFNMADDPDr213mY", 0|(1<<TID::UnmodeledSideEffects), 0x7acc00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2848 = VFNMADDPDr213mY
  { 2849,	3,	1,	0,	"VFNMADDPDr213r", 0|(1<<TID::UnmodeledSideEffects), 0x7acc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2849 = VFNMADDPDr213r
  { 2850,	3,	1,	0,	"VFNMADDPDr213rY", 0|(1<<TID::UnmodeledSideEffects), 0x7acc00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2850 = VFNMADDPDr213rY
  { 2851,	7,	1,	0,	"VFNMADDPDr231m", 0|(1<<TID::UnmodeledSideEffects), 0x7bcc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2851 = VFNMADDPDr231m
  { 2852,	7,	1,	0,	"VFNMADDPDr231mY", 0|(1<<TID::UnmodeledSideEffects), 0x7bcc00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2852 = VFNMADDPDr231mY
  { 2853,	3,	1,	0,	"VFNMADDPDr231r", 0|(1<<TID::UnmodeledSideEffects), 0x7bcc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2853 = VFNMADDPDr231r
  { 2854,	3,	1,	0,	"VFNMADDPDr231rY", 0|(1<<TID::UnmodeledSideEffects), 0x7bcc00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2854 = VFNMADDPDr231rY
  { 2855,	7,	1,	0,	"VFNMADDPSr132m", 0|(1<<TID::UnmodeledSideEffects), 0x59cc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2855 = VFNMADDPSr132m
  { 2856,	7,	1,	0,	"VFNMADDPSr132mY", 0|(1<<TID::UnmodeledSideEffects), 0x59cc00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2856 = VFNMADDPSr132mY
  { 2857,	3,	1,	0,	"VFNMADDPSr132r", 0|(1<<TID::UnmodeledSideEffects), 0x59cc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2857 = VFNMADDPSr132r
  { 2858,	3,	1,	0,	"VFNMADDPSr132rY", 0|(1<<TID::UnmodeledSideEffects), 0x59cc00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2858 = VFNMADDPSr132rY
  { 2859,	7,	1,	0,	"VFNMADDPSr213m", 0|(1<<TID::UnmodeledSideEffects), 0x5acc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2859 = VFNMADDPSr213m
  { 2860,	7,	1,	0,	"VFNMADDPSr213mY", 0|(1<<TID::UnmodeledSideEffects), 0x5acc00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2860 = VFNMADDPSr213mY
  { 2861,	3,	1,	0,	"VFNMADDPSr213r", 0|(1<<TID::UnmodeledSideEffects), 0x5acc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2861 = VFNMADDPSr213r
  { 2862,	3,	1,	0,	"VFNMADDPSr213rY", 0|(1<<TID::UnmodeledSideEffects), 0x5acc00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2862 = VFNMADDPSr213rY
  { 2863,	7,	1,	0,	"VFNMADDPSr231m", 0|(1<<TID::UnmodeledSideEffects), 0x5bcc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2863 = VFNMADDPSr231m
  { 2864,	7,	1,	0,	"VFNMADDPSr231mY", 0|(1<<TID::UnmodeledSideEffects), 0x5bcc00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2864 = VFNMADDPSr231mY
  { 2865,	3,	1,	0,	"VFNMADDPSr231r", 0|(1<<TID::UnmodeledSideEffects), 0x5bcc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2865 = VFNMADDPSr231r
  { 2866,	3,	1,	0,	"VFNMADDPSr231rY", 0|(1<<TID::UnmodeledSideEffects), 0x5bcc00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2866 = VFNMADDPSr231rY
  { 2867,	7,	1,	0,	"VFNMSUBPDr132m", 0|(1<<TID::UnmodeledSideEffects), 0x79ec00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2867 = VFNMSUBPDr132m
  { 2868,	7,	1,	0,	"VFNMSUBPDr132mY", 0|(1<<TID::UnmodeledSideEffects), 0x79ec00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2868 = VFNMSUBPDr132mY
  { 2869,	3,	1,	0,	"VFNMSUBPDr132r", 0|(1<<TID::UnmodeledSideEffects), 0x79ec00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2869 = VFNMSUBPDr132r
  { 2870,	3,	1,	0,	"VFNMSUBPDr132rY", 0|(1<<TID::UnmodeledSideEffects), 0x79ec00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2870 = VFNMSUBPDr132rY
  { 2871,	7,	1,	0,	"VFNMSUBPDr213m", 0|(1<<TID::UnmodeledSideEffects), 0x7aec00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2871 = VFNMSUBPDr213m
  { 2872,	7,	1,	0,	"VFNMSUBPDr213mY", 0|(1<<TID::UnmodeledSideEffects), 0x7aec00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2872 = VFNMSUBPDr213mY
  { 2873,	3,	1,	0,	"VFNMSUBPDr213r", 0|(1<<TID::UnmodeledSideEffects), 0x7aec00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2873 = VFNMSUBPDr213r
  { 2874,	3,	1,	0,	"VFNMSUBPDr213rY", 0|(1<<TID::UnmodeledSideEffects), 0x7aec00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2874 = VFNMSUBPDr213rY
  { 2875,	7,	1,	0,	"VFNMSUBPDr231m", 0|(1<<TID::UnmodeledSideEffects), 0x7bec00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2875 = VFNMSUBPDr231m
  { 2876,	7,	1,	0,	"VFNMSUBPDr231mY", 0|(1<<TID::UnmodeledSideEffects), 0x7bec00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2876 = VFNMSUBPDr231mY
  { 2877,	3,	1,	0,	"VFNMSUBPDr231r", 0|(1<<TID::UnmodeledSideEffects), 0x7bec00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2877 = VFNMSUBPDr231r
  { 2878,	3,	1,	0,	"VFNMSUBPDr231rY", 0|(1<<TID::UnmodeledSideEffects), 0x7bec00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2878 = VFNMSUBPDr231rY
  { 2879,	7,	1,	0,	"VFNMSUBPSr132m", 0|(1<<TID::UnmodeledSideEffects), 0x59ec00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2879 = VFNMSUBPSr132m
  { 2880,	7,	1,	0,	"VFNMSUBPSr132mY", 0|(1<<TID::UnmodeledSideEffects), 0x59ec00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2880 = VFNMSUBPSr132mY
  { 2881,	3,	1,	0,	"VFNMSUBPSr132r", 0|(1<<TID::UnmodeledSideEffects), 0x59ec00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2881 = VFNMSUBPSr132r
  { 2882,	3,	1,	0,	"VFNMSUBPSr132rY", 0|(1<<TID::UnmodeledSideEffects), 0x59ec00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2882 = VFNMSUBPSr132rY
  { 2883,	7,	1,	0,	"VFNMSUBPSr213m", 0|(1<<TID::UnmodeledSideEffects), 0x5aec00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2883 = VFNMSUBPSr213m
  { 2884,	7,	1,	0,	"VFNMSUBPSr213mY", 0|(1<<TID::UnmodeledSideEffects), 0x5aec00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2884 = VFNMSUBPSr213mY
  { 2885,	3,	1,	0,	"VFNMSUBPSr213r", 0|(1<<TID::UnmodeledSideEffects), 0x5aec00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2885 = VFNMSUBPSr213r
  { 2886,	3,	1,	0,	"VFNMSUBPSr213rY", 0|(1<<TID::UnmodeledSideEffects), 0x5aec00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2886 = VFNMSUBPSr213rY
  { 2887,	7,	1,	0,	"VFNMSUBPSr231m", 0|(1<<TID::UnmodeledSideEffects), 0x5bec00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2887 = VFNMSUBPSr231m
  { 2888,	7,	1,	0,	"VFNMSUBPSr231mY", 0|(1<<TID::UnmodeledSideEffects), 0x5bec00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2888 = VFNMSUBPSr231mY
  { 2889,	3,	1,	0,	"VFNMSUBPSr231r", 0|(1<<TID::UnmodeledSideEffects), 0x5bec00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2889 = VFNMSUBPSr231r
  { 2890,	3,	1,	0,	"VFNMSUBPSr231rY", 0|(1<<TID::UnmodeledSideEffects), 0x5bec00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2890 = VFNMSUBPSr231rY
  { 2891,	7,	1,	0,	"VFsANDNPDrm", 0|(1<<TID::MayLoad), 0x555800046ULL, NULL, NULL, NULL, OperandInfo226 },  // Inst #2891 = VFsANDNPDrm
  { 2892,	3,	1,	0,	"VFsANDNPDrr", 0, 0x555800045ULL, NULL, NULL, NULL, OperandInfo227 },  // Inst #2892 = VFsANDNPDrr
  { 2893,	7,	1,	0,	"VFsANDNPSrm", 0|(1<<TID::MayLoad), 0x555400006ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #2893 = VFsANDNPSrm
  { 2894,	3,	1,	0,	"VFsANDNPSrr", 0, 0x555400005ULL, NULL, NULL, NULL, OperandInfo229 },  // Inst #2894 = VFsANDNPSrr
  { 2895,	7,	1,	0,	"VFsANDPDrm", 0|(1<<TID::MayLoad), 0x554800046ULL, NULL, NULL, NULL, OperandInfo226 },  // Inst #2895 = VFsANDPDrm
  { 2896,	3,	1,	0,	"VFsANDPDrr", 0|(1<<TID::Commutable), 0x554800045ULL, NULL, NULL, NULL, OperandInfo227 },  // Inst #2896 = VFsANDPDrr
  { 2897,	7,	1,	0,	"VFsANDPSrm", 0|(1<<TID::MayLoad), 0x554400006ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #2897 = VFsANDPSrm
  { 2898,	3,	1,	0,	"VFsANDPSrr", 0|(1<<TID::Commutable), 0x554400005ULL, NULL, NULL, NULL, OperandInfo229 },  // Inst #2898 = VFsANDPSrr
  { 2899,	7,	1,	0,	"VFsORPDrm", 0|(1<<TID::MayLoad), 0x556800046ULL, NULL, NULL, NULL, OperandInfo226 },  // Inst #2899 = VFsORPDrm
  { 2900,	3,	1,	0,	"VFsORPDrr", 0|(1<<TID::Commutable), 0x556800045ULL, NULL, NULL, NULL, OperandInfo227 },  // Inst #2900 = VFsORPDrr
  { 2901,	7,	1,	0,	"VFsORPSrm", 0|(1<<TID::MayLoad), 0x556400006ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #2901 = VFsORPSrm
  { 2902,	3,	1,	0,	"VFsORPSrr", 0|(1<<TID::Commutable), 0x556400005ULL, NULL, NULL, NULL, OperandInfo229 },  // Inst #2902 = VFsORPSrr
  { 2903,	7,	1,	0,	"VFsXORPDrm", 0|(1<<TID::MayLoad), 0x557800046ULL, NULL, NULL, NULL, OperandInfo226 },  // Inst #2903 = VFsXORPDrm
  { 2904,	3,	1,	0,	"VFsXORPDrr", 0|(1<<TID::Commutable), 0x557800045ULL, NULL, NULL, NULL, OperandInfo227 },  // Inst #2904 = VFsXORPDrr
  { 2905,	7,	1,	0,	"VFsXORPSrm", 0|(1<<TID::MayLoad), 0x557400006ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #2905 = VFsXORPSrm
  { 2906,	3,	1,	0,	"VFsXORPSrr", 0|(1<<TID::Commutable), 0x557400005ULL, NULL, NULL, NULL, OperandInfo229 },  // Inst #2906 = VFsXORPSrr
  { 2907,	7,	1,	0,	"VHADDPDYrm", 0|(1<<TID::MayLoad), 0x57c800146ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2907 = VHADDPDYrm
  { 2908,	3,	1,	0,	"VHADDPDYrr", 0, 0x57c800145ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2908 = VHADDPDYrr
  { 2909,	7,	1,	0,	"VHADDPDrm", 0|(1<<TID::MayLoad), 0x57c800146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2909 = VHADDPDrm
  { 2910,	3,	1,	0,	"VHADDPDrr", 0, 0x57c800145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2910 = VHADDPDrr
  { 2911,	7,	1,	0,	"VHADDPSYrm", 0|(1<<TID::MayLoad), 0x57c800b06ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2911 = VHADDPSYrm
  { 2912,	3,	1,	0,	"VHADDPSYrr", 0, 0x57c800b05ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2912 = VHADDPSYrr
  { 2913,	7,	1,	0,	"VHADDPSrm", 0|(1<<TID::MayLoad), 0x57c800b06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2913 = VHADDPSrm
  { 2914,	3,	1,	0,	"VHADDPSrr", 0, 0x57c800b05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2914 = VHADDPSrr
  { 2915,	7,	1,	0,	"VHSUBPDYrm", 0|(1<<TID::MayLoad), 0x57d800146ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2915 = VHSUBPDYrm
  { 2916,	3,	1,	0,	"VHSUBPDYrr", 0, 0x57d800145ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2916 = VHSUBPDYrr
  { 2917,	7,	1,	0,	"VHSUBPDrm", 0|(1<<TID::MayLoad), 0x57d800146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2917 = VHSUBPDrm
  { 2918,	3,	1,	0,	"VHSUBPDrr", 0, 0x57d800145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2918 = VHSUBPDrr
  { 2919,	7,	1,	0,	"VHSUBPSYrm", 0|(1<<TID::MayLoad), 0x57d800b06ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2919 = VHSUBPSYrm
  { 2920,	3,	1,	0,	"VHSUBPSYrr", 0, 0x57d800b05ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2920 = VHSUBPSYrr
  { 2921,	7,	1,	0,	"VHSUBPSrm", 0|(1<<TID::MayLoad), 0x57d800b06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2921 = VHSUBPSrm
  { 2922,	3,	1,	0,	"VHSUBPSrr", 0, 0x57d800b05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2922 = VHSUBPSrr
  { 2923,	8,	1,	0,	"VINSERTF128rm", 0|(1<<TID::UnmodeledSideEffects), 0x518c02e46ULL, NULL, NULL, NULL, OperandInfo231 },  // Inst #2923 = VINSERTF128rm
  { 2924,	4,	1,	0,	"VINSERTF128rr", 0|(1<<TID::UnmodeledSideEffects), 0x518c02e45ULL, NULL, NULL, NULL, OperandInfo253 },  // Inst #2924 = VINSERTF128rr
  { 2925,	8,	1,	0,	"VINSERTPSrm", 0|(1<<TID::MayLoad), 0x521c02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #2925 = VINSERTPSrm
  { 2926,	4,	1,	0,	"VINSERTPSrr", 0, 0x521c02e45ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #2926 = VINSERTPSrr
  { 2927,	6,	1,	0,	"VLDDQUYrm", 0|(1<<TID::MayLoad), 0x1f0800b06ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #2927 = VLDDQUYrm
  { 2928,	6,	1,	0,	"VLDDQUrm", 0|(1<<TID::MayLoad), 0x1f0800b06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2928 = VLDDQUrm
  { 2929,	5,	0,	0,	"VLDMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x1ae40001aULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2929 = VLDMXCSR
  { 2930,	2,	0,	0,	"VMASKMOVDQU", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x1f7c00045ULL, ImplicitList34, NULL, NULL, OperandInfo43 },  // Inst #2930 = VMASKMOVDQU
  { 2931,	2,	0,	0,	"VMASKMOVDQU64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x1f7c00045ULL, ImplicitList35, NULL, NULL, OperandInfo43 },  // Inst #2931 = VMASKMOVDQU64
  { 2932,	7,	0,	0,	"VMASKMOVPDYmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x52fc00d44ULL, NULL, NULL, NULL, OperandInfo254 },  // Inst #2932 = VMASKMOVPDYmr
  { 2933,	7,	1,	0,	"VMASKMOVPDYrm", 0|(1<<TID::MayLoad), 0x52dc00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2933 = VMASKMOVPDYrm
  { 2934,	7,	0,	0,	"VMASKMOVPDmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x52fc00d44ULL, NULL, NULL, NULL, OperandInfo255 },  // Inst #2934 = VMASKMOVPDmr
  { 2935,	7,	1,	0,	"VMASKMOVPDrm", 0|(1<<TID::MayLoad), 0x52dc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2935 = VMASKMOVPDrm
  { 2936,	7,	0,	0,	"VMASKMOVPSYmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x52ec00d44ULL, NULL, NULL, NULL, OperandInfo254 },  // Inst #2936 = VMASKMOVPSYmr
  { 2937,	7,	1,	0,	"VMASKMOVPSYrm", 0|(1<<TID::MayLoad), 0x52cc00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2937 = VMASKMOVPSYrm
  { 2938,	7,	0,	0,	"VMASKMOVPSmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x52ec00d44ULL, NULL, NULL, NULL, OperandInfo255 },  // Inst #2938 = VMASKMOVPSmr
  { 2939,	7,	1,	0,	"VMASKMOVPSrm", 0|(1<<TID::MayLoad), 0x52cc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2939 = VMASKMOVPSrm
  { 2940,	7,	1,	0,	"VMAXPDYrm", 0|(1<<TID::MayLoad), 0x55f800146ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2940 = VMAXPDYrm
  { 2941,	7,	1,	0,	"VMAXPDYrm_Int", 0|(1<<TID::MayLoad), 0x55f800146ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2941 = VMAXPDYrm_Int
  { 2942,	3,	1,	0,	"VMAXPDYrr", 0, 0x55f800145ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2942 = VMAXPDYrr
  { 2943,	3,	1,	0,	"VMAXPDYrr_Int", 0, 0x55f800145ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2943 = VMAXPDYrr_Int
  { 2944,	7,	1,	0,	"VMAXPDrm", 0|(1<<TID::MayLoad), 0x55f800146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2944 = VMAXPDrm
  { 2945,	7,	1,	0,	"VMAXPDrm_Int", 0|(1<<TID::MayLoad), 0x55f800146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2945 = VMAXPDrm_Int
  { 2946,	3,	1,	0,	"VMAXPDrr", 0, 0x55f800145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2946 = VMAXPDrr
  { 2947,	3,	1,	0,	"VMAXPDrr_Int", 0, 0x55f800145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2947 = VMAXPDrr_Int
  { 2948,	7,	1,	0,	"VMAXPSYrm", 0|(1<<TID::MayLoad), 0x55f400106ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2948 = VMAXPSYrm
  { 2949,	7,	1,	0,	"VMAXPSYrm_Int", 0|(1<<TID::MayLoad), 0x55f400106ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2949 = VMAXPSYrm_Int
  { 2950,	3,	1,	0,	"VMAXPSYrr", 0, 0x55f400105ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2950 = VMAXPSYrr
  { 2951,	3,	1,	0,	"VMAXPSYrr_Int", 0, 0x55f400105ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2951 = VMAXPSYrr_Int
  { 2952,	7,	1,	0,	"VMAXPSrm", 0|(1<<TID::MayLoad), 0x55f400106ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2952 = VMAXPSrm
  { 2953,	7,	1,	0,	"VMAXPSrm_Int", 0|(1<<TID::MayLoad), 0x55f400106ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2953 = VMAXPSrm_Int
  { 2954,	3,	1,	0,	"VMAXPSrr", 0, 0x55f400105ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2954 = VMAXPSrr
  { 2955,	3,	1,	0,	"VMAXPSrr_Int", 0, 0x55f400105ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2955 = VMAXPSrr_Int
  { 2956,	7,	1,	0,	"VMAXSDrm", 0|(1<<TID::MayLoad), 0x55f000b06ULL, NULL, NULL, NULL, OperandInfo226 },  // Inst #2956 = VMAXSDrm
  { 2957,	7,	1,	0,	"VMAXSDrm_Int", 0|(1<<TID::MayLoad), 0x55f000b06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2957 = VMAXSDrm_Int
  { 2958,	3,	1,	0,	"VMAXSDrr", 0, 0x55f000b05ULL, NULL, NULL, NULL, OperandInfo227 },  // Inst #2958 = VMAXSDrr
  { 2959,	3,	1,	0,	"VMAXSDrr_Int", 0, 0x55f000b05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2959 = VMAXSDrr_Int
  { 2960,	7,	1,	0,	"VMAXSSrm", 0|(1<<TID::MayLoad), 0x55f000c06ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #2960 = VMAXSSrm
  { 2961,	7,	1,	0,	"VMAXSSrm_Int", 0|(1<<TID::MayLoad), 0x55f000c06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2961 = VMAXSSrm_Int
  { 2962,	3,	1,	0,	"VMAXSSrr", 0, 0x55f000c05ULL, NULL, NULL, NULL, OperandInfo229 },  // Inst #2962 = VMAXSSrr
  { 2963,	3,	1,	0,	"VMAXSSrr_Int", 0, 0x55f000c05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2963 = VMAXSSrr_Int
  { 2964,	0,	0,	0,	"VMCALL", 0|(1<<TID::UnmodeledSideEffects), 0x1000121ULL, NULL, NULL, NULL, 0 },  // Inst #2964 = VMCALL
  { 2965,	5,	0,	0,	"VMCLEARm", 0|(1<<TID::UnmodeledSideEffects), 0xc700015eULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #2965 = VMCLEARm
  { 2966,	7,	1,	0,	"VMINPDYrm", 0|(1<<TID::MayLoad), 0x55d800146ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2966 = VMINPDYrm
  { 2967,	7,	1,	0,	"VMINPDYrm_Int", 0|(1<<TID::MayLoad), 0x55d800146ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2967 = VMINPDYrm_Int
  { 2968,	3,	1,	0,	"VMINPDYrr", 0, 0x55d800145ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2968 = VMINPDYrr
  { 2969,	3,	1,	0,	"VMINPDYrr_Int", 0, 0x55d800145ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2969 = VMINPDYrr_Int
  { 2970,	7,	1,	0,	"VMINPDrm", 0|(1<<TID::MayLoad), 0x55d800146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2970 = VMINPDrm
  { 2971,	7,	1,	0,	"VMINPDrm_Int", 0|(1<<TID::MayLoad), 0x55d800146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2971 = VMINPDrm_Int
  { 2972,	3,	1,	0,	"VMINPDrr", 0, 0x55d800145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2972 = VMINPDrr
  { 2973,	3,	1,	0,	"VMINPDrr_Int", 0, 0x55d800145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2973 = VMINPDrr_Int
  { 2974,	7,	1,	0,	"VMINPSYrm", 0|(1<<TID::MayLoad), 0x55d400106ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2974 = VMINPSYrm
  { 2975,	7,	1,	0,	"VMINPSYrm_Int", 0|(1<<TID::MayLoad), 0x55d400106ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #2975 = VMINPSYrm_Int
  { 2976,	3,	1,	0,	"VMINPSYrr", 0, 0x55d400105ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2976 = VMINPSYrr
  { 2977,	3,	1,	0,	"VMINPSYrr_Int", 0, 0x55d400105ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #2977 = VMINPSYrr_Int
  { 2978,	7,	1,	0,	"VMINPSrm", 0|(1<<TID::MayLoad), 0x55d400106ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2978 = VMINPSrm
  { 2979,	7,	1,	0,	"VMINPSrm_Int", 0|(1<<TID::MayLoad), 0x55d400106ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2979 = VMINPSrm_Int
  { 2980,	3,	1,	0,	"VMINPSrr", 0, 0x55d400105ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2980 = VMINPSrr
  { 2981,	3,	1,	0,	"VMINPSrr_Int", 0, 0x55d400105ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2981 = VMINPSrr_Int
  { 2982,	7,	1,	0,	"VMINSDrm", 0|(1<<TID::MayLoad), 0x55d000b06ULL, NULL, NULL, NULL, OperandInfo226 },  // Inst #2982 = VMINSDrm
  { 2983,	7,	1,	0,	"VMINSDrm_Int", 0|(1<<TID::MayLoad), 0x55d000b06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2983 = VMINSDrm_Int
  { 2984,	3,	1,	0,	"VMINSDrr", 0, 0x55d000b05ULL, NULL, NULL, NULL, OperandInfo227 },  // Inst #2984 = VMINSDrr
  { 2985,	3,	1,	0,	"VMINSDrr_Int", 0, 0x55d000b05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2985 = VMINSDrr_Int
  { 2986,	7,	1,	0,	"VMINSSrm", 0|(1<<TID::MayLoad), 0x55d000c06ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #2986 = VMINSSrm
  { 2987,	7,	1,	0,	"VMINSSrm_Int", 0|(1<<TID::MayLoad), 0x55d000c06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #2987 = VMINSSrm_Int
  { 2988,	3,	1,	0,	"VMINSSrr", 0, 0x55d000c05ULL, NULL, NULL, NULL, OperandInfo229 },  // Inst #2988 = VMINSSrr
  { 2989,	3,	1,	0,	"VMINSSrr_Int", 0, 0x55d000c05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #2989 = VMINSSrr_Int
  { 2990,	0,	0,	0,	"VMLAUNCH", 0|(1<<TID::UnmodeledSideEffects), 0x1000122ULL, NULL, NULL, NULL, 0 },  // Inst #2990 = VMLAUNCH
  { 2991,	6,	0,	0,	"VMOVAPDYmr", 0|(1<<TID::MayStore), 0x129800044ULL, NULL, NULL, NULL, OperandInfo256 },  // Inst #2991 = VMOVAPDYmr
  { 2992,	6,	1,	0,	"VMOVAPDYrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x128800046ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #2992 = VMOVAPDYrm
  { 2993,	2,	1,	0,	"VMOVAPDYrr", 0, 0x128800045ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #2993 = VMOVAPDYrr
  { 2994,	6,	0,	0,	"VMOVAPDmr", 0|(1<<TID::MayStore), 0x129800044ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #2994 = VMOVAPDmr
  { 2995,	6,	1,	0,	"VMOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x128800046ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #2995 = VMOVAPDrm
  { 2996,	2,	1,	0,	"VMOVAPDrr", 0, 0x128800045ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #2996 = VMOVAPDrr
  { 2997,	6,	0,	0,	"VMOVAPSYmr", 0|(1<<TID::MayStore), 0x129400004ULL, NULL, NULL, NULL, OperandInfo256 },  // Inst #2997 = VMOVAPSYmr
  { 2998,	6,	1,	0,	"VMOVAPSYrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x128400006ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #2998 = VMOVAPSYrm
  { 2999,	2,	1,	0,	"VMOVAPSYrr", 0, 0x128400005ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #2999 = VMOVAPSYrr
  { 3000,	6,	0,	0,	"VMOVAPSmr", 0|(1<<TID::MayStore), 0x129400004ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3000 = VMOVAPSmr
  { 3001,	6,	1,	0,	"VMOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x128400006ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3001 = VMOVAPSrm
  { 3002,	2,	1,	0,	"VMOVAPSrr", 0, 0x128400005ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3002 = VMOVAPSrr
  { 3003,	6,	1,	0,	"VMOVDDUPYrm", 0|(1<<TID::UnmodeledSideEffects), 0x112800b06ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3003 = VMOVDDUPYrm
  { 3004,	2,	1,	0,	"VMOVDDUPYrr", 0|(1<<TID::UnmodeledSideEffects), 0x112800b05ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3004 = VMOVDDUPYrr
  { 3005,	6,	1,	0,	"VMOVDDUPrm", 0|(1<<TID::MayLoad), 0x112800b06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3005 = VMOVDDUPrm
  { 3006,	2,	1,	0,	"VMOVDDUPrr", 0, 0x112800b05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3006 = VMOVDDUPrr
  { 3007,	6,	1,	0,	"VMOVDI2PDIrm", 0|(1<<TID::MayLoad), 0x16e800046ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3007 = VMOVDI2PDIrm
  { 3008,	2,	1,	0,	"VMOVDI2PDIrr", 0, 0x16e800045ULL, NULL, NULL, NULL, OperandInfo187 },  // Inst #3008 = VMOVDI2PDIrr
  { 3009,	6,	1,	0,	"VMOVDI2SSrm", 0|(1<<TID::MayLoad), 0x16e800046ULL, NULL, NULL, NULL, OperandInfo92 },  // Inst #3009 = VMOVDI2SSrm
  { 3010,	2,	1,	0,	"VMOVDI2SSrr", 0, 0x16e800045ULL, NULL, NULL, NULL, OperandInfo98 },  // Inst #3010 = VMOVDI2SSrr
  { 3011,	6,	0,	0,	"VMOVDQAYmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x17fc00044ULL, NULL, NULL, NULL, OperandInfo256 },  // Inst #3011 = VMOVDQAYmr
  { 3012,	6,	1,	0,	"VMOVDQAYrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x16fc00046ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3012 = VMOVDQAYrm
  { 3013,	2,	1,	0,	"VMOVDQAYrr", 0, 0x16fc00045ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3013 = VMOVDQAYrr
  { 3014,	6,	0,	0,	"VMOVDQAmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x17fc00044ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3014 = VMOVDQAmr
  { 3015,	6,	1,	0,	"VMOVDQArm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x16fc00046ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3015 = VMOVDQArm
  { 3016,	2,	1,	0,	"VMOVDQArr", 0, 0x16fc00045ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3016 = VMOVDQArr
  { 3017,	6,	0,	0,	"VMOVDQUYmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x17fc00c04ULL, NULL, NULL, NULL, OperandInfo256 },  // Inst #3017 = VMOVDQUYmr
  { 3018,	6,	1,	0,	"VMOVDQUYrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x16fc00c06ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3018 = VMOVDQUYrm
  { 3019,	2,	1,	0,	"VMOVDQUYrr", 0|(1<<TID::UnmodeledSideEffects), 0x16fc00c45ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3019 = VMOVDQUYrr
  { 3020,	6,	0,	0,	"VMOVDQUmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x17fc00c04ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3020 = VMOVDQUmr
  { 3021,	6,	0,	0,	"VMOVDQUmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x17fc00c04ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3021 = VMOVDQUmr_Int
  { 3022,	6,	1,	0,	"VMOVDQUrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x16fc00c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3022 = VMOVDQUrm
  { 3023,	6,	1,	0,	"VMOVDQUrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x16fc00c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3023 = VMOVDQUrm_Int
  { 3024,	2,	1,	0,	"VMOVDQUrr", 0|(1<<TID::UnmodeledSideEffects), 0x16fc00c45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3024 = VMOVDQUrr
  { 3025,	3,	1,	0,	"VMOVHLPSrr", 0, 0x512400005ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3025 = VMOVHLPSrr
  { 3026,	6,	0,	0,	"VMOVHPDmr", 0|(1<<TID::MayStore), 0x117800044ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3026 = VMOVHPDmr
  { 3027,	7,	1,	0,	"VMOVHPDrm", 0|(1<<TID::MayLoad), 0x516800146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3027 = VMOVHPDrm
  { 3028,	6,	0,	0,	"VMOVHPSmr", 0|(1<<TID::MayStore), 0x117400004ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3028 = VMOVHPSmr
  { 3029,	7,	1,	0,	"VMOVHPSrm", 0|(1<<TID::MayLoad), 0x516400106ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3029 = VMOVHPSrm
  { 3030,	3,	1,	0,	"VMOVLHPSrr", 0, 0x516400005ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3030 = VMOVLHPSrr
  { 3031,	6,	0,	0,	"VMOVLPDmr", 0|(1<<TID::MayStore), 0x113800044ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3031 = VMOVLPDmr
  { 3032,	7,	1,	0,	"VMOVLPDrm", 0|(1<<TID::MayLoad), 0x512800146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3032 = VMOVLPDrm
  { 3033,	6,	0,	0,	"VMOVLPSmr", 0|(1<<TID::MayStore), 0x113400004ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3033 = VMOVLPSmr
  { 3034,	7,	1,	0,	"VMOVLPSrm", 0|(1<<TID::MayLoad), 0x512400106ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3034 = VMOVLPSrm
  { 3035,	6,	0,	0,	"VMOVLQ128mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x1d6800044ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3035 = VMOVLQ128mr
  { 3036,	2,	1,	0,	"VMOVMSKPDYr64r", 0|(1<<TID::UnmodeledSideEffects), 0x150800045ULL, NULL, NULL, NULL, OperandInfo257 },  // Inst #3036 = VMOVMSKPDYr64r
  { 3037,	2,	1,	0,	"VMOVMSKPDYrr", 0, 0x150800045ULL, NULL, NULL, NULL, OperandInfo258 },  // Inst #3037 = VMOVMSKPDYrr
  { 3038,	2,	1,	0,	"VMOVMSKPDr64r", 0|(1<<TID::UnmodeledSideEffects), 0x150800045ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #3038 = VMOVMSKPDr64r
  { 3039,	2,	1,	0,	"VMOVMSKPDrr", 0, 0x150800045ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #3039 = VMOVMSKPDrr
  { 3040,	2,	1,	0,	"VMOVMSKPSYr64r", 0|(1<<TID::UnmodeledSideEffects), 0x150400005ULL, NULL, NULL, NULL, OperandInfo257 },  // Inst #3040 = VMOVMSKPSYr64r
  { 3041,	2,	1,	0,	"VMOVMSKPSYrr", 0, 0x150400005ULL, NULL, NULL, NULL, OperandInfo258 },  // Inst #3041 = VMOVMSKPSYrr
  { 3042,	2,	1,	0,	"VMOVMSKPSr64r", 0|(1<<TID::UnmodeledSideEffects), 0x150400005ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #3042 = VMOVMSKPSr64r
  { 3043,	2,	1,	0,	"VMOVMSKPSrr", 0, 0x150400005ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #3043 = VMOVMSKPSrr
  { 3044,	6,	1,	0,	"VMOVNTDQArm", 0|(1<<TID::MayLoad), 0x12ac00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3044 = VMOVNTDQArm
  { 3045,	6,	0,	0,	"VMOVNTDQY_64mr", 0|(1<<TID::MayStore), 0x1e7800044ULL, NULL, NULL, NULL, OperandInfo256 },  // Inst #3045 = VMOVNTDQY_64mr
  { 3046,	6,	0,	0,	"VMOVNTDQYmr", 0|(1<<TID::MayStore), 0x1e7c00044ULL, NULL, NULL, NULL, OperandInfo256 },  // Inst #3046 = VMOVNTDQYmr
  { 3047,	6,	0,	0,	"VMOVNTDQ_64mr", 0|(1<<TID::MayStore), 0x1e7800044ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3047 = VMOVNTDQ_64mr
  { 3048,	6,	0,	0,	"VMOVNTDQmr", 0|(1<<TID::MayStore), 0x1e7c00044ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3048 = VMOVNTDQmr
  { 3049,	6,	0,	0,	"VMOVNTDQmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x1e7c00044ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3049 = VMOVNTDQmr_Int
  { 3050,	6,	0,	0,	"VMOVNTPDYmr", 0|(1<<TID::MayStore), 0x12b800044ULL, NULL, NULL, NULL, OperandInfo256 },  // Inst #3050 = VMOVNTPDYmr
  { 3051,	6,	0,	0,	"VMOVNTPDmr", 0|(1<<TID::MayStore), 0x12b800044ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3051 = VMOVNTPDmr
  { 3052,	6,	0,	0,	"VMOVNTPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x12b800044ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3052 = VMOVNTPDmr_Int
  { 3053,	6,	0,	0,	"VMOVNTPSYmr", 0|(1<<TID::MayStore), 0x12b400004ULL, NULL, NULL, NULL, OperandInfo256 },  // Inst #3053 = VMOVNTPSYmr
  { 3054,	6,	0,	0,	"VMOVNTPSmr", 0|(1<<TID::MayStore), 0x12b400004ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3054 = VMOVNTPSmr
  { 3055,	6,	0,	0,	"VMOVNTPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x12b400004ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3055 = VMOVNTPSmr_Int
  { 3056,	6,	0,	0,	"VMOVPDI2DImr", 0|(1<<TID::MayStore), 0x17e800044ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3056 = VMOVPDI2DImr
  { 3057,	2,	1,	0,	"VMOVPDI2DIrr", 0, 0x17e800043ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #3057 = VMOVPDI2DIrr
  { 3058,	6,	0,	0,	"VMOVPQI2QImr", 0|(1<<TID::MayStore), 0x1d6800044ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3058 = VMOVPQI2QImr
  { 3059,	6,	1,	0,	"VMOVQI2PQIrm", 0|(1<<TID::MayLoad), 0x17e000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3059 = VMOVQI2PQIrm
  { 3060,	2,	1,	0,	"VMOVQd64rr", 0|(1<<TID::UnmodeledSideEffects), 0x37e800043ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #3060 = VMOVQd64rr
  { 3061,	2,	1,	0,	"VMOVQd64rr_alt", 0|(1<<TID::UnmodeledSideEffects), 0x37e800043ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #3061 = VMOVQd64rr_alt
  { 3062,	2,	1,	0,	"VMOVQs64rr", 0|(1<<TID::UnmodeledSideEffects), 0x36e800045ULL, NULL, NULL, NULL, OperandInfo182 },  // Inst #3062 = VMOVQs64rr
  { 3063,	2,	1,	0,	"VMOVQxrxr", 0|(1<<TID::UnmodeledSideEffects), 0x17e000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3063 = VMOVQxrxr
  { 3064,	6,	0,	0,	"VMOVSDmr", 0|(1<<TID::MayStore), 0x111000b04ULL, NULL, NULL, NULL, OperandInfo188 },  // Inst #3064 = VMOVSDmr
  { 3065,	6,	1,	0,	"VMOVSDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x110000b06ULL, NULL, NULL, NULL, OperandInfo94 },  // Inst #3065 = VMOVSDrm
  { 3066,	3,	1,	0,	"VMOVSDrr", 0, 0x510000b05ULL, NULL, NULL, NULL, OperandInfo259 },  // Inst #3066 = VMOVSDrr
  { 3067,	6,	1,	0,	"VMOVSHDUPYrm", 0|(1<<TID::UnmodeledSideEffects), 0x116400c06ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3067 = VMOVSHDUPYrm
  { 3068,	2,	1,	0,	"VMOVSHDUPYrr", 0|(1<<TID::UnmodeledSideEffects), 0x116400c05ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3068 = VMOVSHDUPYrr
  { 3069,	6,	1,	0,	"VMOVSHDUPrm", 0|(1<<TID::MayLoad), 0x116400c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3069 = VMOVSHDUPrm
  { 3070,	2,	1,	0,	"VMOVSHDUPrr", 0, 0x116400c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3070 = VMOVSHDUPrr
  { 3071,	6,	1,	0,	"VMOVSLDUPYrm", 0|(1<<TID::UnmodeledSideEffects), 0x112400c06ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3071 = VMOVSLDUPYrm
  { 3072,	2,	1,	0,	"VMOVSLDUPYrr", 0|(1<<TID::UnmodeledSideEffects), 0x112400c05ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3072 = VMOVSLDUPYrr
  { 3073,	6,	1,	0,	"VMOVSLDUPrm", 0|(1<<TID::MayLoad), 0x112400c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3073 = VMOVSLDUPrm
  { 3074,	2,	1,	0,	"VMOVSLDUPrr", 0, 0x112400c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3074 = VMOVSLDUPrr
  { 3075,	6,	0,	0,	"VMOVSS2DImr", 0|(1<<TID::MayStore), 0x17e800044ULL, NULL, NULL, NULL, OperandInfo190 },  // Inst #3075 = VMOVSS2DImr
  { 3076,	2,	1,	0,	"VMOVSS2DIrr", 0, 0x17e800043ULL, NULL, NULL, NULL, OperandInfo101 },  // Inst #3076 = VMOVSS2DIrr
  { 3077,	6,	0,	0,	"VMOVSSmr", 0|(1<<TID::MayStore), 0x111000c04ULL, NULL, NULL, NULL, OperandInfo190 },  // Inst #3077 = VMOVSSmr
  { 3078,	6,	1,	0,	"VMOVSSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x110000c06ULL, NULL, NULL, NULL, OperandInfo92 },  // Inst #3078 = VMOVSSrm
  { 3079,	3,	1,	0,	"VMOVSSrr", 0, 0x510000c05ULL, NULL, NULL, NULL, OperandInfo260 },  // Inst #3079 = VMOVSSrr
  { 3080,	6,	0,	0,	"VMOVUPDYmr", 0|(1<<TID::MayStore), 0x111800044ULL, NULL, NULL, NULL, OperandInfo256 },  // Inst #3080 = VMOVUPDYmr
  { 3081,	6,	1,	0,	"VMOVUPDYrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x110800046ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3081 = VMOVUPDYrm
  { 3082,	2,	1,	0,	"VMOVUPDYrr", 0, 0x110800045ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3082 = VMOVUPDYrr
  { 3083,	6,	0,	0,	"VMOVUPDmr", 0|(1<<TID::MayStore), 0x111800044ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3083 = VMOVUPDmr
  { 3084,	6,	0,	0,	"VMOVUPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x111800044ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3084 = VMOVUPDmr_Int
  { 3085,	6,	1,	0,	"VMOVUPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x110800046ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3085 = VMOVUPDrm
  { 3086,	6,	1,	0,	"VMOVUPDrm_Int", 0|(1<<TID::MayLoad), 0x110800046ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3086 = VMOVUPDrm_Int
  { 3087,	2,	1,	0,	"VMOVUPDrr", 0, 0x110800045ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3087 = VMOVUPDrr
  { 3088,	6,	0,	0,	"VMOVUPSYmr", 0|(1<<TID::MayStore), 0x111400004ULL, NULL, NULL, NULL, OperandInfo256 },  // Inst #3088 = VMOVUPSYmr
  { 3089,	6,	1,	0,	"VMOVUPSYrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x110400006ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3089 = VMOVUPSYrm
  { 3090,	2,	1,	0,	"VMOVUPSYrr", 0, 0x110400005ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3090 = VMOVUPSYrr
  { 3091,	6,	0,	0,	"VMOVUPSmr", 0|(1<<TID::MayStore), 0x111400004ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3091 = VMOVUPSmr
  { 3092,	6,	0,	0,	"VMOVUPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x111400004ULL, NULL, NULL, NULL, OperandInfo186 },  // Inst #3092 = VMOVUPSmr_Int
  { 3093,	6,	1,	0,	"VMOVUPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x110400006ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3093 = VMOVUPSrm
  { 3094,	6,	1,	0,	"VMOVUPSrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0x110400006ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3094 = VMOVUPSrm_Int
  { 3095,	2,	1,	0,	"VMOVUPSrr", 0, 0x110400005ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3095 = VMOVUPSrr
  { 3096,	6,	1,	0,	"VMOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0x16e800046ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3096 = VMOVZDI2PDIrm
  { 3097,	2,	1,	0,	"VMOVZDI2PDIrr", 0, 0x16e800045ULL, NULL, NULL, NULL, OperandInfo187 },  // Inst #3097 = VMOVZDI2PDIrr
  { 3098,	6,	1,	0,	"VMOVZPQILo2PQIrm", 0|(1<<TID::MayLoad), 0x17e000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3098 = VMOVZPQILo2PQIrm
  { 3099,	2,	1,	0,	"VMOVZPQILo2PQIrr", 0, 0x17e000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3099 = VMOVZPQILo2PQIrr
  { 3100,	6,	1,	0,	"VMOVZQI2PQIrm", 0|(1<<TID::MayLoad), 0x17e000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3100 = VMOVZQI2PQIrm
  { 3101,	2,	1,	0,	"VMOVZQI2PQIrr", 0, 0x36e800045ULL, NULL, NULL, NULL, OperandInfo182 },  // Inst #3101 = VMOVZQI2PQIrr
  { 3102,	8,	1,	0,	"VMPSADBWrmi", 0|(1<<TID::MayLoad), 0x542c02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #3102 = VMPSADBWrmi
  { 3103,	4,	1,	0,	"VMPSADBWrri", 0, 0x542c02e45ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #3103 = VMPSADBWrri
  { 3104,	5,	0,	0,	"VMPTRLDm", 0|(1<<TID::UnmodeledSideEffects), 0xc700011eULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #3104 = VMPTRLDm
  { 3105,	5,	1,	0,	"VMPTRSTm", 0|(1<<TID::UnmodeledSideEffects), 0xc700011fULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #3105 = VMPTRSTm
  { 3106,	6,	1,	0,	"VMREAD32rm", 0|(1<<TID::UnmodeledSideEffects), 0x78000104ULL, NULL, NULL, NULL, OperandInfo15 },  // Inst #3106 = VMREAD32rm
  { 3107,	2,	1,	0,	"VMREAD32rr", 0|(1<<TID::UnmodeledSideEffects), 0x78000103ULL, NULL, NULL, NULL, OperandInfo58 },  // Inst #3107 = VMREAD32rr
  { 3108,	6,	1,	0,	"VMREAD64rm", 0|(1<<TID::UnmodeledSideEffects), 0x78000104ULL, NULL, NULL, NULL, OperandInfo19 },  // Inst #3108 = VMREAD64rm
  { 3109,	2,	1,	0,	"VMREAD64rr", 0|(1<<TID::UnmodeledSideEffects), 0x78000103ULL, NULL, NULL, NULL, OperandInfo60 },  // Inst #3109 = VMREAD64rr
  { 3110,	0,	0,	0,	"VMRESUME", 0|(1<<TID::UnmodeledSideEffects), 0x1000123ULL, NULL, NULL, NULL, 0 },  // Inst #3110 = VMRESUME
  { 3111,	7,	1,	0,	"VMULPDYrm", 0|(1<<TID::MayLoad), 0x559800146ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #3111 = VMULPDYrm
  { 3112,	3,	1,	0,	"VMULPDYrr", 0|(1<<TID::Commutable), 0x559800145ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #3112 = VMULPDYrr
  { 3113,	7,	1,	0,	"VMULPDrm", 0|(1<<TID::MayLoad), 0x559800146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3113 = VMULPDrm
  { 3114,	3,	1,	0,	"VMULPDrr", 0|(1<<TID::Commutable), 0x559800145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3114 = VMULPDrr
  { 3115,	7,	1,	0,	"VMULPSYrm", 0|(1<<TID::MayLoad), 0x559400106ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #3115 = VMULPSYrm
  { 3116,	3,	1,	0,	"VMULPSYrr", 0|(1<<TID::Commutable), 0x559400105ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #3116 = VMULPSYrr
  { 3117,	7,	1,	0,	"VMULPSrm", 0|(1<<TID::MayLoad), 0x559400106ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3117 = VMULPSrm
  { 3118,	3,	1,	0,	"VMULPSrr", 0|(1<<TID::Commutable), 0x559400105ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3118 = VMULPSrr
  { 3119,	7,	1,	0,	"VMULSDrm", 0|(1<<TID::MayLoad), 0x559000b06ULL, NULL, NULL, NULL, OperandInfo226 },  // Inst #3119 = VMULSDrm
  { 3120,	7,	1,	0,	"VMULSDrm_Int", 0|(1<<TID::MayLoad), 0x559000b06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3120 = VMULSDrm_Int
  { 3121,	3,	1,	0,	"VMULSDrr", 0|(1<<TID::Commutable), 0x559000b05ULL, NULL, NULL, NULL, OperandInfo227 },  // Inst #3121 = VMULSDrr
  { 3122,	3,	1,	0,	"VMULSDrr_Int", 0, 0x559000b05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3122 = VMULSDrr_Int
  { 3123,	7,	1,	0,	"VMULSSrm", 0|(1<<TID::MayLoad), 0x559000c06ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #3123 = VMULSSrm
  { 3124,	7,	1,	0,	"VMULSSrm_Int", 0|(1<<TID::MayLoad), 0x559000c06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3124 = VMULSSrm_Int
  { 3125,	3,	1,	0,	"VMULSSrr", 0|(1<<TID::Commutable), 0x559000c05ULL, NULL, NULL, NULL, OperandInfo229 },  // Inst #3125 = VMULSSrr
  { 3126,	3,	1,	0,	"VMULSSrr_Int", 0, 0x559000c05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3126 = VMULSSrr_Int
  { 3127,	6,	1,	0,	"VMWRITE32rm", 0|(1<<TID::UnmodeledSideEffects), 0x79000106ULL, NULL, NULL, NULL, OperandInfo57 },  // Inst #3127 = VMWRITE32rm
  { 3128,	2,	1,	0,	"VMWRITE32rr", 0|(1<<TID::UnmodeledSideEffects), 0x79000105ULL, NULL, NULL, NULL, OperandInfo58 },  // Inst #3128 = VMWRITE32rr
  { 3129,	6,	1,	0,	"VMWRITE64rm", 0|(1<<TID::UnmodeledSideEffects), 0x79000106ULL, NULL, NULL, NULL, OperandInfo59 },  // Inst #3129 = VMWRITE64rm
  { 3130,	2,	1,	0,	"VMWRITE64rr", 0|(1<<TID::UnmodeledSideEffects), 0x79000105ULL, NULL, NULL, NULL, OperandInfo60 },  // Inst #3130 = VMWRITE64rr
  { 3131,	0,	0,	0,	"VMXOFF", 0|(1<<TID::UnmodeledSideEffects), 0x1000124ULL, NULL, NULL, NULL, 0 },  // Inst #3131 = VMXOFF
  { 3132,	5,	0,	0,	"VMXON", 0|(1<<TID::UnmodeledSideEffects), 0xc7000c1eULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #3132 = VMXON
  { 3133,	7,	1,	0,	"VORPDYrm", 0|(1<<TID::UnmodeledSideEffects), 0x556800046ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #3133 = VORPDYrm
  { 3134,	3,	1,	0,	"VORPDYrr", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0x556800045ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #3134 = VORPDYrr
  { 3135,	7,	1,	0,	"VORPDrm", 0|(1<<TID::UnmodeledSideEffects), 0x556800046ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3135 = VORPDrm
  { 3136,	3,	1,	0,	"VORPDrr", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0x556800045ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3136 = VORPDrr
  { 3137,	7,	1,	0,	"VORPSYrm", 0|(1<<TID::UnmodeledSideEffects), 0x556400006ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #3137 = VORPSYrm
  { 3138,	3,	1,	0,	"VORPSYrr", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0x556400005ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #3138 = VORPSYrr
  { 3139,	7,	1,	0,	"VORPSrm", 0|(1<<TID::UnmodeledSideEffects), 0x556400006ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3139 = VORPSrm
  { 3140,	3,	1,	0,	"VORPSrr", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0x556400005ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3140 = VORPSrr
  { 3141,	6,	1,	0,	"VPABSBrm128", 0|(1<<TID::MayLoad), 0x11cc02d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3141 = VPABSBrm128
  { 3142,	2,	1,	0,	"VPABSBrr128", 0, 0x11cc02d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3142 = VPABSBrr128
  { 3143,	6,	1,	0,	"VPABSDrm128", 0|(1<<TID::MayLoad), 0x11ec02d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3143 = VPABSDrm128
  { 3144,	2,	1,	0,	"VPABSDrr128", 0, 0x11ec02d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3144 = VPABSDrr128
  { 3145,	6,	1,	0,	"VPABSWrm128", 0|(1<<TID::MayLoad), 0x11dc02d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3145 = VPABSWrm128
  { 3146,	2,	1,	0,	"VPABSWrr128", 0, 0x11dc02d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3146 = VPABSWrr128
  { 3147,	7,	1,	0,	"VPACKSSDWrm", 0|(1<<TID::MayLoad), 0x56bc00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3147 = VPACKSSDWrm
  { 3148,	3,	1,	0,	"VPACKSSDWrr", 0, 0x56bc00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3148 = VPACKSSDWrr
  { 3149,	7,	1,	0,	"VPACKSSWBrm", 0|(1<<TID::MayLoad), 0x563c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3149 = VPACKSSWBrm
  { 3150,	3,	1,	0,	"VPACKSSWBrr", 0, 0x563c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3150 = VPACKSSWBrr
  { 3151,	7,	1,	0,	"VPACKUSDWrm", 0|(1<<TID::MayLoad), 0x52bc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3151 = VPACKUSDWrm
  { 3152,	3,	1,	0,	"VPACKUSDWrr", 0, 0x52bc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3152 = VPACKUSDWrr
  { 3153,	7,	1,	0,	"VPACKUSWBrm", 0|(1<<TID::MayLoad), 0x567c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3153 = VPACKUSWBrm
  { 3154,	3,	1,	0,	"VPACKUSWBrr", 0, 0x567c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3154 = VPACKUSWBrr
  { 3155,	7,	1,	0,	"VPADDBrm", 0|(1<<TID::MayLoad), 0x5fcc00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3155 = VPADDBrm
  { 3156,	3,	1,	0,	"VPADDBrr", 0|(1<<TID::Commutable), 0x5fcc00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3156 = VPADDBrr
  { 3157,	7,	1,	0,	"VPADDDrm", 0|(1<<TID::MayLoad), 0x5fec00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3157 = VPADDDrm
  { 3158,	3,	1,	0,	"VPADDDrr", 0|(1<<TID::Commutable), 0x5fec00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3158 = VPADDDrr
  { 3159,	7,	1,	0,	"VPADDQrm", 0|(1<<TID::MayLoad), 0x5d4c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3159 = VPADDQrm
  { 3160,	3,	1,	0,	"VPADDQrr", 0|(1<<TID::Commutable), 0x5d4c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3160 = VPADDQrr
  { 3161,	7,	1,	0,	"VPADDSBrm", 0|(1<<TID::MayLoad), 0x5ecc00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3161 = VPADDSBrm
  { 3162,	3,	1,	0,	"VPADDSBrr", 0|(1<<TID::Commutable), 0x5ecc00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3162 = VPADDSBrr
  { 3163,	7,	1,	0,	"VPADDSWrm", 0|(1<<TID::MayLoad), 0x5edc00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3163 = VPADDSWrm
  { 3164,	3,	1,	0,	"VPADDSWrr", 0|(1<<TID::Commutable), 0x5edc00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3164 = VPADDSWrr
  { 3165,	7,	1,	0,	"VPADDUSBrm", 0|(1<<TID::MayLoad), 0x5dcc00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3165 = VPADDUSBrm
  { 3166,	3,	1,	0,	"VPADDUSBrr", 0|(1<<TID::Commutable), 0x5dcc00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3166 = VPADDUSBrr
  { 3167,	7,	1,	0,	"VPADDUSWrm", 0|(1<<TID::MayLoad), 0x5ddc00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3167 = VPADDUSWrm
  { 3168,	3,	1,	0,	"VPADDUSWrr", 0|(1<<TID::Commutable), 0x5ddc00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3168 = VPADDUSWrr
  { 3169,	7,	1,	0,	"VPADDWrm", 0|(1<<TID::MayLoad), 0x5fdc00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3169 = VPADDWrm
  { 3170,	3,	1,	0,	"VPADDWrr", 0|(1<<TID::Commutable), 0x5fdc00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3170 = VPADDWrr
  { 3171,	8,	1,	0,	"VPALIGNR128rm", 0|(1<<TID::UnmodeledSideEffects), 0x50fc02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #3171 = VPALIGNR128rm
  { 3172,	4,	1,	0,	"VPALIGNR128rr", 0|(1<<TID::UnmodeledSideEffects), 0x50fc02e45ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #3172 = VPALIGNR128rr
  { 3173,	7,	1,	0,	"VPANDNrm", 0|(1<<TID::MayLoad), 0x5dfc00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3173 = VPANDNrm
  { 3174,	3,	1,	0,	"VPANDNrr", 0, 0x5dfc00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3174 = VPANDNrr
  { 3175,	7,	1,	0,	"VPANDrm", 0|(1<<TID::MayLoad), 0x5dbc00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3175 = VPANDrm
  { 3176,	3,	1,	0,	"VPANDrr", 0|(1<<TID::Commutable), 0x5dbc00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3176 = VPANDrr
  { 3177,	7,	1,	0,	"VPAVGBrm", 0|(1<<TID::MayLoad), 0x5e0c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3177 = VPAVGBrm
  { 3178,	3,	1,	0,	"VPAVGBrr", 0|(1<<TID::Commutable), 0x5e0c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3178 = VPAVGBrr
  { 3179,	7,	1,	0,	"VPAVGWrm", 0|(1<<TID::MayLoad), 0x5e3c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3179 = VPAVGWrm
  { 3180,	3,	1,	0,	"VPAVGWrr", 0|(1<<TID::Commutable), 0x5e3c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3180 = VPAVGWrr
  { 3181,	8,	1,	0,	"VPBLENDVBrm", 0|(1<<TID::MayLoad), 0xd4cc00e46ULL, NULL, NULL, NULL, OperandInfo235 },  // Inst #3181 = VPBLENDVBrm
  { 3182,	4,	1,	0,	"VPBLENDVBrr", 0, 0xd4cc00e45ULL, NULL, NULL, NULL, OperandInfo236 },  // Inst #3182 = VPBLENDVBrr
  { 3183,	8,	1,	0,	"VPBLENDWrmi", 0|(1<<TID::MayLoad), 0x50ec02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #3183 = VPBLENDWrmi
  { 3184,	4,	1,	0,	"VPBLENDWrri", 0, 0x50ec02e45ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #3184 = VPBLENDWrri
  { 3185,	7,	1,	0,	"VPCLMULHQHQDQrm", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3185 = VPCLMULHQHQDQrm
  { 3186,	3,	1,	0,	"VPCLMULHQHQDQrr", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3186 = VPCLMULHQHQDQrr
  { 3187,	7,	1,	0,	"VPCLMULHQLQDQrm", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3187 = VPCLMULHQLQDQrm
  { 3188,	3,	1,	0,	"VPCLMULHQLQDQrr", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3188 = VPCLMULHQLQDQrr
  { 3189,	7,	1,	0,	"VPCLMULLQHQDQrm", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3189 = VPCLMULLQHQDQrm
  { 3190,	3,	1,	0,	"VPCLMULLQHQDQrr", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3190 = VPCLMULLQHQDQrr
  { 3191,	7,	1,	0,	"VPCLMULLQLQDQrm", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3191 = VPCLMULLQLQDQrm
  { 3192,	3,	1,	0,	"VPCLMULLQLQDQrr", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3192 = VPCLMULLQLQDQrr
  { 3193,	8,	1,	0,	"VPCLMULQDQrm", 0|(1<<TID::UnmodeledSideEffects), 0x544c02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #3193 = VPCLMULQDQrm
  { 3194,	4,	1,	0,	"VPCLMULQDQrr", 0|(1<<TID::UnmodeledSideEffects), 0x544c02e45ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #3194 = VPCLMULQDQrr
  { 3195,	7,	1,	0,	"VPCMPEQBrm", 0|(1<<TID::MayLoad), 0x574c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3195 = VPCMPEQBrm
  { 3196,	3,	1,	0,	"VPCMPEQBrr", 0|(1<<TID::Commutable), 0x574c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3196 = VPCMPEQBrr
  { 3197,	7,	1,	0,	"VPCMPEQDrm", 0|(1<<TID::MayLoad), 0x576c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3197 = VPCMPEQDrm
  { 3198,	3,	1,	0,	"VPCMPEQDrr", 0|(1<<TID::Commutable), 0x576c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3198 = VPCMPEQDrr
  { 3199,	7,	1,	0,	"VPCMPEQQrm", 0|(1<<TID::MayLoad), 0x529c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3199 = VPCMPEQQrm
  { 3200,	3,	1,	0,	"VPCMPEQQrr", 0|(1<<TID::Commutable), 0x529c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3200 = VPCMPEQQrr
  { 3201,	7,	1,	0,	"VPCMPEQWrm", 0|(1<<TID::MayLoad), 0x575c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3201 = VPCMPEQWrm
  { 3202,	3,	1,	0,	"VPCMPEQWrr", 0|(1<<TID::Commutable), 0x575c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3202 = VPCMPEQWrr
  { 3203,	7,	0,	0,	"VPCMPESTRIArm", 0|(1<<TID::MayLoad), 0x161c02e46ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #3203 = VPCMPESTRIArm
  { 3204,	3,	0,	0,	"VPCMPESTRIArr", 0, 0x161c02e45ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #3204 = VPCMPESTRIArr
  { 3205,	7,	0,	0,	"VPCMPESTRICrm", 0|(1<<TID::MayLoad), 0x161c02e46ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #3205 = VPCMPESTRICrm
  { 3206,	3,	0,	0,	"VPCMPESTRICrr", 0, 0x161c02e45ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #3206 = VPCMPESTRICrr
  { 3207,	7,	0,	0,	"VPCMPESTRIOrm", 0|(1<<TID::MayLoad), 0x161c02e46ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #3207 = VPCMPESTRIOrm
  { 3208,	3,	0,	0,	"VPCMPESTRIOrr", 0, 0x161c02e45ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #3208 = VPCMPESTRIOrr
  { 3209,	7,	0,	0,	"VPCMPESTRISrm", 0|(1<<TID::MayLoad), 0x161c02e46ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #3209 = VPCMPESTRISrm
  { 3210,	3,	0,	0,	"VPCMPESTRISrr", 0, 0x161c02e45ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #3210 = VPCMPESTRISrr
  { 3211,	7,	0,	0,	"VPCMPESTRIZrm", 0|(1<<TID::MayLoad), 0x161c02e46ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #3211 = VPCMPESTRIZrm
  { 3212,	3,	0,	0,	"VPCMPESTRIZrr", 0, 0x161c02e45ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #3212 = VPCMPESTRIZrr
  { 3213,	7,	0,	0,	"VPCMPESTRIrm", 0|(1<<TID::MayLoad), 0x161c02e46ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #3213 = VPCMPESTRIrm
  { 3214,	3,	0,	0,	"VPCMPESTRIrr", 0, 0x161c02e45ULL, ImplicitList14, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #3214 = VPCMPESTRIrr
  { 3215,	8,	1,	0,	"VPCMPESTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0x2000ULL, ImplicitList14, ImplicitList1, Barriers1, OperandInfo136 },  // Inst #3215 = VPCMPESTRM128MEM
  { 3216,	4,	1,	0,	"VPCMPESTRM128REG", 0|(1<<TID::UsesCustomInserter), 0x2000ULL, ImplicitList14, ImplicitList1, Barriers1, OperandInfo80 },  // Inst #3216 = VPCMPESTRM128REG
  { 3217,	7,	0,	0,	"VPCMPESTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0x160c02e46ULL, ImplicitList14, ImplicitList43, Barriers1, OperandInfo44 },  // Inst #3217 = VPCMPESTRM128rm
  { 3218,	3,	0,	0,	"VPCMPESTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0x160c02e45ULL, ImplicitList14, ImplicitList43, Barriers1, OperandInfo45 },  // Inst #3218 = VPCMPESTRM128rr
  { 3219,	7,	1,	0,	"VPCMPGTBrm", 0|(1<<TID::MayLoad), 0x564c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3219 = VPCMPGTBrm
  { 3220,	3,	1,	0,	"VPCMPGTBrr", 0, 0x564c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3220 = VPCMPGTBrr
  { 3221,	7,	1,	0,	"VPCMPGTDrm", 0|(1<<TID::MayLoad), 0x566c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3221 = VPCMPGTDrm
  { 3222,	3,	1,	0,	"VPCMPGTDrr", 0, 0x566c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3222 = VPCMPGTDrr
  { 3223,	7,	1,	0,	"VPCMPGTQrm", 0|(1<<TID::MayLoad), 0x537c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3223 = VPCMPGTQrm
  { 3224,	3,	1,	0,	"VPCMPGTQrr", 0, 0x537c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3224 = VPCMPGTQrr
  { 3225,	7,	1,	0,	"VPCMPGTWrm", 0|(1<<TID::MayLoad), 0x565c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3225 = VPCMPGTWrm
  { 3226,	3,	1,	0,	"VPCMPGTWrr", 0, 0x565c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3226 = VPCMPGTWrr
  { 3227,	7,	0,	0,	"VPCMPISTRIArm", 0|(1<<TID::MayLoad), 0x163c02e46ULL, NULL, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #3227 = VPCMPISTRIArm
  { 3228,	3,	0,	0,	"VPCMPISTRIArr", 0, 0x163c02e45ULL, NULL, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #3228 = VPCMPISTRIArr
  { 3229,	7,	0,	0,	"VPCMPISTRICrm", 0|(1<<TID::MayLoad), 0x163c02e46ULL, NULL, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #3229 = VPCMPISTRICrm
  { 3230,	3,	0,	0,	"VPCMPISTRICrr", 0, 0x163c02e45ULL, NULL, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #3230 = VPCMPISTRICrr
  { 3231,	7,	0,	0,	"VPCMPISTRIOrm", 0|(1<<TID::MayLoad), 0x163c02e46ULL, NULL, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #3231 = VPCMPISTRIOrm
  { 3232,	3,	0,	0,	"VPCMPISTRIOrr", 0, 0x163c02e45ULL, NULL, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #3232 = VPCMPISTRIOrr
  { 3233,	7,	0,	0,	"VPCMPISTRISrm", 0|(1<<TID::MayLoad), 0x163c02e46ULL, NULL, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #3233 = VPCMPISTRISrm
  { 3234,	3,	0,	0,	"VPCMPISTRISrr", 0, 0x163c02e45ULL, NULL, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #3234 = VPCMPISTRISrr
  { 3235,	7,	0,	0,	"VPCMPISTRIZrm", 0|(1<<TID::MayLoad), 0x163c02e46ULL, NULL, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #3235 = VPCMPISTRIZrm
  { 3236,	3,	0,	0,	"VPCMPISTRIZrr", 0, 0x163c02e45ULL, NULL, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #3236 = VPCMPISTRIZrr
  { 3237,	7,	0,	0,	"VPCMPISTRIrm", 0|(1<<TID::MayLoad), 0x163c02e46ULL, NULL, ImplicitList42, Barriers1, OperandInfo44 },  // Inst #3237 = VPCMPISTRIrm
  { 3238,	3,	0,	0,	"VPCMPISTRIrr", 0, 0x163c02e45ULL, NULL, ImplicitList42, Barriers1, OperandInfo45 },  // Inst #3238 = VPCMPISTRIrr
  { 3239,	8,	1,	0,	"VPCMPISTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0x2000ULL, NULL, ImplicitList1, Barriers1, OperandInfo136 },  // Inst #3239 = VPCMPISTRM128MEM
  { 3240,	4,	1,	0,	"VPCMPISTRM128REG", 0|(1<<TID::UsesCustomInserter), 0x2000ULL, NULL, ImplicitList1, Barriers1, OperandInfo80 },  // Inst #3240 = VPCMPISTRM128REG
  { 3241,	7,	0,	0,	"VPCMPISTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0x162c02e46ULL, NULL, ImplicitList43, Barriers1, OperandInfo44 },  // Inst #3241 = VPCMPISTRM128rm
  { 3242,	3,	0,	0,	"VPCMPISTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0x162c02e45ULL, NULL, ImplicitList43, Barriers1, OperandInfo45 },  // Inst #3242 = VPCMPISTRM128rr
  { 3243,	8,	1,	0,	"VPERM2F128rm", 0|(1<<TID::UnmodeledSideEffects), 0x506c02e46ULL, NULL, NULL, NULL, OperandInfo231 },  // Inst #3243 = VPERM2F128rm
  { 3244,	4,	1,	0,	"VPERM2F128rr", 0|(1<<TID::UnmodeledSideEffects), 0x506c02e45ULL, NULL, NULL, NULL, OperandInfo232 },  // Inst #3244 = VPERM2F128rr
  { 3245,	7,	1,	0,	"VPERMILPDYmi", 0|(1<<TID::MayLoad), 0x105c02e46ULL, NULL, NULL, NULL, OperandInfo261 },  // Inst #3245 = VPERMILPDYmi
  { 3246,	3,	1,	0,	"VPERMILPDYri", 0, 0x105c02e45ULL, NULL, NULL, NULL, OperandInfo262 },  // Inst #3246 = VPERMILPDYri
  { 3247,	7,	1,	0,	"VPERMILPDYrm", 0|(1<<TID::MayLoad), 0x50dc00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #3247 = VPERMILPDYrm
  { 3248,	3,	1,	0,	"VPERMILPDYrr", 0, 0x50dc00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #3248 = VPERMILPDYrr
  { 3249,	7,	1,	0,	"VPERMILPDmi", 0|(1<<TID::MayLoad), 0x105c02e46ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #3249 = VPERMILPDmi
  { 3250,	3,	1,	0,	"VPERMILPDri", 0, 0x105c02e45ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3250 = VPERMILPDri
  { 3251,	7,	1,	0,	"VPERMILPDrm", 0|(1<<TID::MayLoad), 0x50dc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3251 = VPERMILPDrm
  { 3252,	3,	1,	0,	"VPERMILPDrr", 0, 0x50dc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3252 = VPERMILPDrr
  { 3253,	7,	1,	0,	"VPERMILPSYmi", 0|(1<<TID::MayLoad), 0x104c02e46ULL, NULL, NULL, NULL, OperandInfo261 },  // Inst #3253 = VPERMILPSYmi
  { 3254,	3,	1,	0,	"VPERMILPSYri", 0, 0x104c02e45ULL, NULL, NULL, NULL, OperandInfo262 },  // Inst #3254 = VPERMILPSYri
  { 3255,	7,	1,	0,	"VPERMILPSYrm", 0|(1<<TID::MayLoad), 0x50cc00d46ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #3255 = VPERMILPSYrm
  { 3256,	3,	1,	0,	"VPERMILPSYrr", 0, 0x50cc00d45ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #3256 = VPERMILPSYrr
  { 3257,	7,	1,	0,	"VPERMILPSmi", 0|(1<<TID::MayLoad), 0x104c02e46ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #3257 = VPERMILPSmi
  { 3258,	3,	1,	0,	"VPERMILPSri", 0, 0x104c02e45ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3258 = VPERMILPSri
  { 3259,	7,	1,	0,	"VPERMILPSrm", 0|(1<<TID::MayLoad), 0x50cc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3259 = VPERMILPSrm
  { 3260,	3,	1,	0,	"VPERMILPSrr", 0, 0x50cc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3260 = VPERMILPSrr
  { 3261,	7,	0,	0,	"VPEXTRBmr", 0|(1<<TID::UnmodeledSideEffects), 0x114c02e44ULL, NULL, NULL, NULL, OperandInfo108 },  // Inst #3261 = VPEXTRBmr
  { 3262,	3,	1,	0,	"VPEXTRBrr", 0, 0x114c02e43ULL, NULL, NULL, NULL, OperandInfo109 },  // Inst #3262 = VPEXTRBrr
  { 3263,	3,	1,	0,	"VPEXTRBrr64", 0|(1<<TID::UnmodeledSideEffects), 0x114c02e43ULL, NULL, NULL, NULL, OperandInfo206 },  // Inst #3263 = VPEXTRBrr64
  { 3264,	7,	0,	0,	"VPEXTRDmr", 0|(1<<TID::MayStore), 0x116c02e44ULL, NULL, NULL, NULL, OperandInfo108 },  // Inst #3264 = VPEXTRDmr
  { 3265,	3,	1,	0,	"VPEXTRDrr", 0, 0x116c02e43ULL, NULL, NULL, NULL, OperandInfo109 },  // Inst #3265 = VPEXTRDrr
  { 3266,	7,	0,	0,	"VPEXTRQmr", 0|(1<<TID::MayStore), 0x316c03e44ULL, NULL, NULL, NULL, OperandInfo108 },  // Inst #3266 = VPEXTRQmr
  { 3267,	3,	1,	0,	"VPEXTRQrr", 0, 0x316c03e43ULL, NULL, NULL, NULL, OperandInfo206 },  // Inst #3267 = VPEXTRQrr
  { 3268,	7,	0,	0,	"VPEXTRWmr", 0|(1<<TID::UnmodeledSideEffects), 0x115c02e44ULL, NULL, NULL, NULL, OperandInfo108 },  // Inst #3268 = VPEXTRWmr
  { 3269,	3,	1,	0,	"VPEXTRWri", 0, 0x1c5c02045ULL, NULL, NULL, NULL, OperandInfo109 },  // Inst #3269 = VPEXTRWri
  { 3270,	7,	1,	0,	"VPHADDDrm128", 0|(1<<TID::MayLoad), 0x502c02d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3270 = VPHADDDrm128
  { 3271,	3,	1,	0,	"VPHADDDrr128", 0, 0x502c02d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3271 = VPHADDDrr128
  { 3272,	7,	1,	0,	"VPHADDSWrm128", 0|(1<<TID::MayLoad), 0x503c02d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3272 = VPHADDSWrm128
  { 3273,	3,	1,	0,	"VPHADDSWrr128", 0, 0x503c02d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3273 = VPHADDSWrr128
  { 3274,	7,	1,	0,	"VPHADDWrm128", 0|(1<<TID::MayLoad), 0x501c02d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3274 = VPHADDWrm128
  { 3275,	3,	1,	0,	"VPHADDWrr128", 0, 0x501c02d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3275 = VPHADDWrr128
  { 3276,	6,	1,	0,	"VPHMINPOSUWrm128", 0|(1<<TID::MayLoad), 0x141c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3276 = VPHMINPOSUWrm128
  { 3277,	2,	1,	0,	"VPHMINPOSUWrr128", 0, 0x141c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3277 = VPHMINPOSUWrr128
  { 3278,	7,	1,	0,	"VPHSUBDrm128", 0|(1<<TID::MayLoad), 0x506c02d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3278 = VPHSUBDrm128
  { 3279,	3,	1,	0,	"VPHSUBDrr128", 0, 0x506c02d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3279 = VPHSUBDrr128
  { 3280,	7,	1,	0,	"VPHSUBSWrm128", 0|(1<<TID::MayLoad), 0x507c02d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3280 = VPHSUBSWrm128
  { 3281,	3,	1,	0,	"VPHSUBSWrr128", 0, 0x507c02d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3281 = VPHSUBSWrr128
  { 3282,	7,	1,	0,	"VPHSUBWrm128", 0|(1<<TID::MayLoad), 0x505c02d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3282 = VPHSUBWrm128
  { 3283,	3,	1,	0,	"VPHSUBWrr128", 0, 0x505c02d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3283 = VPHSUBWrr128
  { 3284,	8,	1,	0,	"VPINSRBrm", 0|(1<<TID::MayLoad), 0x520c02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #3284 = VPINSRBrm
  { 3285,	4,	1,	0,	"VPINSRBrr", 0, 0x520c02e45ULL, NULL, NULL, NULL, OperandInfo263 },  // Inst #3285 = VPINSRBrr
  { 3286,	8,	1,	0,	"VPINSRDrm", 0|(1<<TID::MayLoad), 0x522c02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #3286 = VPINSRDrm
  { 3287,	4,	1,	0,	"VPINSRDrr", 0, 0x522c02e45ULL, NULL, NULL, NULL, OperandInfo263 },  // Inst #3287 = VPINSRDrr
  { 3288,	8,	1,	0,	"VPINSRQrm", 0|(1<<TID::MayLoad), 0x722c02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #3288 = VPINSRQrm
  { 3289,	4,	1,	0,	"VPINSRQrr", 0, 0x722c02e45ULL, NULL, NULL, NULL, OperandInfo264 },  // Inst #3289 = VPINSRQrr
  { 3290,	8,	1,	0,	"VPINSRWrmi", 0|(1<<TID::MayLoad), 0x5c4c02046ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #3290 = VPINSRWrmi
  { 3291,	4,	1,	0,	"VPINSRWrr64i", 0|(1<<TID::UnmodeledSideEffects), 0x5c4c02045ULL, NULL, NULL, NULL, OperandInfo264 },  // Inst #3291 = VPINSRWrr64i
  { 3292,	4,	1,	0,	"VPINSRWrri", 0, 0x5c4c02045ULL, NULL, NULL, NULL, OperandInfo263 },  // Inst #3292 = VPINSRWrri
  { 3293,	7,	1,	0,	"VPMADDUBSWrm128", 0|(1<<TID::MayLoad), 0x504c02d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3293 = VPMADDUBSWrm128
  { 3294,	3,	1,	0,	"VPMADDUBSWrr128", 0, 0x504c02d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3294 = VPMADDUBSWrr128
  { 3295,	7,	1,	0,	"VPMADDWDrm", 0|(1<<TID::MayLoad), 0x5f5c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3295 = VPMADDWDrm
  { 3296,	3,	1,	0,	"VPMADDWDrr", 0|(1<<TID::Commutable), 0x5f5c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3296 = VPMADDWDrr
  { 3297,	7,	1,	0,	"VPMAXSBrm", 0|(1<<TID::MayLoad), 0x53cc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3297 = VPMAXSBrm
  { 3298,	3,	1,	0,	"VPMAXSBrr", 0|(1<<TID::Commutable), 0x53cc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3298 = VPMAXSBrr
  { 3299,	7,	1,	0,	"VPMAXSDrm", 0|(1<<TID::MayLoad), 0x53dc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3299 = VPMAXSDrm
  { 3300,	3,	1,	0,	"VPMAXSDrr", 0|(1<<TID::Commutable), 0x53dc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3300 = VPMAXSDrr
  { 3301,	7,	1,	0,	"VPMAXSWrm", 0|(1<<TID::MayLoad), 0x5eec00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3301 = VPMAXSWrm
  { 3302,	3,	1,	0,	"VPMAXSWrr", 0|(1<<TID::Commutable), 0x5eec00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3302 = VPMAXSWrr
  { 3303,	7,	1,	0,	"VPMAXUBrm", 0|(1<<TID::MayLoad), 0x5dec00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3303 = VPMAXUBrm
  { 3304,	3,	1,	0,	"VPMAXUBrr", 0|(1<<TID::Commutable), 0x5dec00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3304 = VPMAXUBrr
  { 3305,	7,	1,	0,	"VPMAXUDrm", 0|(1<<TID::MayLoad), 0x53fc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3305 = VPMAXUDrm
  { 3306,	3,	1,	0,	"VPMAXUDrr", 0|(1<<TID::Commutable), 0x53fc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3306 = VPMAXUDrr
  { 3307,	7,	1,	0,	"VPMAXUWrm", 0|(1<<TID::MayLoad), 0x53ec00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3307 = VPMAXUWrm
  { 3308,	3,	1,	0,	"VPMAXUWrr", 0|(1<<TID::Commutable), 0x53ec00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3308 = VPMAXUWrr
  { 3309,	7,	1,	0,	"VPMINSBrm", 0|(1<<TID::MayLoad), 0x538c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3309 = VPMINSBrm
  { 3310,	3,	1,	0,	"VPMINSBrr", 0|(1<<TID::Commutable), 0x538c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3310 = VPMINSBrr
  { 3311,	7,	1,	0,	"VPMINSDrm", 0|(1<<TID::MayLoad), 0x539c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3311 = VPMINSDrm
  { 3312,	3,	1,	0,	"VPMINSDrr", 0|(1<<TID::Commutable), 0x539c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3312 = VPMINSDrr
  { 3313,	7,	1,	0,	"VPMINSWrm", 0|(1<<TID::MayLoad), 0x5eac00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3313 = VPMINSWrm
  { 3314,	3,	1,	0,	"VPMINSWrr", 0|(1<<TID::Commutable), 0x5eac00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3314 = VPMINSWrr
  { 3315,	7,	1,	0,	"VPMINUBrm", 0|(1<<TID::MayLoad), 0x5dac00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3315 = VPMINUBrm
  { 3316,	3,	1,	0,	"VPMINUBrr", 0|(1<<TID::Commutable), 0x5dac00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3316 = VPMINUBrr
  { 3317,	7,	1,	0,	"VPMINUDrm", 0|(1<<TID::MayLoad), 0x53bc00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3317 = VPMINUDrm
  { 3318,	3,	1,	0,	"VPMINUDrr", 0|(1<<TID::Commutable), 0x53bc00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3318 = VPMINUDrr
  { 3319,	7,	1,	0,	"VPMINUWrm", 0|(1<<TID::MayLoad), 0x53ac00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3319 = VPMINUWrm
  { 3320,	3,	1,	0,	"VPMINUWrr", 0|(1<<TID::Commutable), 0x53ac00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3320 = VPMINUWrr
  { 3321,	2,	1,	0,	"VPMOVMSKBr64r", 0|(1<<TID::UnmodeledSideEffects), 0x1d7c00045ULL, NULL, NULL, NULL, OperandInfo91 },  // Inst #3321 = VPMOVMSKBr64r
  { 3322,	2,	1,	0,	"VPMOVMSKBrr", 0, 0x1d7c00045ULL, NULL, NULL, NULL, OperandInfo133 },  // Inst #3322 = VPMOVMSKBrr
  { 3323,	6,	1,	0,	"VPMOVSXBDrm", 0|(1<<TID::MayLoad), 0x121c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3323 = VPMOVSXBDrm
  { 3324,	2,	1,	0,	"VPMOVSXBDrr", 0, 0x121c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3324 = VPMOVSXBDrr
  { 3325,	6,	1,	0,	"VPMOVSXBQrm", 0|(1<<TID::MayLoad), 0x122c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3325 = VPMOVSXBQrm
  { 3326,	2,	1,	0,	"VPMOVSXBQrr", 0, 0x122c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3326 = VPMOVSXBQrr
  { 3327,	6,	1,	0,	"VPMOVSXBWrm", 0|(1<<TID::MayLoad), 0x120c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3327 = VPMOVSXBWrm
  { 3328,	2,	1,	0,	"VPMOVSXBWrr", 0, 0x120c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3328 = VPMOVSXBWrr
  { 3329,	6,	1,	0,	"VPMOVSXDQrm", 0|(1<<TID::MayLoad), 0x125c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3329 = VPMOVSXDQrm
  { 3330,	2,	1,	0,	"VPMOVSXDQrr", 0, 0x125c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3330 = VPMOVSXDQrr
  { 3331,	6,	1,	0,	"VPMOVSXWDrm", 0|(1<<TID::MayLoad), 0x123c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3331 = VPMOVSXWDrm
  { 3332,	2,	1,	0,	"VPMOVSXWDrr", 0, 0x123c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3332 = VPMOVSXWDrr
  { 3333,	6,	1,	0,	"VPMOVSXWQrm", 0|(1<<TID::MayLoad), 0x124c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3333 = VPMOVSXWQrm
  { 3334,	2,	1,	0,	"VPMOVSXWQrr", 0, 0x124c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3334 = VPMOVSXWQrr
  { 3335,	6,	1,	0,	"VPMOVZXBDrm", 0|(1<<TID::MayLoad), 0x131c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3335 = VPMOVZXBDrm
  { 3336,	2,	1,	0,	"VPMOVZXBDrr", 0, 0x131c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3336 = VPMOVZXBDrr
  { 3337,	6,	1,	0,	"VPMOVZXBQrm", 0|(1<<TID::MayLoad), 0x132c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3337 = VPMOVZXBQrm
  { 3338,	2,	1,	0,	"VPMOVZXBQrr", 0, 0x132c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3338 = VPMOVZXBQrr
  { 3339,	6,	1,	0,	"VPMOVZXBWrm", 0|(1<<TID::MayLoad), 0x130c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3339 = VPMOVZXBWrm
  { 3340,	2,	1,	0,	"VPMOVZXBWrr", 0, 0x130c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3340 = VPMOVZXBWrr
  { 3341,	6,	1,	0,	"VPMOVZXDQrm", 0|(1<<TID::MayLoad), 0x135c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3341 = VPMOVZXDQrm
  { 3342,	2,	1,	0,	"VPMOVZXDQrr", 0, 0x135c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3342 = VPMOVZXDQrr
  { 3343,	6,	1,	0,	"VPMOVZXWDrm", 0|(1<<TID::MayLoad), 0x133c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3343 = VPMOVZXWDrm
  { 3344,	2,	1,	0,	"VPMOVZXWDrr", 0, 0x133c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3344 = VPMOVZXWDrr
  { 3345,	6,	1,	0,	"VPMOVZXWQrm", 0|(1<<TID::MayLoad), 0x134c00d46ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3345 = VPMOVZXWQrm
  { 3346,	2,	1,	0,	"VPMOVZXWQrr", 0, 0x134c00d45ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3346 = VPMOVZXWQrr
  { 3347,	7,	1,	0,	"VPMULDQrm", 0|(1<<TID::MayLoad), 0x528c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3347 = VPMULDQrm
  { 3348,	3,	1,	0,	"VPMULDQrr", 0|(1<<TID::Commutable), 0x528c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3348 = VPMULDQrr
  { 3349,	7,	1,	0,	"VPMULHRSWrm128", 0|(1<<TID::MayLoad), 0x50bc02d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3349 = VPMULHRSWrm128
  { 3350,	3,	1,	0,	"VPMULHRSWrr128", 0|(1<<TID::Commutable), 0x50bc02d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3350 = VPMULHRSWrr128
  { 3351,	7,	1,	0,	"VPMULHUWrm", 0|(1<<TID::MayLoad), 0x5e4c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3351 = VPMULHUWrm
  { 3352,	3,	1,	0,	"VPMULHUWrr", 0|(1<<TID::Commutable), 0x5e4c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3352 = VPMULHUWrr
  { 3353,	7,	1,	0,	"VPMULHWrm", 0|(1<<TID::MayLoad), 0x5e5c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3353 = VPMULHWrm
  { 3354,	3,	1,	0,	"VPMULHWrr", 0|(1<<TID::Commutable), 0x5e5c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3354 = VPMULHWrr
  { 3355,	7,	1,	0,	"VPMULLDrm", 0|(1<<TID::MayLoad), 0x540c00d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3355 = VPMULLDrm
  { 3356,	3,	1,	0,	"VPMULLDrr", 0|(1<<TID::Commutable), 0x540c00d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3356 = VPMULLDrr
  { 3357,	7,	1,	0,	"VPMULLWrm", 0|(1<<TID::MayLoad), 0x5d5c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3357 = VPMULLWrm
  { 3358,	3,	1,	0,	"VPMULLWrr", 0|(1<<TID::Commutable), 0x5d5c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3358 = VPMULLWrr
  { 3359,	7,	1,	0,	"VPMULUDQrm", 0|(1<<TID::MayLoad), 0x5f4c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3359 = VPMULUDQrm
  { 3360,	3,	1,	0,	"VPMULUDQrr", 0|(1<<TID::Commutable), 0x5f4c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3360 = VPMULUDQrr
  { 3361,	7,	1,	0,	"VPORrm", 0|(1<<TID::MayLoad), 0x5ebc00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3361 = VPORrm
  { 3362,	3,	1,	0,	"VPORrr", 0|(1<<TID::Commutable), 0x5ebc00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3362 = VPORrr
  { 3363,	7,	1,	0,	"VPSADBWrm", 0|(1<<TID::MayLoad), 0x5f6c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3363 = VPSADBWrm
  { 3364,	3,	1,	0,	"VPSADBWrr", 0|(1<<TID::Commutable), 0x5f6c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3364 = VPSADBWrr
  { 3365,	7,	1,	0,	"VPSHUFBrm128", 0|(1<<TID::MayLoad), 0x500c02d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3365 = VPSHUFBrm128
  { 3366,	3,	1,	0,	"VPSHUFBrr128", 0, 0x500c02d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3366 = VPSHUFBrr128
  { 3367,	7,	1,	0,	"VPSHUFDmi", 0|(1<<TID::MayLoad), 0x170c02046ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #3367 = VPSHUFDmi
  { 3368,	3,	1,	0,	"VPSHUFDri", 0, 0x170c02045ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3368 = VPSHUFDri
  { 3369,	7,	1,	0,	"VPSHUFHWmi", 0|(1<<TID::MayLoad), 0x170c02c06ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #3369 = VPSHUFHWmi
  { 3370,	3,	1,	0,	"VPSHUFHWri", 0, 0x170c02c05ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3370 = VPSHUFHWri
  { 3371,	7,	1,	0,	"VPSHUFLWmi", 0|(1<<TID::MayLoad), 0x170c02b06ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #3371 = VPSHUFLWmi
  { 3372,	3,	1,	0,	"VPSHUFLWri", 0, 0x170c02b05ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3372 = VPSHUFLWri
  { 3373,	7,	1,	0,	"VPSIGNBrm128", 0|(1<<TID::MayLoad), 0x508c02d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3373 = VPSIGNBrm128
  { 3374,	3,	1,	0,	"VPSIGNBrr128", 0, 0x508c02d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3374 = VPSIGNBrr128
  { 3375,	7,	1,	0,	"VPSIGNDrm128", 0|(1<<TID::MayLoad), 0x50ac02d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3375 = VPSIGNDrm128
  { 3376,	3,	1,	0,	"VPSIGNDrr128", 0, 0x50ac02d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3376 = VPSIGNDrr128
  { 3377,	7,	1,	0,	"VPSIGNWrm128", 0|(1<<TID::MayLoad), 0x509c02d46ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3377 = VPSIGNWrm128
  { 3378,	3,	1,	0,	"VPSIGNWrr128", 0, 0x509c02d45ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3378 = VPSIGNWrr128
  { 3379,	3,	1,	0,	"VPSLLDQri", 0, 0x573c02157ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3379 = VPSLLDQri
  { 3380,	3,	1,	0,	"VPSLLDri", 0, 0x572c02156ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3380 = VPSLLDri
  { 3381,	7,	1,	0,	"VPSLLDrm", 0|(1<<TID::MayLoad), 0x5f2c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3381 = VPSLLDrm
  { 3382,	3,	1,	0,	"VPSLLDrr", 0, 0x5f2c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3382 = VPSLLDrr
  { 3383,	3,	1,	0,	"VPSLLQri", 0, 0x573c02156ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3383 = VPSLLQri
  { 3384,	7,	1,	0,	"VPSLLQrm", 0|(1<<TID::MayLoad), 0x5f3c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3384 = VPSLLQrm
  { 3385,	3,	1,	0,	"VPSLLQrr", 0, 0x5f3c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3385 = VPSLLQrr
  { 3386,	3,	1,	0,	"VPSLLWri", 0, 0x571c02156ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3386 = VPSLLWri
  { 3387,	7,	1,	0,	"VPSLLWrm", 0|(1<<TID::MayLoad), 0x5f1c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3387 = VPSLLWrm
  { 3388,	3,	1,	0,	"VPSLLWrr", 0, 0x5f1c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3388 = VPSLLWrr
  { 3389,	3,	1,	0,	"VPSRADri", 0, 0x572c02154ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3389 = VPSRADri
  { 3390,	7,	1,	0,	"VPSRADrm", 0|(1<<TID::MayLoad), 0x5e2c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3390 = VPSRADrm
  { 3391,	3,	1,	0,	"VPSRADrr", 0, 0x5e2c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3391 = VPSRADrr
  { 3392,	3,	1,	0,	"VPSRAWri", 0, 0x571c02154ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3392 = VPSRAWri
  { 3393,	7,	1,	0,	"VPSRAWrm", 0|(1<<TID::MayLoad), 0x5e1c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3393 = VPSRAWrm
  { 3394,	3,	1,	0,	"VPSRAWrr", 0, 0x5e1c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3394 = VPSRAWrr
  { 3395,	3,	1,	0,	"VPSRLDQri", 0, 0x573c02153ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3395 = VPSRLDQri
  { 3396,	3,	1,	0,	"VPSRLDri", 0, 0x572c02152ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3396 = VPSRLDri
  { 3397,	7,	1,	0,	"VPSRLDrm", 0|(1<<TID::MayLoad), 0x5d2c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3397 = VPSRLDrm
  { 3398,	3,	1,	0,	"VPSRLDrr", 0, 0x5d2c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3398 = VPSRLDrr
  { 3399,	3,	1,	0,	"VPSRLQri", 0, 0x573c02152ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3399 = VPSRLQri
  { 3400,	7,	1,	0,	"VPSRLQrm", 0|(1<<TID::MayLoad), 0x5d3c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3400 = VPSRLQrm
  { 3401,	3,	1,	0,	"VPSRLQrr", 0, 0x5d3c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3401 = VPSRLQrr
  { 3402,	3,	1,	0,	"VPSRLWri", 0, 0x571c02152ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3402 = VPSRLWri
  { 3403,	7,	1,	0,	"VPSRLWrm", 0|(1<<TID::MayLoad), 0x5d1c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3403 = VPSRLWrm
  { 3404,	3,	1,	0,	"VPSRLWrr", 0, 0x5d1c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3404 = VPSRLWrr
  { 3405,	7,	1,	0,	"VPSUBBrm", 0|(1<<TID::MayLoad), 0x5f8c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3405 = VPSUBBrm
  { 3406,	3,	1,	0,	"VPSUBBrr", 0, 0x5f8c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3406 = VPSUBBrr
  { 3407,	7,	1,	0,	"VPSUBDrm", 0|(1<<TID::MayLoad), 0x5fac00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3407 = VPSUBDrm
  { 3408,	3,	1,	0,	"VPSUBDrr", 0, 0x5fac00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3408 = VPSUBDrr
  { 3409,	7,	1,	0,	"VPSUBQrm", 0|(1<<TID::MayLoad), 0x5fbc00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3409 = VPSUBQrm
  { 3410,	3,	1,	0,	"VPSUBQrr", 0, 0x5fbc00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3410 = VPSUBQrr
  { 3411,	7,	1,	0,	"VPSUBSBrm", 0|(1<<TID::MayLoad), 0x5e8c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3411 = VPSUBSBrm
  { 3412,	3,	1,	0,	"VPSUBSBrr", 0, 0x5e8c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3412 = VPSUBSBrr
  { 3413,	7,	1,	0,	"VPSUBSWrm", 0|(1<<TID::MayLoad), 0x5e9c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3413 = VPSUBSWrm
  { 3414,	3,	1,	0,	"VPSUBSWrr", 0, 0x5e9c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3414 = VPSUBSWrr
  { 3415,	7,	1,	0,	"VPSUBUSBrm", 0|(1<<TID::MayLoad), 0x5d8c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3415 = VPSUBUSBrm
  { 3416,	3,	1,	0,	"VPSUBUSBrr", 0, 0x5d8c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3416 = VPSUBUSBrr
  { 3417,	7,	1,	0,	"VPSUBUSWrm", 0|(1<<TID::MayLoad), 0x5d9c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3417 = VPSUBUSWrm
  { 3418,	3,	1,	0,	"VPSUBUSWrr", 0, 0x5d9c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3418 = VPSUBUSWrr
  { 3419,	7,	1,	0,	"VPSUBWrm", 0|(1<<TID::MayLoad), 0x5f9c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3419 = VPSUBWrm
  { 3420,	3,	1,	0,	"VPSUBWrr", 0, 0x5f9c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3420 = VPSUBWrr
  { 3421,	6,	0,	0,	"VPTESTYrm", 0|(1<<TID::MayLoad), 0x117c00d46ULL, NULL, ImplicitList1, Barriers1, OperandInfo237 },  // Inst #3421 = VPTESTYrm
  { 3422,	2,	0,	0,	"VPTESTYrr", 0, 0x117c00d45ULL, NULL, ImplicitList1, Barriers1, OperandInfo241 },  // Inst #3422 = VPTESTYrr
  { 3423,	6,	0,	0,	"VPTESTrm", 0|(1<<TID::MayLoad), 0x117c00d46ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #3423 = VPTESTrm
  { 3424,	2,	0,	0,	"VPTESTrr", 0, 0x117c00d45ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #3424 = VPTESTrr
  { 3425,	7,	1,	0,	"VPUNPCKHBWrm", 0|(1<<TID::MayLoad), 0x568c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3425 = VPUNPCKHBWrm
  { 3426,	3,	1,	0,	"VPUNPCKHBWrr", 0, 0x568c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3426 = VPUNPCKHBWrr
  { 3427,	7,	1,	0,	"VPUNPCKHDQrm", 0|(1<<TID::MayLoad), 0x56ac00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3427 = VPUNPCKHDQrm
  { 3428,	3,	1,	0,	"VPUNPCKHDQrr", 0, 0x56ac00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3428 = VPUNPCKHDQrr
  { 3429,	7,	1,	0,	"VPUNPCKHQDQrm", 0|(1<<TID::MayLoad), 0x56dc00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3429 = VPUNPCKHQDQrm
  { 3430,	3,	1,	0,	"VPUNPCKHQDQrr", 0, 0x56dc00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3430 = VPUNPCKHQDQrr
  { 3431,	7,	1,	0,	"VPUNPCKHWDrm", 0|(1<<TID::MayLoad), 0x569c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3431 = VPUNPCKHWDrm
  { 3432,	3,	1,	0,	"VPUNPCKHWDrr", 0, 0x569c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3432 = VPUNPCKHWDrr
  { 3433,	7,	1,	0,	"VPUNPCKLBWrm", 0|(1<<TID::MayLoad), 0x560c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3433 = VPUNPCKLBWrm
  { 3434,	3,	1,	0,	"VPUNPCKLBWrr", 0, 0x560c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3434 = VPUNPCKLBWrr
  { 3435,	7,	1,	0,	"VPUNPCKLDQrm", 0|(1<<TID::MayLoad), 0x562c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3435 = VPUNPCKLDQrm
  { 3436,	3,	1,	0,	"VPUNPCKLDQrr", 0, 0x562c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3436 = VPUNPCKLDQrr
  { 3437,	7,	1,	0,	"VPUNPCKLQDQrm", 0|(1<<TID::MayLoad), 0x56cc00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3437 = VPUNPCKLQDQrm
  { 3438,	3,	1,	0,	"VPUNPCKLQDQrr", 0, 0x56cc00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3438 = VPUNPCKLQDQrr
  { 3439,	7,	1,	0,	"VPUNPCKLWDrm", 0|(1<<TID::MayLoad), 0x561c00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3439 = VPUNPCKLWDrm
  { 3440,	3,	1,	0,	"VPUNPCKLWDrr", 0, 0x561c00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3440 = VPUNPCKLWDrr
  { 3441,	7,	1,	0,	"VPXORrm", 0|(1<<TID::MayLoad), 0x5efc00146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3441 = VPXORrm
  { 3442,	3,	1,	0,	"VPXORrr", 0|(1<<TID::Commutable), 0x5efc00145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3442 = VPXORrr
  { 3443,	6,	1,	0,	"VRCPPSYm", 0|(1<<TID::MayLoad), 0x153400106ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3443 = VRCPPSYm
  { 3444,	6,	1,	0,	"VRCPPSYm_Int", 0|(1<<TID::MayLoad), 0x153400106ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3444 = VRCPPSYm_Int
  { 3445,	2,	1,	0,	"VRCPPSYr", 0, 0x153400105ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3445 = VRCPPSYr
  { 3446,	2,	1,	0,	"VRCPPSYr_Int", 0, 0x153400105ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3446 = VRCPPSYr_Int
  { 3447,	6,	1,	0,	"VRCPPSm", 0|(1<<TID::MayLoad), 0x153400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3447 = VRCPPSm
  { 3448,	6,	1,	0,	"VRCPPSm_Int", 0|(1<<TID::MayLoad), 0x153400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3448 = VRCPPSm_Int
  { 3449,	2,	1,	0,	"VRCPPSr", 0, 0x153400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3449 = VRCPPSr
  { 3450,	2,	1,	0,	"VRCPPSr_Int", 0, 0x153400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3450 = VRCPPSr_Int
  { 3451,	7,	1,	0,	"VRCPSSm", 0|(1<<TID::UnmodeledSideEffects), 0x553000c06ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #3451 = VRCPSSm
  { 3452,	6,	1,	0,	"VRCPSSm_Int", 0|(1<<TID::MayLoad), 0x553000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3452 = VRCPSSm_Int
  { 3453,	3,	1,	0,	"VRCPSSr", 0|(1<<TID::UnmodeledSideEffects), 0x553000c05ULL, NULL, NULL, NULL, OperandInfo229 },  // Inst #3453 = VRCPSSr
  { 3454,	2,	1,	0,	"VRCPSSr_Int", 0, 0x553000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3454 = VRCPSSr_Int
  { 3455,	7,	1,	0,	"VROUNDPDm", 0|(1<<TID::UnmodeledSideEffects), 0x109c02e46ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #3455 = VROUNDPDm
  { 3456,	7,	1,	0,	"VROUNDPDm_Int", 0|(1<<TID::MayLoad), 0x109c02e46ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #3456 = VROUNDPDm_Int
  { 3457,	3,	1,	0,	"VROUNDPDr", 0|(1<<TID::UnmodeledSideEffects), 0x109c02e45ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3457 = VROUNDPDr
  { 3458,	3,	1,	0,	"VROUNDPDr_Int", 0, 0x109c02e45ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3458 = VROUNDPDr_Int
  { 3459,	7,	1,	0,	"VROUNDPSm", 0|(1<<TID::UnmodeledSideEffects), 0x108002e46ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #3459 = VROUNDPSm
  { 3460,	7,	1,	0,	"VROUNDPSm_Int", 0|(1<<TID::MayLoad), 0x108002e46ULL, NULL, NULL, NULL, OperandInfo44 },  // Inst #3460 = VROUNDPSm_Int
  { 3461,	3,	1,	0,	"VROUNDPSr", 0|(1<<TID::UnmodeledSideEffects), 0x108c02e45ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3461 = VROUNDPSr
  { 3462,	3,	1,	0,	"VROUNDPSr_Int", 0, 0x108c02e45ULL, NULL, NULL, NULL, OperandInfo45 },  // Inst #3462 = VROUNDPSr_Int
  { 3463,	8,	1,	0,	"VROUNDSDm", 0|(1<<TID::UnmodeledSideEffects), 0x50bc02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #3463 = VROUNDSDm
  { 3464,	8,	1,	0,	"VROUNDSDm_Int", 0|(1<<TID::MayLoad), 0x50bc02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #3464 = VROUNDSDm_Int
  { 3465,	4,	1,	0,	"VROUNDSDr", 0|(1<<TID::UnmodeledSideEffects), 0x50bc02e45ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #3465 = VROUNDSDr
  { 3466,	4,	1,	0,	"VROUNDSDr_Int", 0, 0x50bc02e45ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #3466 = VROUNDSDr_Int
  { 3467,	8,	1,	0,	"VROUNDSSm", 0|(1<<TID::UnmodeledSideEffects), 0x50ac02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #3467 = VROUNDSSm
  { 3468,	8,	1,	0,	"VROUNDSSm_Int", 0|(1<<TID::MayLoad), 0x50ac02e46ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #3468 = VROUNDSSm_Int
  { 3469,	4,	1,	0,	"VROUNDSSr", 0|(1<<TID::UnmodeledSideEffects), 0x50ac02e45ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #3469 = VROUNDSSr
  { 3470,	4,	1,	0,	"VROUNDSSr_Int", 0, 0x50ac02e45ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #3470 = VROUNDSSr_Int
  { 3471,	7,	1,	0,	"VROUNDYPDm", 0|(1<<TID::UnmodeledSideEffects), 0x109c02e46ULL, NULL, NULL, NULL, OperandInfo261 },  // Inst #3471 = VROUNDYPDm
  { 3472,	7,	1,	0,	"VROUNDYPDm_Int", 0|(1<<TID::MayLoad), 0x109c02e46ULL, NULL, NULL, NULL, OperandInfo261 },  // Inst #3472 = VROUNDYPDm_Int
  { 3473,	3,	1,	0,	"VROUNDYPDr", 0|(1<<TID::UnmodeledSideEffects), 0x109c02e45ULL, NULL, NULL, NULL, OperandInfo262 },  // Inst #3473 = VROUNDYPDr
  { 3474,	3,	1,	0,	"VROUNDYPDr_Int", 0, 0x109c02e45ULL, NULL, NULL, NULL, OperandInfo262 },  // Inst #3474 = VROUNDYPDr_Int
  { 3475,	7,	1,	0,	"VROUNDYPSm", 0|(1<<TID::UnmodeledSideEffects), 0x108002e46ULL, NULL, NULL, NULL, OperandInfo261 },  // Inst #3475 = VROUNDYPSm
  { 3476,	7,	1,	0,	"VROUNDYPSm_Int", 0|(1<<TID::MayLoad), 0x108002e46ULL, NULL, NULL, NULL, OperandInfo261 },  // Inst #3476 = VROUNDYPSm_Int
  { 3477,	3,	1,	0,	"VROUNDYPSr", 0|(1<<TID::UnmodeledSideEffects), 0x108c02e45ULL, NULL, NULL, NULL, OperandInfo262 },  // Inst #3477 = VROUNDYPSr
  { 3478,	3,	1,	0,	"VROUNDYPSr_Int", 0, 0x108c02e45ULL, NULL, NULL, NULL, OperandInfo262 },  // Inst #3478 = VROUNDYPSr_Int
  { 3479,	6,	1,	0,	"VRSQRTPSYm", 0|(1<<TID::MayLoad), 0x152400106ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3479 = VRSQRTPSYm
  { 3480,	6,	1,	0,	"VRSQRTPSYm_Int", 0|(1<<TID::MayLoad), 0x152400106ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3480 = VRSQRTPSYm_Int
  { 3481,	2,	1,	0,	"VRSQRTPSYr", 0, 0x152400105ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3481 = VRSQRTPSYr
  { 3482,	2,	1,	0,	"VRSQRTPSYr_Int", 0, 0x152400105ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3482 = VRSQRTPSYr_Int
  { 3483,	6,	1,	0,	"VRSQRTPSm", 0|(1<<TID::MayLoad), 0x152400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3483 = VRSQRTPSm
  { 3484,	6,	1,	0,	"VRSQRTPSm_Int", 0|(1<<TID::MayLoad), 0x152400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3484 = VRSQRTPSm_Int
  { 3485,	2,	1,	0,	"VRSQRTPSr", 0, 0x152400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3485 = VRSQRTPSr
  { 3486,	2,	1,	0,	"VRSQRTPSr_Int", 0, 0x152400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3486 = VRSQRTPSr_Int
  { 3487,	7,	1,	0,	"VRSQRTSSm", 0|(1<<TID::UnmodeledSideEffects), 0x552000c06ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #3487 = VRSQRTSSm
  { 3488,	6,	1,	0,	"VRSQRTSSm_Int", 0|(1<<TID::MayLoad), 0x552000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3488 = VRSQRTSSm_Int
  { 3489,	3,	1,	0,	"VRSQRTSSr", 0|(1<<TID::UnmodeledSideEffects), 0x552000c05ULL, NULL, NULL, NULL, OperandInfo229 },  // Inst #3489 = VRSQRTSSr
  { 3490,	2,	1,	0,	"VRSQRTSSr_Int", 0, 0x552000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3490 = VRSQRTSSr_Int
  { 3491,	8,	1,	0,	"VSHUFPDYrmi", 0|(1<<TID::MayLoad), 0x5c6802046ULL, NULL, NULL, NULL, OperandInfo231 },  // Inst #3491 = VSHUFPDYrmi
  { 3492,	4,	1,	0,	"VSHUFPDYrri", 0, 0x5c6802045ULL, NULL, NULL, NULL, OperandInfo232 },  // Inst #3492 = VSHUFPDYrri
  { 3493,	8,	1,	0,	"VSHUFPDrmi", 0|(1<<TID::MayLoad), 0x5c6802046ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #3493 = VSHUFPDrmi
  { 3494,	4,	1,	0,	"VSHUFPDrri", 0, 0x5c6802045ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #3494 = VSHUFPDrri
  { 3495,	8,	1,	0,	"VSHUFPSYrmi", 0|(1<<TID::MayLoad), 0x5c6402006ULL, NULL, NULL, NULL, OperandInfo231 },  // Inst #3495 = VSHUFPSYrmi
  { 3496,	4,	1,	0,	"VSHUFPSYrri", 0, 0x5c6402005ULL, NULL, NULL, NULL, OperandInfo232 },  // Inst #3496 = VSHUFPSYrri
  { 3497,	8,	1,	0,	"VSHUFPSrmi", 0|(1<<TID::MayLoad), 0x5c6402006ULL, NULL, NULL, NULL, OperandInfo136 },  // Inst #3497 = VSHUFPSrmi
  { 3498,	4,	1,	0,	"VSHUFPSrri", 0, 0x5c6402005ULL, NULL, NULL, NULL, OperandInfo80 },  // Inst #3498 = VSHUFPSrri
  { 3499,	6,	1,	0,	"VSQRTPDYm", 0|(1<<TID::MayLoad), 0x151800146ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3499 = VSQRTPDYm
  { 3500,	6,	1,	0,	"VSQRTPDYm_Int", 0|(1<<TID::MayLoad), 0x151800146ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3500 = VSQRTPDYm_Int
  { 3501,	2,	1,	0,	"VSQRTPDYr", 0, 0x151800145ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3501 = VSQRTPDYr
  { 3502,	2,	1,	0,	"VSQRTPDYr_Int", 0, 0x151800145ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3502 = VSQRTPDYr_Int
  { 3503,	6,	1,	0,	"VSQRTPDm", 0|(1<<TID::MayLoad), 0x151800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3503 = VSQRTPDm
  { 3504,	6,	1,	0,	"VSQRTPDm_Int", 0|(1<<TID::MayLoad), 0x151800146ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3504 = VSQRTPDm_Int
  { 3505,	2,	1,	0,	"VSQRTPDr", 0, 0x151800145ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3505 = VSQRTPDr
  { 3506,	2,	1,	0,	"VSQRTPDr_Int", 0, 0x151800145ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3506 = VSQRTPDr_Int
  { 3507,	6,	1,	0,	"VSQRTPSYm", 0|(1<<TID::MayLoad), 0x151400106ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3507 = VSQRTPSYm
  { 3508,	6,	1,	0,	"VSQRTPSYm_Int", 0|(1<<TID::MayLoad), 0x151400106ULL, NULL, NULL, NULL, OperandInfo237 },  // Inst #3508 = VSQRTPSYm_Int
  { 3509,	2,	1,	0,	"VSQRTPSYr", 0, 0x151400105ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3509 = VSQRTPSYr
  { 3510,	2,	1,	0,	"VSQRTPSYr_Int", 0, 0x151400105ULL, NULL, NULL, NULL, OperandInfo241 },  // Inst #3510 = VSQRTPSYr_Int
  { 3511,	6,	1,	0,	"VSQRTPSm", 0|(1<<TID::MayLoad), 0x151400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3511 = VSQRTPSm
  { 3512,	6,	1,	0,	"VSQRTPSm_Int", 0|(1<<TID::MayLoad), 0x151400106ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3512 = VSQRTPSm_Int
  { 3513,	2,	1,	0,	"VSQRTPSr", 0, 0x151400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3513 = VSQRTPSr
  { 3514,	2,	1,	0,	"VSQRTPSr_Int", 0, 0x151400105ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3514 = VSQRTPSr_Int
  { 3515,	7,	1,	0,	"VSQRTSDm", 0|(1<<TID::UnmodeledSideEffects), 0x551000b06ULL, NULL, NULL, NULL, OperandInfo226 },  // Inst #3515 = VSQRTSDm
  { 3516,	6,	1,	0,	"VSQRTSDm_Int", 0|(1<<TID::MayLoad), 0x551000b06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3516 = VSQRTSDm_Int
  { 3517,	3,	1,	0,	"VSQRTSDr", 0|(1<<TID::UnmodeledSideEffects), 0x551000b05ULL, NULL, NULL, NULL, OperandInfo227 },  // Inst #3517 = VSQRTSDr
  { 3518,	2,	1,	0,	"VSQRTSDr_Int", 0, 0x551000b05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3518 = VSQRTSDr_Int
  { 3519,	7,	1,	0,	"VSQRTSSm", 0|(1<<TID::UnmodeledSideEffects), 0x551000c06ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #3519 = VSQRTSSm
  { 3520,	6,	1,	0,	"VSQRTSSm_Int", 0|(1<<TID::MayLoad), 0x551000c06ULL, NULL, NULL, NULL, OperandInfo42 },  // Inst #3520 = VSQRTSSm_Int
  { 3521,	3,	1,	0,	"VSQRTSSr", 0|(1<<TID::UnmodeledSideEffects), 0x551000c05ULL, NULL, NULL, NULL, OperandInfo229 },  // Inst #3521 = VSQRTSSr
  { 3522,	2,	1,	0,	"VSQRTSSr_Int", 0, 0x551000c05ULL, NULL, NULL, NULL, OperandInfo43 },  // Inst #3522 = VSQRTSSr_Int
  { 3523,	5,	0,	0,	"VSTMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x1ae40001bULL, NULL, NULL, NULL, OperandInfo34 },  // Inst #3523 = VSTMXCSR
  { 3524,	7,	1,	0,	"VSUBPDYrm", 0|(1<<TID::MayLoad), 0x55c800146ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #3524 = VSUBPDYrm
  { 3525,	3,	1,	0,	"VSUBPDYrr", 0, 0x55c800145ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #3525 = VSUBPDYrr
  { 3526,	7,	1,	0,	"VSUBPDrm", 0|(1<<TID::MayLoad), 0x55c800146ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3526 = VSUBPDrm
  { 3527,	3,	1,	0,	"VSUBPDrr", 0, 0x55c800145ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3527 = VSUBPDrr
  { 3528,	7,	1,	0,	"VSUBPSYrm", 0|(1<<TID::MayLoad), 0x55c400106ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #3528 = VSUBPSYrm
  { 3529,	3,	1,	0,	"VSUBPSYrr", 0, 0x55c400105ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #3529 = VSUBPSYrr
  { 3530,	7,	1,	0,	"VSUBPSrm", 0|(1<<TID::MayLoad), 0x55c400106ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3530 = VSUBPSrm
  { 3531,	3,	1,	0,	"VSUBPSrr", 0, 0x55c400105ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3531 = VSUBPSrr
  { 3532,	7,	1,	0,	"VSUBSDrm", 0|(1<<TID::MayLoad), 0x55c000b06ULL, NULL, NULL, NULL, OperandInfo226 },  // Inst #3532 = VSUBSDrm
  { 3533,	7,	1,	0,	"VSUBSDrm_Int", 0|(1<<TID::MayLoad), 0x55c000b06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3533 = VSUBSDrm_Int
  { 3534,	3,	1,	0,	"VSUBSDrr", 0, 0x55c000b05ULL, NULL, NULL, NULL, OperandInfo227 },  // Inst #3534 = VSUBSDrr
  { 3535,	3,	1,	0,	"VSUBSDrr_Int", 0, 0x55c000b05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3535 = VSUBSDrr_Int
  { 3536,	7,	1,	0,	"VSUBSSrm", 0|(1<<TID::MayLoad), 0x55c000c06ULL, NULL, NULL, NULL, OperandInfo228 },  // Inst #3536 = VSUBSSrm
  { 3537,	7,	1,	0,	"VSUBSSrm_Int", 0|(1<<TID::MayLoad), 0x55c000c06ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3537 = VSUBSSrm_Int
  { 3538,	3,	1,	0,	"VSUBSSrr", 0, 0x55c000c05ULL, NULL, NULL, NULL, OperandInfo229 },  // Inst #3538 = VSUBSSrr
  { 3539,	3,	1,	0,	"VSUBSSrr_Int", 0, 0x55c000c05ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3539 = VSUBSSrr_Int
  { 3540,	6,	0,	0,	"VTESTPDYrm", 0|(1<<TID::MayLoad), 0x10fc00d46ULL, NULL, ImplicitList1, Barriers1, OperandInfo237 },  // Inst #3540 = VTESTPDYrm
  { 3541,	2,	0,	0,	"VTESTPDYrr", 0, 0x10fc00d45ULL, NULL, ImplicitList1, Barriers1, OperandInfo241 },  // Inst #3541 = VTESTPDYrr
  { 3542,	6,	0,	0,	"VTESTPDrm", 0|(1<<TID::MayLoad), 0x10fc00d46ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #3542 = VTESTPDrm
  { 3543,	2,	0,	0,	"VTESTPDrr", 0, 0x10fc00d45ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #3543 = VTESTPDrr
  { 3544,	6,	0,	0,	"VTESTPSYrm", 0|(1<<TID::MayLoad), 0x10ec00d46ULL, NULL, ImplicitList1, Barriers1, OperandInfo237 },  // Inst #3544 = VTESTPSYrm
  { 3545,	2,	0,	0,	"VTESTPSYrr", 0, 0x10ec00d45ULL, NULL, ImplicitList1, Barriers1, OperandInfo241 },  // Inst #3545 = VTESTPSYrr
  { 3546,	6,	0,	0,	"VTESTPSrm", 0|(1<<TID::MayLoad), 0x10ec00d46ULL, NULL, ImplicitList1, Barriers1, OperandInfo42 },  // Inst #3546 = VTESTPSrm
  { 3547,	2,	0,	0,	"VTESTPSrr", 0, 0x10ec00d45ULL, NULL, ImplicitList1, Barriers1, OperandInfo43 },  // Inst #3547 = VTESTPSrr
  { 3548,	6,	0,	0,	"VUCOMISDrm", 0|(1<<TID::MayLoad), 0x12e800046ULL, NULL, ImplicitList1, Barriers1, OperandInfo94 },  // Inst #3548 = VUCOMISDrm
  { 3549,	2,	0,	0,	"VUCOMISDrr", 0, 0x12e800045ULL, NULL, ImplicitList1, Barriers1, OperandInfo118 },  // Inst #3549 = VUCOMISDrr
  { 3550,	6,	0,	0,	"VUCOMISSrm", 0|(1<<TID::MayLoad), 0x12e400006ULL, NULL, ImplicitList1, Barriers1, OperandInfo92 },  // Inst #3550 = VUCOMISSrm
  { 3551,	2,	0,	0,	"VUCOMISSrr", 0, 0x12e400005ULL, NULL, ImplicitList1, Barriers1, OperandInfo119 },  // Inst #3551 = VUCOMISSrr
  { 3552,	7,	1,	0,	"VUNPCKHPDYrm", 0|(1<<TID::MayLoad), 0x515800046ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #3552 = VUNPCKHPDYrm
  { 3553,	3,	1,	0,	"VUNPCKHPDYrr", 0, 0x515800045ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #3553 = VUNPCKHPDYrr
  { 3554,	7,	1,	0,	"VUNPCKHPDrm", 0|(1<<TID::MayLoad), 0x515800046ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3554 = VUNPCKHPDrm
  { 3555,	3,	1,	0,	"VUNPCKHPDrr", 0, 0x515800045ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3555 = VUNPCKHPDrr
  { 3556,	7,	1,	0,	"VUNPCKHPSYrm", 0|(1<<TID::MayLoad), 0x515400006ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #3556 = VUNPCKHPSYrm
  { 3557,	3,	1,	0,	"VUNPCKHPSYrr", 0, 0x515400005ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #3557 = VUNPCKHPSYrr
  { 3558,	7,	1,	0,	"VUNPCKHPSrm", 0|(1<<TID::MayLoad), 0x515400006ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3558 = VUNPCKHPSrm
  { 3559,	3,	1,	0,	"VUNPCKHPSrr", 0, 0x515400005ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3559 = VUNPCKHPSrr
  { 3560,	7,	1,	0,	"VUNPCKLPDYrm", 0|(1<<TID::MayLoad), 0x514800046ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #3560 = VUNPCKLPDYrm
  { 3561,	3,	1,	0,	"VUNPCKLPDYrr", 0, 0x514800045ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #3561 = VUNPCKLPDYrr
  { 3562,	7,	1,	0,	"VUNPCKLPDrm", 0|(1<<TID::MayLoad), 0x514800046ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3562 = VUNPCKLPDrm
  { 3563,	3,	1,	0,	"VUNPCKLPDrr", 0, 0x514800045ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3563 = VUNPCKLPDrr
  { 3564,	7,	1,	0,	"VUNPCKLPSYrm", 0|(1<<TID::MayLoad), 0x514400006ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #3564 = VUNPCKLPSYrm
  { 3565,	3,	1,	0,	"VUNPCKLPSYrr", 0, 0x514400005ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #3565 = VUNPCKLPSYrr
  { 3566,	7,	1,	0,	"VUNPCKLPSrm", 0|(1<<TID::MayLoad), 0x514400006ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3566 = VUNPCKLPSrm
  { 3567,	3,	1,	0,	"VUNPCKLPSrr", 0, 0x514400005ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3567 = VUNPCKLPSrr
  { 3568,	7,	1,	0,	"VXORPDYrm", 0|(1<<TID::UnmodeledSideEffects), 0x557800046ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #3568 = VXORPDYrm
  { 3569,	3,	1,	0,	"VXORPDYrr", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0x557800045ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #3569 = VXORPDYrr
  { 3570,	7,	1,	0,	"VXORPDrm", 0|(1<<TID::UnmodeledSideEffects), 0x557800046ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3570 = VXORPDrm
  { 3571,	3,	1,	0,	"VXORPDrr", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0x557800045ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3571 = VXORPDrr
  { 3572,	7,	1,	0,	"VXORPSYrm", 0|(1<<TID::UnmodeledSideEffects), 0x557400006ULL, NULL, NULL, NULL, OperandInfo224 },  // Inst #3572 = VXORPSYrm
  { 3573,	3,	1,	0,	"VXORPSYrr", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0x557400005ULL, NULL, NULL, NULL, OperandInfo225 },  // Inst #3573 = VXORPSYrr
  { 3574,	7,	1,	0,	"VXORPSrm", 0|(1<<TID::UnmodeledSideEffects), 0x557400006ULL, NULL, NULL, NULL, OperandInfo137 },  // Inst #3574 = VXORPSrm
  { 3575,	3,	1,	0,	"VXORPSrr", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0x557400005ULL, NULL, NULL, NULL, OperandInfo138 },  // Inst #3575 = VXORPSrr
  { 3576,	0,	0,	0,	"VZEROALL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x1177000001ULL, NULL, NULL, NULL, 0 },  // Inst #3576 = VZEROALL
  { 3577,	0,	0,	0,	"VZEROUPPER", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x177000001ULL, NULL, NULL, NULL, 0 },  // Inst #3577 = VZEROUPPER
  { 3578,	1,	1,	0,	"V_SET0PD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0x57800160ULL, NULL, NULL, NULL, OperandInfo51 },  // Inst #3578 = V_SET0PD
  { 3579,	1,	1,	0,	"V_SET0PI", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0xefc00160ULL, NULL, NULL, NULL, OperandInfo51 },  // Inst #3579 = V_SET0PI
  { 3580,	1,	1,	0,	"V_SET0PS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0x57400120ULL, NULL, NULL, NULL, OperandInfo51 },  // Inst #3580 = V_SET0PS
  { 3581,	1,	1,	0,	"V_SETALLONES", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0x76c00160ULL, NULL, NULL, NULL, OperandInfo51 },  // Inst #3581 = V_SETALLONES
  { 3582,	0,	0,	0,	"WAIT", 0|(1<<TID::UnmodeledSideEffects), 0x9b000001ULL, NULL, NULL, NULL, 0 },  // Inst #3582 = WAIT
  { 3583,	0,	0,	0,	"WBINVD", 0|(1<<TID::UnmodeledSideEffects), 0x9000101ULL, NULL, NULL, NULL, 0 },  // Inst #3583 = WBINVD
  { 3584,	5,	0,	0,	"WINCALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0xff00001aULL, ImplicitList4, ImplicitList60, Barriers8, OperandInfo34 },  // Inst #3584 = WINCALL64m
  { 3585,	1,	0,	0,	"WINCALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0xe800c001ULL, ImplicitList4, ImplicitList60, Barriers8, OperandInfo2 },  // Inst #3585 = WINCALL64pcrel32
  { 3586,	1,	0,	0,	"WINCALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0xff000012ULL, ImplicitList4, ImplicitList60, Barriers8, OperandInfo67 },  // Inst #3586 = WINCALL64r
  { 3587,	0,	0,	0,	"WRMSR", 0|(1<<TID::UnmodeledSideEffects), 0x30000101ULL, NULL, NULL, NULL, 0 },  // Inst #3587 = WRMSR
  { 3588,	6,	0,	0,	"XADD16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xc1000144ULL, NULL, NULL, NULL, OperandInfo11 },  // Inst #3588 = XADD16rm
  { 3589,	2,	1,	0,	"XADD16rr", 0|(1<<TID::UnmodeledSideEffects), 0xc1000143ULL, NULL, NULL, NULL, OperandInfo56 },  // Inst #3589 = XADD16rr
  { 3590,	6,	0,	0,	"XADD32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xc1000104ULL, NULL, NULL, NULL, OperandInfo15 },  // Inst #3590 = XADD32rm
  { 3591,	2,	1,	0,	"XADD32rr", 0|(1<<TID::UnmodeledSideEffects), 0xc1000103ULL, NULL, NULL, NULL, OperandInfo58 },  // Inst #3591 = XADD32rr
  { 3592,	6,	0,	0,	"XADD64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xc1001104ULL, NULL, NULL, NULL, OperandInfo19 },  // Inst #3592 = XADD64rm
  { 3593,	2,	1,	0,	"XADD64rr", 0|(1<<TID::UnmodeledSideEffects), 0xc1001103ULL, NULL, NULL, NULL, OperandInfo60 },  // Inst #3593 = XADD64rr
  { 3594,	6,	0,	0,	"XADD8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0xc0000104ULL, NULL, NULL, NULL, OperandInfo24 },  // Inst #3594 = XADD8rm
  { 3595,	2,	1,	0,	"XADD8rr", 0|(1<<TID::UnmodeledSideEffects), 0xc0000103ULL, NULL, NULL, NULL, OperandInfo83 },  // Inst #3595 = XADD8rr
  { 3596,	1,	0,	0,	"XCHG16ar", 0|(1<<TID::UnmodeledSideEffects), 0x90000042ULL, NULL, NULL, NULL, OperandInfo106 },  // Inst #3596 = XCHG16ar
  { 3597,	7,	1,	0,	"XCHG16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x87000046ULL, NULL, NULL, NULL, OperandInfo13 },  // Inst #3597 = XCHG16rm
  { 3598,	3,	1,	0,	"XCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0x87000045ULL, NULL, NULL, NULL, OperandInfo14 },  // Inst #3598 = XCHG16rr
  { 3599,	1,	0,	0,	"XCHG32ar", 0|(1<<TID::UnmodeledSideEffects), 0x90000002ULL, NULL, NULL, NULL, OperandInfo66 },  // Inst #3599 = XCHG32ar
  { 3600,	7,	1,	0,	"XCHG32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x87000006ULL, NULL, NULL, NULL, OperandInfo17 },  // Inst #3600 = XCHG32rm
  { 3601,	3,	1,	0,	"XCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0x87000005ULL, NULL, NULL, NULL, OperandInfo18 },  // Inst #3601 = XCHG32rr
  { 3602,	1,	0,	0,	"XCHG64ar", 0|(1<<TID::UnmodeledSideEffects), 0x90001002ULL, NULL, NULL, NULL, OperandInfo67 },  // Inst #3602 = XCHG64ar
  { 3603,	7,	1,	0,	"XCHG64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x87001006ULL, NULL, NULL, NULL, OperandInfo21 },  // Inst #3603 = XCHG64rm
  { 3604,	3,	1,	0,	"XCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0x87001005ULL, NULL, NULL, NULL, OperandInfo22 },  // Inst #3604 = XCHG64rr
  { 3605,	7,	1,	0,	"XCHG8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x86000006ULL, NULL, NULL, NULL, OperandInfo26 },  // Inst #3605 = XCHG8rm
  { 3606,	3,	1,	0,	"XCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0x86000005ULL, NULL, NULL, NULL, OperandInfo27 },  // Inst #3606 = XCHG8rr
  { 3607,	1,	0,	0,	"XCH_F", 0|(1<<TID::UnmodeledSideEffects), 0xc8000402ULL, NULL, NULL, NULL, OperandInfo35 },  // Inst #3607 = XCH_F
  { 3608,	0,	0,	0,	"XLAT", 0|(1<<TID::UnmodeledSideEffects), 0xd7000001ULL, NULL, NULL, NULL, 0 },  // Inst #3608 = XLAT
  { 3609,	1,	0,	0,	"XOR16i16", 0|(1<<TID::UnmodeledSideEffects), 0x35006041ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #3609 = XOR16i16
  { 3610,	6,	0,	0,	"XOR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100605eULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #3610 = XOR16mi
  { 3611,	6,	0,	0,	"XOR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300205eULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #3611 = XOR16mi8
  { 3612,	6,	0,	0,	"XOR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x31000044ULL, NULL, ImplicitList1, Barriers1, OperandInfo11 },  // Inst #3612 = XOR16mr
  { 3613,	3,	1,	0,	"XOR16ri", 0, 0x81006056ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #3613 = XOR16ri
  { 3614,	3,	1,	0,	"XOR16ri8", 0, 0x83002056ULL, NULL, ImplicitList1, Barriers1, OperandInfo12 },  // Inst #3614 = XOR16ri8
  { 3615,	7,	1,	0,	"XOR16rm", 0|(1<<TID::MayLoad), 0x33000046ULL, NULL, ImplicitList1, Barriers1, OperandInfo13 },  // Inst #3615 = XOR16rm
  { 3616,	3,	1,	0,	"XOR16rr", 0|(1<<TID::Commutable), 0x31000043ULL, NULL, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #3616 = XOR16rr
  { 3617,	3,	1,	0,	"XOR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x33000045ULL, NULL, ImplicitList1, Barriers1, OperandInfo14 },  // Inst #3617 = XOR16rr_REV
  { 3618,	1,	0,	0,	"XOR32i32", 0|(1<<TID::UnmodeledSideEffects), 0x3500a001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #3618 = XOR32i32
  { 3619,	6,	0,	0,	"XOR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100a01eULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #3619 = XOR32mi
  { 3620,	6,	0,	0,	"XOR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300201eULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #3620 = XOR32mi8
  { 3621,	6,	0,	0,	"XOR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x31000004ULL, NULL, ImplicitList1, Barriers1, OperandInfo15 },  // Inst #3621 = XOR32mr
  { 3622,	3,	1,	0,	"XOR32ri", 0, 0x8100a016ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #3622 = XOR32ri
  { 3623,	3,	1,	0,	"XOR32ri8", 0, 0x83002016ULL, NULL, ImplicitList1, Barriers1, OperandInfo16 },  // Inst #3623 = XOR32ri8
  { 3624,	7,	1,	0,	"XOR32rm", 0|(1<<TID::MayLoad), 0x33000006ULL, NULL, ImplicitList1, Barriers1, OperandInfo17 },  // Inst #3624 = XOR32rm
  { 3625,	3,	1,	0,	"XOR32rr", 0|(1<<TID::Commutable), 0x31000003ULL, NULL, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #3625 = XOR32rr
  { 3626,	3,	1,	0,	"XOR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x33000005ULL, NULL, ImplicitList1, Barriers1, OperandInfo18 },  // Inst #3626 = XOR32rr_REV
  { 3627,	1,	0,	0,	"XOR64i32", 0|(1<<TID::UnmodeledSideEffects), 0x3500b001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #3627 = XOR64i32
  { 3628,	6,	0,	0,	"XOR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8100b01eULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #3628 = XOR64mi32
  { 3629,	6,	0,	0,	"XOR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8300301eULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #3629 = XOR64mi8
  { 3630,	6,	0,	0,	"XOR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x31001004ULL, NULL, ImplicitList1, Barriers1, OperandInfo19 },  // Inst #3630 = XOR64mr
  { 3631,	3,	1,	0,	"XOR64ri32", 0, 0x8100b016ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #3631 = XOR64ri32
  { 3632,	3,	1,	0,	"XOR64ri8", 0, 0x83003016ULL, NULL, ImplicitList1, Barriers1, OperandInfo20 },  // Inst #3632 = XOR64ri8
  { 3633,	7,	1,	0,	"XOR64rm", 0|(1<<TID::MayLoad), 0x33001006ULL, NULL, ImplicitList1, Barriers1, OperandInfo21 },  // Inst #3633 = XOR64rm
  { 3634,	3,	1,	0,	"XOR64rr", 0|(1<<TID::Commutable), 0x31001003ULL, NULL, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #3634 = XOR64rr
  { 3635,	3,	1,	0,	"XOR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x33001005ULL, NULL, ImplicitList1, Barriers1, OperandInfo22 },  // Inst #3635 = XOR64rr_REV
  { 3636,	1,	0,	0,	"XOR8i8", 0|(1<<TID::UnmodeledSideEffects), 0x34002001ULL, NULL, ImplicitList1, Barriers1, OperandInfo2 },  // Inst #3636 = XOR8i8
  { 3637,	6,	0,	0,	"XOR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x8000201eULL, NULL, ImplicitList1, Barriers1, OperandInfo10 },  // Inst #3637 = XOR8mi
  { 3638,	6,	0,	0,	"XOR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0x30000004ULL, NULL, ImplicitList1, Barriers1, OperandInfo24 },  // Inst #3638 = XOR8mr
  { 3639,	3,	1,	0,	"XOR8ri", 0, 0x80002016ULL, NULL, ImplicitList1, Barriers1, OperandInfo25 },  // Inst #3639 = XOR8ri
  { 3640,	7,	1,	0,	"XOR8rm", 0|(1<<TID::MayLoad), 0x32000006ULL, NULL, ImplicitList1, Barriers1, OperandInfo26 },  // Inst #3640 = XOR8rm
  { 3641,	3,	1,	0,	"XOR8rr", 0|(1<<TID::Commutable), 0x30000003ULL, NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #3641 = XOR8rr
  { 3642,	3,	1,	0,	"XOR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0x32000005ULL, NULL, ImplicitList1, Barriers1, OperandInfo27 },  // Inst #3642 = XOR8rr_REV
  { 3643,	7,	1,	0,	"XORPDrm", 0|(1<<TID::MayLoad), 0x57800146ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #3643 = XORPDrm
  { 3644,	3,	1,	0,	"XORPDrr", 0|(1<<TID::Commutable), 0x57800145ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #3644 = XORPDrr
  { 3645,	7,	1,	0,	"XORPSrm", 0|(1<<TID::MayLoad), 0x57400106ULL, NULL, NULL, NULL, OperandInfo28 },  // Inst #3645 = XORPSrm
  { 3646,	3,	1,	0,	"XORPSrr", 0|(1<<TID::Commutable), 0x57400105ULL, NULL, NULL, NULL, OperandInfo29 },  // Inst #3646 = XORPSrr
};
} // End llvm namespace